Index: mptable.c
===================================================================
--- mptable.c	(revision 4027)
+++ mptable.c	(working copy)
@@ -88,13 +88,13 @@
 				smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
 			}
 
-			dword = 0x43c6c643;
+			dword = 0x0030C003; //TODO: Check again and verify if hw:v1 is equal.
 	        	pci_write_config32(dev, 0x7c, dword);
 
-		        dword = 0x81001a00;
+		        dword = 0x2D010A09; //TODO: Check again and verify if hw:v1 is equal.
 		        pci_write_config32(dev, 0x80, dword);
 
-	        	dword = 0xd0001202;
+	        	dword = 0x8E10D202; //TODO: Check again and verify if hw:v1 is equal.
 		        pci_write_config32(dev, 0x84, dword);
 
                 }
@@ -128,33 +128,37 @@
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
 			 bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
 
-        PCI_INT(0,sbdn+1,1, 10); /* SMBus */
         PCI_INT(0,sbdn+2,0, 22); /* USB */
         PCI_INT(0,sbdn+2,1, 23); /* USB */
-        PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
-        PCI_INT(0,sbdn+5,0, 20); /* SATA */
-        PCI_INT(0,sbdn+5,1, 23); /* SATA */
-        PCI_INT(0,sbdn+5,2, 21); /* SATA */
+        PCI_INT(0,sbdn+4,0, 14); /* IDE */
+        PCI_INT(0,sbdn+5,0, 22); /* SATA */
+        PCI_INT(0,sbdn+5,1, 21); /* SATA */
+        PCI_INT(0,sbdn+5,2, 20); /* SATA */
+	PCI_INT(0,sbdn+6,1, 21); /* HD Audio */
 
-        PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
+	/* NOTE: udev renames eth0 to eth1 because of
+	different mac addresses. The coreboot MAC address
+	is stored in src/southbridge/nvidia/mcp55/romstrap.inc
+	*/
+	PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
+	
+	/* TODO: why does the bus nummber increase to 7
+	when using coreboot (proprietary bios bus for
+	pci-e 16x is 2)? 
+	Maybe this is related to get_bus_conf.c #DEBUG# */
+	PCI_INT(2,sbdn+0,0, 16); //PCI-E 16x #2 (black) on hw:v2 
+	PCI_INT(7,sbdn+0,0, 16); //PCI-E 16x #1 (blue) on hw:v2 
 
-	/* The PCIe slots, each on its own bus */
-	for(j=7; j>=2; j--) {
-		if(!bus_mcp55[j]) continue;
-	        for(i=0;i<4;i++) { /* map all functions */
-        	        PCI_INT(j,0,i, 16+(1+j+i)%4);
-        	}
-	}
+	/* TODO: clear out why PCI 0.0a-0.0f are available,
+	while just 0.0f should be enough */
+	
+	PCI_INT(1,sbdn+7,0, 19); /* PCI #1 (near cpu) on hw:v2 */
+	PCI_INT(1,sbdn+8,0, 16); /* PCI #2 (near edge) on hw:v2 */
 
-	/* On bus 1: the physical PCI bus slots...  */
-	for(j=0; j<2; j++) /* on a Rev 1.x board, they are devs 7 and 8 */
-	        for(i=0;i<4;i++) { /* map all functions */
-        	        PCI_INT(1,7+j,i, 16+(3+i+j)%4);
-	        }
 	/* ... and OB FireWire */
 	PCI_INT(1,0x0a,0, 18);
 
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
 	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
Index: cache_as_ram_auto.c
===================================================================
--- cache_as_ram_auto.c	(revision 4027)
+++ cache_as_ram_auto.c	(working copy)
@@ -137,10 +137,10 @@
 #define MCP55_MB_SETUP \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
-        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0xA8,/* GPIO40 PCI_GNT2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0xA8,/* GPIO41 PCI_REQ2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x48,/* GPIP60 FANCTL0 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x48,/* GPIO61 FANCTL1 */
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
