Index: coreboot-v2-fix_implicit_declarations/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- coreboot-v2-fix_implicit_declarations/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	(revision 4097)
+++ coreboot-v2-fix_implicit_declarations/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	(working copy)
@@ -87,30 +87,10 @@
 	return smbus_read_byte(device, address);
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
-#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/via/k8t890/k8t890_early_car.c"
-#include "cpu/amd/car/copy_and_run.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
 void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
-void hard_reset(void)
-{
-	print_info("NO HARD RESET. FIX ME!\n");
-}
-
 void soft_reset(void)
 {
 	uint8_t tmp;
@@ -129,6 +109,26 @@
 	}
 }
 
+#define K8_4RANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "sdram/generic_sdram.c"
+#include "cpu/amd/dualcore/dualcore.c"
+#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+void hard_reset(void)
+{
+	print_info("NO HARD RESET. FIX ME!\n");
+}
+
 unsigned int get_sbdn(unsigned bus)
 {
 	device_t dev;
Index: coreboot-v2-fix_implicit_declarations/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- coreboot-v2-fix_implicit_declarations/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	(revision 4097)
+++ coreboot-v2-fix_implicit_declarations/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	(working copy)
@@ -90,6 +90,10 @@
 	return smbus_read_byte(device, address);
 }
 
+void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
 #define K8_4RANK_DIMM_SUPPORT 1
 
 
@@ -122,10 +126,6 @@
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
 #warning No hard_reset implemented for this board!
 void hard_reset(void)
 {
