Index: svn/src/mainboard/intel/eagleheights/Config.lb
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/Config.lb
+++ svn/src/mainboard/intel/eagleheights/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007-2008 coresystems GmbH
 ##
 ## This program is free software; you can redistribute it and/or
@@ -21,7 +21,7 @@
 
 ##
 ## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-## 
+##
 
 ##
 ## Only use the option table in a normal image
@@ -43,17 +43,15 @@ arch i386 end
 ##
 
 driver mainboard.o
-driver rtl8168.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-if HAVE_SMI_HANDLER smmobject mainboard_smi.o end
 
 if HAVE_ACPI_TABLES
 	object fadt.o
 	object acpi_tables.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dsdt.asl"
-		action  "iasl -p dsdt -tc $(MAINBOARD)/dsdt.asl"
+		depends "$(MAINBOARD)/dsdt.dsl"
+		action  "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl"
 		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
 	end
 	object ./dsdt.o
@@ -93,7 +91,7 @@ end
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/reset16.inc
         ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -111,10 +109,10 @@ ldscript /arch/i386/lib/id.lds
 ##
 ## Setup Cache-As-Ram
 ##
-mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
+mainboardinit cpu/intel/model_1067x/cache_as_ram.inc
 
 ###
-### This is the early phase of coreboot startup 
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -133,140 +131,83 @@ mainboardinit ./auto.inc
 end
 
 ##
-## Include the secondary Configuration files 
+## Include the secondary Configuration files
 ##
 dir /pc80
 config chip.h
 
-chip northbridge/intel/i945
-
-        device apic_cluster 0 on
-                chip cpu/intel/socket_mFCPGA478
-                        device apic 0 on end
-                end
-        end
-
-        device pci_domain 0 on 
-                device pci 00.0 on end # host bridge
-		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-			# register "rom_address" = "0xfffc0000"	# 256 KB image
-			# register "rom_address" = "0xfff80000"	# 512 KB image
-			register "rom_address" = "0xfff00000" # 1 MB image
-		end
-		device pci 02.1 on end # display controller
-
-                chip southbridge/intel/i82801gx
-			register "pirqa_routing" = "0x05"
-			register "pirqb_routing" = "0x07"
-			register "pirqc_routing" = "0x05"
-			register "pirqd_routing" = "0x07"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x06"
-
-			# GPI routing
-			#  0 No effect (default)
-			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
-			#  2 SCI (if corresponding GPIO_EN bit is also set)
-			register "gpi13_routing" = "1"
-
-                        register "ide_legacy_combined" = "0x1"
-                        register "ide_enable_primary" = "0x1"
-                        register "ide_enable_secondary" = "0x0"
-                        register "sata_ahci" = "0x0"
-
-                	device pci 1b.0 on end # High Definition Audio
-                	device pci 1c.0 on end # PCIe
-                	device pci 1c.1 on end # PCIe
-                	device pci 1c.2 on end # PCIe
-			#device pci 1c.3 off end # PCIe port 4
-			#device pci 1c.4 off end # PCIe port 5
-			#device pci 1c.5 off end # PCIe port 6
-                	device pci 1d.0 on end # USB UHCI
-                	device pci 1d.1 on end # USB UHCI
-                	device pci 1d.2 on end # USB UHCI
-                	device pci 1d.3 on end # USB UHCI
-                	device pci 1d.7 on end # USB2 EHCI
-                	device pci 1e.0 on end # PCI bridge
-			#device pci 1e.2 off end # AC'97 Audio 
-			#device pci 1e.3 off end # AC'97 Modem
-                        device pci 1f.0 on # LPC bridge
-                                chip superio/winbond/w83627thg
-					device pnp 2e.0 off		# Floppy
-					end
-					device pnp 2e.1 off		# Parport
-					end
-                                        device pnp 2e.2 on
+chip northbridge/intel/i3100
+        device pci_domain 0 on
+                device pci 00.0 on end # IMCH
+                device pci 00.1 on end # IMCH error status
+                device pci 01.0 on end # IMCH EDMA engine
+                device pci 02.0 on end # PCIe port A/A0
+                device pci 03.0 on end # PCIe port A1
+                chip southbridge/intel/i3100
+                        # PIRQ line -> legacy IRQ mappings
+			register "pirq_a_d" = "0x8b808a8a"
+                        register "pirq_e_h" = "0x85808080"
+
+                        device pci 1c.0 on end # PCIe port B0
+                        device pci 1c.1 off end # PCIe port B1
+                        device pci 1c.2 off end # PCIe port B2
+                        device pci 1c.3 off end # PCIe port B3
+                        device pci 1d.0 on end # USB (UHCI) 1
+                        device pci 1d.1 on end # USB (UHCI) 2
+                        device pci 1d.7 on end # USB (EHCI)
+                        device pci 1e.0 on end # PCI bridge
+			device pci 1e.2 off end # Audio
+			device pci 1e.3 off end # Modem
+                        device pci 1f.0 on     # LPC bridge
+                                chip superio/intel/i3100
+                                        device pnp 4e.4 on # Com1
                                                  io 0x60 = 0x3f8
                                                 irq 0x70 = 4
                                         end
-                                        device pnp 2e.3 on
+                                        device pnp 4e.5 on # Com2
                                                  io 0x60 = 0x2f8
                                                 irq 0x70 = 3
-						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
                                         end
-					device pnp 2e.5 on		# Keyboard+Mouse
-						 io 0x60 = 0x60
-						 io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-						irq 0xf0 = 0x82		# HW accel A20.
-					end
-					device pnp 2e.7 on		# GPIO1, GAME, MIDI
-						 io 0x62 = 0x330
-						irq 0x70 = 9
-					end
-					device pnp 2e.8 on		# GPIO2
-						# all default
-					end
-					device pnp 2e.9 on		# GPIO3/4
-						irq 0x30 = 0x03		# does this work?
-						irq 0xf0 = 0xfb		# set inputs/outputs
-						irq 0xf1 = 0x66
-					end
-					device pnp 2e.a off		# ACPI
-					end
-					device pnp 2e.b on		# HWM
-						 io 0x60 = 0xa00
-						irq 0x70 = 0
-					end
-
                                 end
-                                chip superio/winbond/w83627thg
-                                        device pnp 4e.0 off		# Floppy
-					end
-					device pnp 4e.1 off		# Parport
-					end
-                                        device pnp 4e.2 on		# COM3
-                                                 io 0x60 = 0x3e8
-                                                irq 0x70 = 11
-                                        end
-                                        device pnp 4e.3 on		# COM4
-                                                 io 0x60 = 0x2e8
-                                                irq 0x70 = 10
-                                        end
-					device pnp 4e.5 off		# Keyboard
-					end
-					device pnp 4e.7 off		# GPIO1, GAME, MIDI
-					end
-					device pnp 4e.8 off		# GPIO2
-					end
-					device pnp 4e.9 off		# GPIO3/4
+				chip superio/smsc/smscsuperio
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.2 off	# Serial Port 4
+						io 0x60 = 0x2e8
+						irq 0x70 = 3
+					end
+					device pnp 2e.3 on	# Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 2
+					end
+					device pnp 2e.4 off	# Serial Port 3
+						io 0x60 = 0x3e8
+						irq 0x70 = 4
+					end
+					device pnp 2e.7 on	# PS/2 Keyboard / Mouse
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1    # PS/2 keyboard interrupt
+						irq 0x72 = 12   # PS/2 mouse interrupt
 					end
-					device pnp 4e.a off		# ACPI
+					device pnp 2e.a off     # Runtime registers
+					       io 0x60 = 0x600
 					end
-					device pnp 4e.b off		# HWM
-					end
-                                end
-
+				end
                         end
-			#device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-			#device pci 1f.4 off end # Realtek ID Codec
+                        device pci 1f.2 on end # SATA
+                        device pci 1f.3 on end # SMBus
+			device pci 1f.4 on end # Performance counters
+                end
+        end
+        device apic_cluster 0 on
+                chip cpu/intel/bga956
+                        device apic 0 on end
                 end
         end
 end
+
Index: svn/src/mainboard/intel/eagleheights/Options.lb
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/Options.lb
+++ svn/src/mainboard/intel/eagleheights/Options.lb
@@ -1,6 +1,6 @@
 ##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007-2008 coresystems GmbH
 ##
 ## This program is free software; you can redistribute it and/or
@@ -29,7 +29,6 @@ uses LB_CKS_RANGE_START
 uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
 uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
 uses HAVE_MAINBOARD_RESOURCES
 # SMP
 uses CONFIG_SMP
@@ -51,6 +50,7 @@ uses ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses PAYLOAD_SIZE
 # Build Internals
@@ -70,9 +70,7 @@ uses HAVE_SMI_HANDLER
 uses CONFIG_PCIE_CONFIGSPACE_HOLE
 uses MMCONF_SUPPORT
 uses MMCONF_BASE_ADDRESS
-uses CONFIG_GFXUMA
 uses CONFIG_CBFS
-
 #
 uses MAINBOARD
 uses MAINBOARD_PART_NUMBER
@@ -93,6 +91,8 @@ uses CONFIG_CONSOLE_VGA
 uses CONFIG_VGA_ROM_RUN
 uses CONFIG_PCI_ROM_RUN
 uses DEBUG
+uses CONFIG_VGA
+uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
 # Toolchain
 uses CC
 uses HOSTCC
@@ -132,7 +132,7 @@ default HAVE_FALLBACK_BOOT=1
 ##
 ## Delay timer options
 ## Use timer2
-## 
+##
 default CONFIG_UDELAY_TSC=1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 
@@ -144,20 +144,14 @@ default HAVE_HARD_RESET=1
 ##
 ## Build SMI handler
 ##
-default HAVE_SMI_HANDLER=1
+default HAVE_SMI_HANDLER=0
 
 ##
 ## Leave a hole for mmapped PCIe config space
 ##
-
 default CONFIG_PCIE_CONFIGSPACE_HOLE=1
 default MMCONF_SUPPORT=1
-default MMCONF_BASE_ADDRESS=0xf0000000
-
-##
-## UMA
-##
-default CONFIG_GFXUMA=1
+default MMCONF_BASE_ADDRESS=0xE0000000
 
 ##
 ## Build code to export a programmable irq routing table
@@ -190,14 +184,17 @@ default LB_CKS_RANGE_END=122
 default LB_CKS_LOC=123
 
 #VGA Console
-default CONFIG_CONSOLE_VGA=1
+default CONFIG_CONSOLE_VGA=0
 # There are some network option roms that don't work with
 # coreboot's x86emu. Thus, we only execute the VGA option rom
 # for now:
-default CONFIG_VGA_ROM_RUN=1
+default CONFIG_VGA_ROM_RUN=0
 default CONFIG_PCI_ROM_RUN=0
 default DEBUG=0
 
+#default CONFIG_VGA=0
+#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0
+
 ##
 ## Build code for SMP support
 ## Only worry about 2 micro processors
@@ -224,8 +221,8 @@ default CONFIG_IOAPIC=1
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="986LCD-M"
-default MAINBOARD_VENDOR=     "KONTRON"
+default MAINBOARD_PART_NUMBER="EagleHeights"
+default MAINBOARD_VENDOR=     "Intel"
 
 ###
 ### coreboot layout values
@@ -260,10 +257,13 @@ default _RAMBASE=0x00100000
 ## Load the payload from the ROM
 ##
 default CONFIG_ROM_PAYLOAD=1
+default CONFIG_PRECOMPRESSED_PAYLOAD=1
+default CONFIG_COMPRESSED_PAYLOAD_LZMA=1
+#default CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
 
 ###
 ### Defaults of options that you may want to override in the target config file
-### 
+###
 
 ##
 ## The default compiler
@@ -303,18 +303,18 @@ default TTYS0_LCS=0x3
 ##
 ### Select the coreboot loglevel
 ##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=5
+default  DEFAULT_CONSOLE_LOGLEVEL=7
 ## At a maximum only compile in this level of debugging
 default  MAXIMUM_CONSOLE_LOGLEVEL=9
 
@@ -324,7 +324,7 @@ default MAINBOARD_POWER_ON_AFTER_POWER_F
 
 #
 # CBFS
-# 
+#
 default CONFIG_CBFS=1
 
 ### End Options.lb
Index: svn/src/mainboard/intel/eagleheights/acpi_tables.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/acpi_tables.c
+++ svn/src/mainboard/intel/eagleheights/acpi_tables.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -25,12 +25,13 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include "dmi.h"
+#include "ioapic.h"
 
 extern unsigned char AmlCode[];
 
 typedef struct acpi_oemb {
 	acpi_header_t header;
+#if 0
 	u8  ss;
 	u16 iost;
 	u32 topm;
@@ -54,12 +55,13 @@ typedef struct acpi_oemb {
 	u8  dts1;
 	u8  dts2;
 	u8  mpen;
+#endif
 } __attribute__((packed)) acpi_oemb_t;
 
 void acpi_create_oemb(acpi_oemb_t *oemb)
 {
 	acpi_header_t *header = &(oemb->header);
-	unsigned long tolud;
+	/* unsigned long tolud; */
 
 	memset (oemb, 0, sizeof(oemb));
 
@@ -71,11 +73,11 @@ void acpi_create_oemb(acpi_oemb_t *oemb)
 
 	header->length = sizeof(acpi_oemb_t);
 	header->revision = 1;
-
+#if 0
 	oemb->ss   =   0x09; // ss1 + ss 4
 	oemb->iost = 0x0403; // ??
 
-        tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
+	tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
 	oemb->topm = tolud;
 
 	oemb->roms = 0xfff00000; // 1M hardcoded
@@ -88,51 +90,27 @@ void acpi_create_oemb(acpi_oemb_t *oemb)
 
 	oemb->dmax = 0x87;
 	oemb->hpta = 0x000e36c0;
-
-	header->checksum =
-	    acpi_checksum((void *) oemb, sizeof(acpi_oemb_t));
+#endif
+	header->checksum = acpi_checksum((void *) oemb, sizeof(acpi_oemb_t));
 
 };
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	device_t dev;
-	u32 pciexbar = 0;
-	u32 pciexbar_reg;
-	int max_buses;
+	u64 mmcfg;
 
-	dev = dev_find_device(0x8086, 0x27a0, 0);
+	dev = dev_find_device(0x8086, 0x35B0, 0);	// 0:0x13.0
 	if (!dev)
 		return current;
 
 	// MMCFG not supported or not enabled.
-	pciexbar_reg=pci_read_config32(dev, 0x48);
-
-	if (!(pciexbar_reg & (1 << 0)))
-		return current;
-
-	switch ((pciexbar_reg >> 1) & 3) {
-	case 0: // 256MB
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
-		max_buses = 256;
-		break;
-	case 1: // 128M
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
-		max_buses = 128;
-		break;
-	case 2: // 64M
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
-		max_buses = 64;
-		break;
-	default: // RSVD
-		return current;
-	}
-
-	if (!pciexbar)
+	mmcfg = ((u64) pci_read_config16(dev, 0xce)) << 16;
+	if (!mmcfg)
 		return current;
 
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
-			pciexbar, 0x0, 0x0, max_buses - 1);
+			mmcfg, 0x0, 0x0, 0xff);
 
 	return current;
 }
@@ -148,44 +126,65 @@ void acpi_create_intel_hpet(acpi_hpet_t 
 	/* fill out header fields */
 	memcpy(header->signature, HPET_NAME, 4);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->oem_table_id, "IC      ", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
 	header->revision = 1;
 
 	/* fill out HPET address */
+	// XXX factory bios just puts an address here -- who's right?
 	addr->space_id = 0;	/* Memory */
 	addr->bit_width = 64;
 	addr->bit_offset = 0;
 	addr->addrl = HPET_ADDR & 0xffffffff;
 	addr->addrh = HPET_ADDR >> 32;
 
-	hpet->id = 0x8086a201;	/* Intel */
+	hpet->id = 0x80861234;
 	hpet->number = 0x00;
-	hpet->min_tick = 0x0080;
+	hpet->min_tick = 0x0090;
 
-	header->checksum =
-	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+	header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
 }
 
-
-
-#define IO_APIC_ADDR	0xfec00000UL
+#define IO_APIC0 2
+#define IO_APIC1 3
+#define IO_APIC0_ADDR	0xfec00000UL
+#define IO_APIC1_ADDR	0xfec10000UL
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
+	unsigned int irq_start = 0;
+	device_t dev = 0;
+	struct resource* res = NULL;
+	unsigned char bus_isa;
+
 	/* Local Apic */
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0);
 	// This one is for the second core... Will it hurt?
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1);
 
 	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0);
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC0_ADDR, irq_start);
+	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC1_ADDR, irq_start);
+	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+	dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
+
+	if (dev) {
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+	} else {
+		printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+		bus_isa = 7;
+	}
+
+	/* Map ISA IRQ 0 to IRQ 2 */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, bus_isa, 0, 2, 0);
 
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d);	// high/level
+	/* IRQ9 differs from ISA standard - ours is active high, level-triggered */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d);
 
 	return current;
 }
@@ -223,7 +222,7 @@ unsigned long write_acpi_tables(unsigned
 	/* Align ACPI tables to 16byte */
 	ALIGN_CURRENT;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk_info("ACPI: Writing ACPI tables at %lx.\n", current);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -296,7 +295,7 @@ unsigned long write_acpi_tables(unsigned
 
 	/* We patched up the DSDT, so we need to recalculate the checksum */
 	dsdt->checksum = 0;
-	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
 #endif
 
 	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
@@ -309,15 +308,6 @@ unsigned long write_acpi_tables(unsigned
 
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdt, fadt);
-	printk_debug("current = %lx\n", current);
-
-	printk_debug("ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if HAVE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
 
 	printk_info("ACPI: done.\n");
 	return current;
Index: svn/src/mainboard/intel/eagleheights/auto.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/auto.c
+++ svn/src/mainboard/intel/eagleheights/auto.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -19,19 +19,17 @@
  * MA 02110-1301 USA
  */
 
-// __ROMCC__ means: use "unsigned" for device, not a struct.
-#define __ROMCC__ 
+#define __ROMCC__
+
+#include <delay.h>
 
 #include <stdint.h>
-#include <string.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 
-#include "superio/winbond/w83627thg/w83627thg.h"
-
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
@@ -40,332 +38,210 @@
 #include <cpu/x86/bist.h>
 
 #include "ram/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+#include "southbridge/intel/i3100/i3100_early_smbus.c"
+#include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"
-#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-
-#include "northbridge/intel/i945/udelay.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+#include "eagleheights_fixups.c"
+#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#define SIO_GPIO_BASE 0x680
+#define SIO_XBUS_BASE 0x4880
+
+#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
+#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
+
+#define IA32_PERF_STS     0x198
+#define IA32_PERF_CTL     0x199
+#define MSR_THERM2_CTL    0x19D
+#define IA32_MISC_ENABLES 0x1A0
+
+/* SATA */
+#define SATA_MAP 0x90
+
+#define SATA_MODE_IDE  0x00
+#define SATA_MODE_AHCI 0x01
+
+/* RCBA registers */
+#define RCBA 0xF0
+#define DEFAULT_RCBA 0xFEA00000
+
+#define RCBA_RPC   0x0224 /* 32 bit */
+
+#define RCBA_TCTL  0x3000 /*  8 bit */
+
+#define RCBA_D31IP 0x3100 /* 32 bit */
+#define RCBA_D30IP 0x3104 /* 32 bit */
+#define RCBA_D29IP 0x3108 /* 32 bit */
+#define RCBA_D28IP 0x310C /* 32 bit */
+#define RCBA_D31IR 0x3140 /* 16 bit */
+#define RCBA_D30IR 0x3142 /* 16 bit */
+#define RCBA_D29IR 0x3144 /* 16 bit */
+#define RCBA_D28IR 0x3146 /* 16 bit */
+
+#define RCBA_RTC   0x3400 /* 32 bit */
+#define RCBA_HPTC  0x3404 /* 32 bit */
+#define RCBA_GCS   0x3410 /* 32 bit */
+#define RCBA_BUC   0x3414 /*  8 bit */
+#define RCBA_FD    0x3418 /* 32 bit */
+#define RCBA_PRC   0x341C /* 32 bit */
 
-#include "northbridge/intel/i945/ich7.h"
-static void setup_ich7_gpios(void)
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-	/* TODO: This is highly board specific and should be moved */
-	printk_debug(" GPIOS...");
-	/* General Registers */
-	outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
-	outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
-	outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
-	/* Output Control Registers */
-	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
-	/* Input Control Registers */
-	outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
-	outl(0x000100ff, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
-	outl(0x00000030, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
-	outl(0x00010035, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
+	/* nothing to do */
 }
-
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
+static inline int spd_read_byte(u16 device, u8 address)
 {
 	return smbus_read_byte(device, address);
 }
 
-/* Usually system firmware turns off system memory clock signals to 
- * unused SO-DIMM slots to reduce EMI and power consumption.
- * However, the Kontron 986LCD-M does not like unused clock signals to
- * be disabled. If other similar mainboard occur, it would make sense
- * to make this an entry in the sysinfo structure, and pre-initialize that
- * structure in the mainboard's auto.c main() function. For now a
- * #define will do.
- */
-#define OVERRIDE_CLOCK_DISABLE 1
-
-#define CHANNEL_XOR_RANDOMIZATION 1
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/reset_test.c"
-#include "northbridge/intel/i945/errata.c"
+#include "northbridge/intel/i3100/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/intel/i3100/memory_initialized.c"
+#include "northbridge/intel/i3100/raminit.c"
+#include "sdram/generic_sdram.c"
+#include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
-static void ich7_enable_lpc(void)
-{
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
-	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
-	// Enable COM1/COM2/KBD/SuperIO1+2
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
-	// Enable HWM at 0xa00
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
-	// COM3 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
-	// COM4 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
-	// io 0x300 decode 
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
-}
-
+#if USE_FALLBACK_IMAGE == 1
+#include "southbridge/intel/i3100/cmos_failover.c"
+#endif
 
-/* This box has two superios, so enabling serial becomes slightly excessive.
- * We disable a lot of stuff to make sure that there are no conflicts between
- * the two. Also set up the GPIOs from the beginning. This is the "no schematic
- * but safe anyways" method.
- */
-static void early_superio_config_w83627thg(void)
-{
+void early_config(void) {
 	device_t dev;
-	
-	dev=PNP_DEV(0x2e, W83627THG_SP1);
-	pnp_enter_ext_func_mode(dev);
-
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
-	pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
-	pnp_set_enable(dev, 1);
-
-	dev=PNP_DEV(0x2e, W83627THG_SP2);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
-	pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
-	// pnp_write_config(dev, 0xf1, 4); // IRMODE0
-	pnp_set_enable(dev, 1);
-
-	dev=PNP_DEV(0x2e, W83627THG_KBC);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
-	pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
-	// pnp_write_config(dev, 0xf0, 0x82);
-	pnp_set_enable(dev, 1);
-
-	dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
-	pnp_set_enable(dev, 1);
-
-	dev=PNP_DEV(0x2e, W83627THG_GPIO2);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 1); // Just enable it
-
-	dev=PNP_DEV(0x2e, W83627THG_GPIO3);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
-	pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
-	pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
-
-	dev=PNP_DEV(0x2e, W83627THG_FDC);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-
-	dev=PNP_DEV(0x2e, W83627THG_PP);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-
-	/* Enable HWM */
-	dev=PNP_DEV(0x2e, W83627THG_HWM);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
-	pnp_set_enable(dev, 1);
-
-	pnp_exit_ext_func_mode(dev);
-
-	dev=PNP_DEV(0x4e, W83627THG_SP1);
-	pnp_enter_ext_func_mode(dev);
-
-	pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
-	pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
-	pnp_set_enable(dev, 1);
-
-	dev=PNP_DEV(0x4e, W83627THG_SP2); 
-	pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
-	pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
-	pnp_set_enable(dev, 1);
-
-	dev=PNP_DEV(0x4e, W83627THG_FDC);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-
-	dev=PNP_DEV(0x4e, W83627THG_PP);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-
-	dev=PNP_DEV(0x4e, W83627THG_KBC);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
-	pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
-
-	pnp_exit_ext_func_mode(dev);
-}
-
-static void rcba_config(void)
-{
-	/* Set up virtual channel 0 */
-	//RCBA32(0x0014) = 0x80000001;
-	//RCBA32(0x001c) = 0x03128010;
-
-	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00042210;
-	/* Device 1d interrupt pin register */
-	RCBA32(0x310c) = 0x00214321;
-
-	/* dev irq route register */
-	RCBA16(0x3140) = 0x0132;
-	RCBA16(0x3142) = 0x3241;
-	RCBA16(0x3144) = 0x0237;
-	RCBA16(0x3146) = 0x3210;
-	RCBA16(0x3148) = 0x3210;
-
-	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
-
-	/* Enable upper 128bytes of CMOS */
-	RCBA32(0x3400) = (1 << 2);
-
-	/* Disable unused devices */
-	RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
-	RCBA32(0x3418) |= (1 << 0); // Required.
+	u32 gcs, rpc, fd;
 
-	/* Enable PCIe Root Port Clock Gate */
-	// RCBA32(0x341c) = 0x00000001;
-}
+	/* Enable RCBA */
+	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
 
-static void early_ich7_init(void)
-{
-	uint8_t reg8;
-	uint32_t reg32;
+	/* Disable watchdog */
+	gcs = readl(DEFAULT_RCBA + RCBA_GCS);
+	gcs |= (1 << 5); /* No reset */
+	writel(gcs, DEFAULT_RCBA + RCBA_GCS);
+
+	/* Configure PCIe port B as 4x */
+	rpc = readl(DEFAULT_RCBA + RCBA_RPC);
+	rpc |= (3 << 0);
+	writel(rpc, DEFAULT_RCBA + RCBA_RPC);
+
+	/* Disable Modem, Audio, PCIe ports 2/3/4 */
+	fd = readl(DEFAULT_RCBA + RCBA_FD);
+	fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
+	writel(fd, DEFAULT_RCBA + RCBA_FD);
+
+	/* Enable HPET */
+	writel((1 << 7), DEFAULT_RCBA + RCBA_HPTC);
+
+	/* Improve interrupt routing
+	 * D31:F2 SATA        INTB# -> PIRQD
+	 * D31:F3 SMBUS       INTB# -> PIRQD
+	 * D31:F4 CHAP        INTD# -> PIRQA
+	 * D29:F0 USB1#1      INTA# -> PIRQH
+	 * D29:F1 USB1#2      INTB# -> PIRQD
+	 * D29:F7 USB2        INTA# -> PIRQH
+	 * D28:F0 PCIe Port 1 INTA# -> PIRQE
+	 */
 
-	// program secondary mlt XXX byte?
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+	writew(0x0230, DEFAULT_RCBA + RCBA_D31IR);
+	writew(0x3210, DEFAULT_RCBA + RCBA_D30IR);
+	writew(0x3237, DEFAULT_RCBA + RCBA_D29IR);
+	writew(0x3214, DEFAULT_RCBA + RCBA_D28IR);
 
-	// reset rtc power status
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
-
-	// usb transient disconnect
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
-	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	/* Setup sata mode */
+	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
 }
 
-#if USE_FALLBACK_IMAGE == 1
-#include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
-
 void real_main(unsigned long bist)
 {
-	int boot_mode = 0;
+	/* int boot_mode = 0; */
+
+	static const struct mem_controller mch[] = {
+		{
+			.node_id = 0,
+			.f0 = PCI_DEV(0, 0x00, 0),
+			.f1 = PCI_DEV(0, 0x00, 1),
+			.f2 = PCI_DEV(0, 0x00, 2),
+			.f3 = PCI_DEV(0, 0x00, 3),
+			.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
+			.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+		}
+	};
 
 	if (bist == 0) {
 		enable_lapic();
 	}
 
-	ich7_enable_lpc();
-	early_superio_config_w83627thg();
-
-	/* Set up the console */
+	/* Setup the console */
+	i3100_enable_superio();
+	i3100_enable_serial(0x4E, I3100_SP1, TTYS0_BASE);
 	uart_init();
 	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk_debug("soft reset detected.\n");
-		boot_mode = 1;
-	}
+	/* Perform early board specific init */
+	early_config();
 
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	i945_early_initialization();
+	/* Prevent the TCO timer from rebooting us */
+	i3100_halt_tco_timer();
 
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
-	
-#if DEFAULT_CONSOLE_LOGLEVEL > 8
-	dump_spd_registers();
-#endif
-
-	sdram_initialize(boot_mode);
-
-	/* Perform some initialization that must run before stage2 */
-	early_ich7_init();
-
-	/* This should probably go away. Until now it is required 
-	 * and mainboard specific 
-	 */
-	rcba_config();
 
-	/* Chipset Errata! */
-	fixup_i945_errata();
-
-	/* Initialize the internal PCIe links before we go into stage2 */
-	i945_late_initialization();
+	/* Enable SpeedStep and automatic thermal throttling */
+	{
+		msr_t msr;
+		u16 perf;
 
-#if DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
-	sdram_dump_mchbar_registers();
+		msr = rdmsr(IA32_MISC_ENABLES);
+		msr.lo |= (1 << 3) | (1 << 16);
+		wrmsr(IA32_MISC_ENABLES, msr);
+
+#if 0
+		msr = rdmsr(MSR_THERM2_CTL);
+		msr.lo |= (1 << 16);
+		wrmsr(MSR_THERM2_CTL, msr);
 #endif
 
-	{
-		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		/* Set CPU frequency/voltage to maximum */
 
-		printk_debug("TOM: 0x%08x\n", tom);
-		ram_check(0x00000000, 0x000a0000);
-		ram_check(0x00100000, tom);
+		/* Read performance status register and keep
+		 * bits 47:32, where BUS_RATIO_MAX and VID_MAX
+		 * are encoded
+		 */
+		msr = rdmsr(IA32_PERF_STS);
+		perf = msr.hi & 0x0000ffff;
+
+		/* Write VID_MAX & BUS_RATIO_MAX to
+		 * performance control register
+		 */
+		msr = rdmsr(IA32_PERF_CTL);
+		msr.lo &= 0xffff0000;
+		msr.lo |= perf;
+		wrmsr(IA32_PERF_CTL, msr);
 	}
-#endif
-	MCHBAR16(SSKPD) = 0xCAFE;
+
+	/* Initialize memory */
+	sdram_initialize(ARRAY_SIZE(mch), mch);
 }
 
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
+#include "cpu/intel/model_1067x/cache_as_ram_disable.c"
Index: svn/src/mainboard/intel/eagleheights/chip.h
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/chip.h
+++ svn/src/mainboard/intel/eagleheights/chip.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -20,6 +20,7 @@
  */
 
 extern struct chip_operations mainboard_ops;
+
 struct mainboard_config {
 	int nothing;
 };
Index: svn/src/mainboard/intel/eagleheights/debug.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/debug.c
+++ svn/src/mainboard/intel/eagleheights/debug.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -20,14 +20,133 @@
  */
 
 #define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x53
+#define SMBUS_MEM_DEVICE_END 0x57
 #define SMBUS_MEM_DEVICE_INC 1
 
+static void print_reg(unsigned char index)
+{
+        unsigned char data;
+
+        outb(index, 0x2e);
+        data = inb(0x2f);
+	print_debug("0x");
+	print_debug_hex8(index);
+	print_debug(": 0x");
+	print_debug_hex8(data);
+	print_debug("\r\n");
+        return;
+}
+
+static void xbus_en(void)
+{
+        /* select the XBUS function in the SIO */
+        outb(0x07, 0x2e);
+        outb(0x0f, 0x2f);
+        outb(0x30, 0x2e);
+        outb(0x01, 0x2f);
+	return;
+}
+
+static void setup_func(unsigned char func)
+{
+        /* select the function in the SIO */
+        outb(0x07, 0x2e);
+        outb(func, 0x2f);
+        /* print out the regs */
+        print_reg(0x30);
+        print_reg(0x60);
+        print_reg(0x61);
+        print_reg(0x62);
+        print_reg(0x63);
+        print_reg(0x70);
+        print_reg(0x71);
+        print_reg(0x74);
+        print_reg(0x75);
+        return;
+}
+
+static void siodump(void)
+{
+        int i;
+        unsigned char data;
+
+	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+        for (i=0x10; i<=0x2d; i++) {
+                print_reg((unsigned char)i);
+        }
+#if 0
+        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        setup_func(0x0f);
+        for (i=0xf0; i<=0xff; i++) {
+                print_reg((unsigned char)i);
+        }
+
+        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        setup_func(0x03);
+        print_reg(0xf0);
+
+        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        setup_func(0x02);
+        print_reg(0xf0);
+
+#endif
+        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        setup_func(0x07);
+        for (i=0xf0; i<=0xf8; i++) {
+                print_reg((unsigned char)i);
+        }
+        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        data = inb(0x68a);
+	print_debug("\r\nGPDO 4: 0x");
+	print_debug_hex8(data);
+        data = inb(0x68b);
+	print_debug("\r\nGPDI 4: 0x");
+	print_debug_hex8(data);
+	print_debug("\r\n");
+
+#if 0
+
+        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        setup_func(0x0a);
+        print_reg(0xf0);
+
+        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        setup_func(0x09);
+        print_reg(0xf0);
+        print_reg(0xf1);
+
+        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        setup_func(0x10);
+        print_reg(0xf0);
+        print_reg(0xf1);
+        print_reg(0xf3);
+        print_reg(0xf6);
+        print_reg(0xf7);
+        print_reg(0xfe);
+        print_reg(0xff);
+
+        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        setup_func(0x14);
+        print_reg(0xf0);
+#endif
+        return;
+}
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
 static void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -36,36 +155,65 @@ static void print_pci_devices(void)
 			(((id >> 16) & 0xffff) == 0x0000)) {
 			continue;
 		}
-		printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
-			(dev >> 15) & 0x1f, (dev >> 12) & 7);
-		printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16);
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
 	}
 }
 
 static void dump_pci_device(unsigned dev)
 {
 	int i;
-
-	printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
 
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			print_debug_hex8(i);
+			print_debug_char(':');
 		}
 		val = pci_read_config8(dev, i);
-		printk_debug(" %02x", val);
+		print_debug_char(' ');
+		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			printk_debug("\r\n");
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_bar14(unsigned dev)
+{
+	int i;
+	unsigned long bar;
+
+	print_debug("BAR 14 Dump\r\n");
+
+	bar = pci_read_config32(dev, 0x14);
+	for(i = 0; i <= 0x300; i+=4) {
+#if 0
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+#endif
+		if((i%4)==0) {
+		print_debug("\r\n");
+		print_debug_hex16(i);
+		print_debug_char(' ');
 		}
+		print_debug_hex32(read32(bar + i));
+		print_debug_char(' ');
 	}
+	print_debug("\r\n");
 }
 
 static void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
+	for(dev = PCI_DEV(0, 0, 0);
+		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -78,6 +226,69 @@ static void dump_pci_devices(void)
 	}
 }
 
+#if 0
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+	int i;
+	print_debug("\r\n");
+	for(i = 0; i < 4; i++) {
+		unsigned device;
+		device = ctrl->channel0[i];
+		if (device) {
+			int j;
+			print_debug("dimm: ");
+			print_debug_hex8(i);
+			print_debug(".0: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = smbus_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+		device = ctrl->channel1[i];
+		if (device) {
+			int j;
+			print_debug("dimm: ");
+			print_debug_hex8(i);
+			print_debug(".1: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = smbus_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+	}
+}
+#endif
+
 void dump_spd_registers(void)
 {
         unsigned device;
@@ -85,44 +296,54 @@ void dump_spd_registers(void)
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	printk_debug("\r\ndimm %02x", device);
-		
+        	print_debug("\r\n");
+                print_debug("dimm ");
+		print_debug_hex8(device);
+
                 for(i = 0; (i < 256) ; i++) {
                         if ((i % 16) == 0) {
-				printk_debug("\r\n%02x: ", i);
+				print_debug("\r\n");
+				print_debug_hex8(i);
+				print_debug(": ");
                         }
 			status = smbus_read_byte(device, i);
                         if (status < 0) {
-			         printk_debug("bad device: %02x\r\n", -status);
-			         break; 
+			         print_debug("bad device: ");
+				 print_debug_hex8(-status);
+				 print_debug("\r\n");
+			         break;
 			}
-			printk_debug("%02x ", status);
+			print_debug_hex8(status);
+			print_debug_char(' ');
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
-static void dump_mem(unsigned start, unsigned end)
+void dump_ipmi_registers(void)
 {
-        unsigned i;
-	print_debug("dump_mem:");
-        for(i=start;i<end;i++) {
-		if((i & 0xf)==0) {
-#if CONFIG_USE_INIT
-			printk_debug("\r\n%08x:", i);
-#else	
-			print_debug("\r\n");
-			print_debug_hex32(i);
-			print_debug(":");
-#endif
+        unsigned device;
+        device = 0x42;
+        while(device <= 0x42) {
+                int status = 0;
+                int i;
+        	print_debug("\r\n");
+                print_debug("ipmi ");
+		print_debug_hex8(device);
+
+                for(i = 0; (i < 8) ; i++) {
+			status = smbus_read_byte(device, 2);
+                        if (status < 0) {
+			         print_debug("bad device: ");
+				 print_debug_hex8(-status);
+				 print_debug("\r\n");
+			         break;
+			}
+			print_debug_hex8(status);
+			print_debug_char(' ');
 		}
-#if CONFIG_USE_INIT	
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
-#else
-		print_debug(" ");
-             	print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
-        }
-        print_debug("\r\n");
- }
+		device += SMBUS_MEM_DEVICE_INC;
+		print_debug("\n");
+	}
+}
Index: svn/src/mainboard/intel/eagleheights/dsdt.dsl
===================================================================
--- /dev/null
+++ svn/src/mainboard/intel/eagleheights/dsdt.dsl
@@ -0,0 +1,1079 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001)
+{
+	Scope (\_PR)
+	{
+		Processor (CPU1, 0x01, 0x00000810, 0x06)
+		{
+			OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+			Name (NCPU, 0x80)
+			Name (TYPE, 0x80000000)
+			Name (HNDL, 0x80000000)
+			Name (CFGD, 0x80000000)
+			Name (TBLD, 0x80)
+			Method (_PDC, 1, NotSerialized)
+			{
+			}
+		}
+	}
+
+	Scope (\_PR)
+	{
+		Processor (CPU2, 0x02, 0x00000000, 0x00)
+		{
+			OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+			Name (NCPU, 0x80)
+			Name (TYPE, 0x80000000)
+			Name (HNDL, 0x80000000)
+			Name (CFGD, 0x80000000)
+			Name (TBLD, 0x80)
+			Method (_PDC, 1, NotSerialized)
+			{
+			}
+		}
+	}
+
+	/* For now only define 2 power states:
+	*  - S0 which is fully on
+	*  - S5 which is soft off
+	* Any others would involve declaring the wake up methods.
+	*/
+	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+	Name (PICM, 0x00)
+	Method (_PIC, 1, NotSerialized)
+	{
+		Store (Arg0, PICM)
+	}
+
+	/* System bus */
+	Scope (\_SB)
+	{
+		/* Routing PCI0 */
+		Name (PR00, Package (0x0E)
+		{
+		Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */
+		Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */
+		Package (0x04){0x0002FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0002FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0002FFFF,0x03,LNKD,0x00},
+		Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */
+		Package (0x04){0x0003FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0003FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0003FFFF,0x03,LNKD,0x00},
+		Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */
+			Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */
+			Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */
+		Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */
+			Package (0x04){0x001FFFFF,0x03,LNKA,0x00}  /* CHAP INTD# */
+		})
+		Name (AR00, Package (0x0E)
+		{
+		Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */
+		Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */
+		Package (0x04){0x0002FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0002FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0002FFFF,0x03,0x00,0x13},
+		Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */
+		Package (0x04){0x0003FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0003FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0003FFFF,0x03,0x00,0x13},
+		Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */
+			Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */
+			Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */
+		Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */
+			Package (0x04){0x001FFFFF,0x0D,0x00,0x10}  /* CHAP INTD# */
+		})
+	/* Routing PCIe Port A */
+		Name (PR0A, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,LNKA,0x00},
+			Package (0x04){0xFFFF,0x01,LNKB,0x00},
+			Package (0x04){0xFFFF,0x02,LNKC,0x00},
+			Package (0x04){0xFFFF,0x03,LNKD,0x00}
+		})
+		Name (AR0A, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,0x00,0x10},
+			Package (0x04){0xFFFF,0x01,0x00,0x11},
+			Package (0x04){0xFFFF,0x02,0x00,0x12},
+			Package (0x04){0xFFFF,0x03,0x00,0x13}
+		})
+	/* Routing PCIe Port B */
+		Name (PR0B, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,LNKA,0x00},
+			Package (0x04){0xFFFF,0x01,LNKB,0x00},
+			Package (0x04){0xFFFF,0x02,LNKC,0x00},
+			Package (0x04){0xFFFF,0x03,LNKD,0x00}
+		})
+		Name (AR0B, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,0x00,0x10},
+			Package (0x04){0xFFFF,0x01,0x00,0x11},
+			Package (0x04){0xFFFF,0x02,0x00,0x12},
+			Package (0x04){0xFFFF,0x03,0x00,0x13}
+		})
+	/* Routing Bus PCI */
+	Name (PR01, Package (0x04)
+		{
+		Package (0x04){0x0000FFFF,0x00,LNKA,0x00},
+		Package (0x04){0x0000FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0000FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0000FFFF,0x03,LNKD,0x00},
+	})
+	Name (AR01, Package (0x04)
+		{
+		Package (0x04){0x0000FFFF,0x00,0x00,0x10},
+		Package (0x04){0x0000FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0000FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0000FFFF,0x03,0x00,0x13},
+	})
+
+		Name (PRSA, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared, )
+				{3,4,5,6,7,10,11,12,14,15}
+		})
+		Alias (PRSA, PRSB)
+		Alias (PRSA, PRSC)
+		Alias (PRSA, PRSD)
+		Alias (PRSA, PRSE)
+		Alias (PRSA, PRSF)
+		Alias (PRSA, PRSG)
+		Alias (PRSA, PRSH)
+
+	Device (PCI0)
+	{
+		Name (_HID, EisaId ("PNP0A08"))
+		Name (_CID, EisaId ("PNP0A03"))
+		Name (_ADR, 0x00)
+		Name (_SEG, 0x00)
+		Name (_UID, 0x00)
+		Name (_BBN, 0x00)
+
+		Name (SUPP, 0) /* PCI _OSC Support Field Value */
+		Name (CTRL, 0) /* PCI _OSC Control Field Value */
+
+		Method (_OSC, 4)
+		{
+			/* Check for proper GUID */
+		If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+		{
+			/* Create DWORD-adressable field from the Capabilities Buffer */
+			CreateDWordField (Arg3, 0, CDW1)
+			CreateDWordField (Arg3, 4, CDW2)
+			CreateDWordField (Arg3, 8, CDW3)
+
+			/* Save Capabilities DWord 2 & 3 */
+			Store (CDW2, SUPP)
+			Store (CDW3, CTRL)
+
+			/* Don't care of OS capabilites */
+			/* We support nothing (maybe we should add PCIe Capability Structure Control) */
+			And (CTRL, 0x00, CTRL)
+
+			/* Query flag clear ? */
+			If (Not (And (CDW1, 1)))
+			{
+				/* Nothing to do */
+			}
+
+			/* Unknown revision ? */
+			If (LNotEqual (Arg1, One))
+			{
+				Or (CDW1, 0x08, CDW1)
+			}
+
+			/* Capabilities bits masked ? */
+			If (LNotEqual (CDW3, CTRL))
+			{
+				Or (CDW1, 0x10, CDW1)
+			}
+
+			/* Update DWORD3 in the buffer */
+			Store (CTRL, CDW3)
+
+			Return (Arg3)
+		}
+		Else
+		{
+			/* Unrecognized UUID */
+			Or (CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+		} /* End _OSC */
+
+			Method (_PRT, 0, NotSerialized)
+			{
+				If (PICM)
+				{
+					Return (AR00)
+				}
+
+				Return (PR00)
+			}
+
+		/* PCI Express Port A */
+		Device (EPA0)
+			{
+				Name (_ADR, 0x00020000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0A)
+					}
+
+					Return (PR0A)
+				}
+			}
+
+		/* PCI Express Port A1 */
+			Device (EPA1)
+			{
+				Name (_ADR, 0x00030000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0A)
+					}
+
+					Return (PR0A)
+				}
+			}
+
+		/* PCI Express Port B0 */
+			Device (EPB0)
+			{
+				Name (_ADR, 0x001C0000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0B)
+					}
+
+					Return (PR0B)
+				}
+			}
+
+		/* PCI Bridge */
+			Device (P0P1)
+			{
+				Name (_ADR, 0x001E0000)
+
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR01)
+					}
+
+					Return (PR01)
+				}
+			}
+
+		/* LPC I/F Bridge */
+		Device (ISA) {
+			Name (_ADR, 0x001F0000)
+
+				/* MMCONF */
+				Device (^PCIE)
+				{
+					Name (_HID, EisaId ("PNP0C02"))
+					Name (_UID, 0x11)
+					Name (CRS, ResourceTemplate ()
+					{
+						Memory32Fixed (ReadOnly,
+							0xE0000000,         // Address Base
+							0x10000000,         // Address Length
+							_Y10)
+					})
+					Method (_CRS, 0, NotSerialized)
+					{
+						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)
+						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)
+						Store (0xE0000000, BAS1)
+						Store (0x10000000, LEN1)
+						Return (CRS)
+					}
+				}
+
+		/* PIC */
+				Device (PIC)
+				{
+			Name (_HID, EisaId ("PNP0000"))
+			Name (_CRS, ResourceTemplate()
+			{
+				IO (Decode16,
+				0x0020,
+				0x0020,
+				0x00,
+				0x02,
+				)
+			IO (Decode16,
+				0x00A0,
+				0x00A0,
+				0x00,
+				0x02,
+				)
+			IRQNoFlags ()
+				{2}
+			})
+				}
+
+		/* Real time clock */
+				Device (RTC0)
+				{
+					Name (_HID, EisaId ("PNP0B00"))
+					Name (_CRS, ResourceTemplate ()
+					{
+						IO (Decode16,
+				0x0070,
+				0x0070,
+				0x00,
+				0x02)
+						IRQNoFlags ()
+				{8}
+					})
+				}
+
+				Device (UAR1)
+				{
+					Name (_UID, 0x01)
+					Name (_HID, EisaId ("PNP0501"))
+
+					Method (_PRS, 0, NotSerialized)
+					{
+						Return (CMPR)
+					}
+
+					Name (CMPR, ResourceTemplate ()
+					{
+						StartDependentFn (0x00, 0x00)
+						{
+							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+							IRQNoFlags () {4}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x02F8,0x02F8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+				DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x03E8,0x03E8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+				DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x02E8,0x02E8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						EndDependentFn ()
+					})
+				}
+
+		/* PS/2 keyboard (seems to be important for WinXP install) */
+		Device (KBD)
+		{
+			Name (_HID, EisaId ("PNP0303"))
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0f)
+			}
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+				IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+				IRQNoFlags () {1}
+			})
+			Return (TMP)
+			}
+		}
+
+		/* PS/2 mouse */
+		Device (MOU)
+		{
+			Name (_HID, EisaId ("PNP0F13"))
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0f)
+			}
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (TMP, ResourceTemplate () {
+				IRQNoFlags () {12}
+			})
+			Return (TMP)
+			}
+		}
+
+		/* COM ports of SIO */
+		Device(SIO) {
+				OperationRegion (PT4E, SystemIO, 0x4E, 0x02)
+				Field (PT4E, ByteAcc, NoLock, Preserve)
+				{
+					PO4E,   8,
+					PO4F,   8
+				}
+
+				IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)
+				{
+							Offset (0x07),
+					ILDN,   8,
+							Offset (0x28),
+					SIUI,   8,
+					SIUC,   8,
+							Offset (0x30),
+					IACT,   8,
+							Offset (0x60),
+					IIOH,   8,
+					IIOL,   8,
+							Offset (0x70),
+					IINT,   8
+				}
+
+				Method (IENF, 0, NotSerialized)
+				{
+					Store (0x80, PO4E)
+					Store (0x86, PO4E)
+				}
+
+				Method (IEXF, 0, NotSerialized)
+				{
+					Store (0x68, PO4E)
+					Store (0x08, PO4E)
+				}
+
+				Device (COM1)
+				{
+					Name (_UID, 0x03)
+					Name (_HID, EisaId ("PNP0501"))
+					Method (_STA, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x04, ILDN)
+						Store (IACT, Local0)
+						IEXF ()
+						If (LEqual (Local0, 0xFF))
+						{
+							Return (0x00)
+						}
+
+						If (LEqual (Local0, One))
+						{
+							Return (0x0F)
+						}
+						Else
+						{
+							Return (0x0D)
+						}
+					}
+
+					Method (_DIS, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x04, ILDN)
+						Store (Zero, IACT)
+						IEXF ()
+					}
+
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BFU1, ResourceTemplate ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								_Y03)
+							IRQNoFlags (_Y04)
+								{5}
+						})
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)
+						IENF ()
+						Store (0x04, ILDN)
+						Store (IIOH, Local0)
+						ShiftLeft (Local0, 0x08, Local1)
+						Store (IIOL, Local0)
+						Add (Local1, Local0, Local0)
+						Store (Local0, IMIN)
+						Store (Local0, IMAX)
+						Store (IINT, Local0)
+						IEXF ()
+						Store (0x01, Local1)
+						ShiftLeft (Local1, Local0, IRQ0)
+						Return (BFU1)
+					}
+
+					Name (_PRS, ResourceTemplate ()
+					{
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{5}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x02F8,             // Range Minimum
+								0x02F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{9}
+						}
+				EndDependentFn ()
+					})
+					Method (_SRS, 1, NotSerialized)
+					{
+						CreateByteField (Arg0, 0x02, IOLO)
+						CreateByteField (Arg0, 0x03, IOHI)
+						CreateWordField (Arg0, 0x09, IRQ0)
+						IENF ()
+						Store (0x04, ILDN)
+						Store (Zero, IACT)
+						Store (IOLO, IIOL)
+						Store (IOHI, IIOH)
+						FindSetRightBit (IRQ0, Local0)
+						If (LGreater (Local0, 0x00))
+						{
+							Decrement (Local0)
+						}
+
+						Store (Local0, IINT)
+						Store (One, IACT)
+						IEXF ()
+					}
+				} /* COM1 */
+
+				Device (COM2)
+				{
+					Name (_UID, 0x04)
+					Name (_HID, EisaId ("PNP0501"))
+					Method (_STA, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x05, ILDN)
+						Store (IACT, Local0)
+						IEXF ()
+						If (LEqual (Local0, 0xFF))
+						{
+							Return (0x00)
+						}
+
+						If (LEqual (Local0, One))
+						{
+							Return (0x0F)
+						}
+						Else
+						{
+							Return (0x0D)
+						}
+					}
+
+					Method (_DIS, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x05, ILDN)
+						Store (Zero, IACT)
+						IEXF ()
+					}
+
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BFU1, ResourceTemplate ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								_Y05)
+							IRQNoFlags (_Y06)
+								{9}
+						})
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)
+						IENF ()
+						Store (0x05, ILDN)
+						Store (IIOH, Local0)
+						ShiftLeft (Local0, 0x08, Local1)
+						Store (IIOL, Local0)
+						Add (Local1, Local0, Local0)
+						Store (Local0, IMIN)
+						Store (Local0, IMAX)
+						Store (IINT, Local0)
+						IEXF ()
+						Store (0x01, Local1)
+						ShiftLeft (Local1, Local0, IRQ0)
+						Return (BFU1)
+					}
+
+					Name (_PRS, ResourceTemplate ()
+					{
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{5}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x02F8,             // Range Minimum
+								0x02F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{9}
+						}
+						EndDependentFn ()
+					})
+					Method (_SRS, 1, NotSerialized)
+					{
+						CreateByteField (Arg0, 0x02, IOLO)
+						CreateByteField (Arg0, 0x03, IOHI)
+						CreateWordField (Arg0, 0x09, IRQ0)
+						IENF ()
+						Store (0x05, ILDN)
+						Store (Zero, IACT)
+						Store (IOLO, IIOL)
+						Store (IOHI, IIOH)
+						FindSetRightBit (IRQ0, Local0)
+						If (LGreater (Local0, 0x00))
+						{
+							Decrement (Local0)
+						}
+
+						Store (Local0, IINT)
+						Store (One, IACT)
+						IEXF ()
+					}
+				} /* COM2 */
+		} /* Device SIO */
+		} /* Device ISA */
+	} /* Device PCI 0*/
+	} /* Scope SB */
+
+	OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)
+	Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)
+	{
+		PIRA,   8,
+		PIRB,   8,
+		PIRC,   8,
+		PIRD,   8,
+				Offset (0x08),
+		PIRE,   8,
+		PIRF,   8,
+		PIRG,   8,
+		PIRH,   8
+	}
+
+	Scope (_SB)
+	{
+		Name (BUFA, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared, _Y1C)
+				{15}
+		})
+		CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)
+		Device (LNKA)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x01)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRA, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSA)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRA, 0x80, PIRA)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRA, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRA)
+			}
+		}
+
+		Device (LNKB)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x02)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRB, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSB)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRB, 0x80, PIRB)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRB, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRB)
+			}
+		}
+
+		Device (LNKC)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x03)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRC, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSC)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRC, 0x80, PIRC)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRC, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRC)
+			}
+		}
+
+		Device (LNKD)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x04)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRD, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSD)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRD, 0x80, PIRD)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRD, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRD)
+			}
+		}
+
+		Device (LNKE)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x05)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRE, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSE)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRE, 0x80, PIRE)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRE, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRE)
+			}
+		}
+
+		Device (LNKF)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x06)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRF, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSF)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRF, 0x80, PIRF)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRF, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRF)
+			}
+		}
+
+		Device (LNKG)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x07)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRG, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSG)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRG, 0x80, PIRG)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRG, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRG)
+			}
+		}
+
+		Device (LNKH)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x08)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRH, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSH)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRH, 0x80, PIRH)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRH, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRH)
+			}
+		}
+	}
+}
+
+
Index: svn/src/mainboard/intel/eagleheights/eagleheights_fixups.c
===================================================================
--- /dev/null
+++ svn/src/mainboard/intel/eagleheights/eagleheights_fixups.c
@@ -0,0 +1,16 @@
+#include <arch/romcc_io.h>
+
+static void mch_reset(void)
+{
+        return;
+}
+
+static void mainboard_set_i3100_pll(unsigned bits)
+{
+	return;
+}
+
+static void mainboard_set_i3100_leds(void)
+{
+	return;
+}
Index: svn/src/mainboard/intel/eagleheights/fadt.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/fadt.c
+++ svn/src/mainboard/intel/eagleheights/fadt.c
@@ -23,6 +23,30 @@
 #include <device/pci.h>
 #include <arch/acpi.h>
 
+#define ACPI_PM1_STS        (pmbase + 0x00)
+#define ACPI_PM1_EN         (pmbase + 0x02)
+#define ACPI_PM1_CNT        (pmbase + 0x04)
+#define ACPI_PM1_TMR        (pmbase + 0x08)
+#define ACPI_PROC_CNT       (pmbase + 0x10)
+#define ACPI_LV2            (pmbase + 0x14)
+#define ACPI_GPE0_STS       (pmbase + 0x28)
+#define ACPI_GPE0_EN        (pmbase + 0x2C)
+#define ACPI_SMI_EN         (pmbase + 0x30)
+#define ACPI_SMI_STS        (pmbase + 0x34)
+#define ACPI_ALT_GP_SMI_EN  (pmbase + 0x38)
+#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A)
+#define ACPI_MON_SMI        (pmbase + 0x40)
+#define ACPI_DEVACT_STS     (pmbase + 0x44)
+#define ACPI_DEVTRAP_EN     (pmbase + 0x48)
+#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C)
+#define ACPI_BUS_CYC_TRACK  (pmbase + 0x4E)
+
+#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS
+#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT
+#define ACPI_PM_TMR_BLK   ACPI_PM1_TMR
+#define ACPI_P_BLK        ACPI_PROC_CNT
+#define ACPI_GPE0_BLK     ACPI_GPE0_STS
+
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
@@ -30,19 +54,22 @@ void acpi_create_fadt(acpi_fadt_t * fadt
 
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
-	header->length = 132;
-	header->revision = 2;
+	header->length = 244;
+	header->revision = 1;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
-	header->asl_compiler_revision = 1;
+	header->asl_compiler_revision = 0;
 
 	fadt->firmware_ctrl = (unsigned long) facs;
 	fadt->dsdt = (unsigned long) dsdt;
-	fadt->model = 1;
-	fadt->preferred_pm_profile = 2;
+	fadt->preferred_pm_profile = 7; /* Performance Server */
 	fadt->sci_int = 0x9;
+#if HAVE_SMI_HANDLER == 1
 	fadt->smi_cmd = 0xb2;
+#else
+	fadt->smi_cmd = 0x00;
+#endif
 	fadt->acpi_enable = 0xe1;
 	fadt->acpi_disable = 0x1e;
 	fadt->s4bios_req = 0x0;
@@ -52,37 +79,102 @@ void acpi_create_fadt(acpi_fadt_t * fadt
 	fadt->pm1b_evt_blk = 0x0;
 	fadt->pm1a_cnt_blk = pmbase + 0x4;
 	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x20;
+	fadt->pm2_cnt_blk = 0x0;
 	fadt->pm_tmr_blk = pmbase + 0x8;
 	fadt->gpe0_blk = pmbase + 0x28;
-	fadt->gpe1_blk = 0;
+	fadt->gpe1_blk = 0x0;
 
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 0;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
+	fadt->pm1_evt_len = 0x4;
+	fadt->pm1_cnt_len = 0x2;
+	fadt->pm2_cnt_len = 0x0;
+	fadt->pm_tmr_len = 0x4;
+	fadt->gpe0_blk_len = 0x8;
+	fadt->gpe1_blk_len = 0x0;
+	fadt->gpe1_base = 0x0;
 	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 85;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 0;
+	fadt->p_lvl2_lat = 0x65;
+	fadt->p_lvl3_lat = 0x3e9;
+	fadt->flush_size = 0x400;
+	fadt->flush_stride = 0x10;
+	fadt->duty_offset = 0x1;
+	fadt->duty_width = 0x3;
 	fadt->day_alrm = 0xd;
 	fadt->mon_alrm = 0x00;
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
-	fadt->flags = 0x80a5;
-	// wbinvd is operational
-	// all cpus support c1
-	// sleep button is generic
-	// rtc wakeup/s4 not possible
-	// use platform timer
-	
+	fadt->flags = 0xa5;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = 6;
+	fadt->res3 = 0;
+	fadt->res4 = 0;
+	fadt->res5 = 0;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 32;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = 0x0;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 32;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
 	header->checksum =
 	    acpi_checksum((void *) fadt, header->length);
-
 }
Index: svn/src/mainboard/intel/eagleheights/ioapic.h
===================================================================
--- /dev/null
+++ svn/src/mainboard/intel/eagleheights/ioapic.h
@@ -0,0 +1,2 @@
+#define IOAPIC_I3100 2
+#define INTEL_IOAPIC_NUM_INTERRUPTS 24
Index: svn/src/mainboard/intel/eagleheights/irq_tables.c
===================================================================
--- /dev/null
+++ svn/src/mainboard/intel/eagleheights/irq_tables.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 200x TODO <TODO@TODO>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 9,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x2670,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x4b,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+		{0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x1, 0x0},
+		{0x01, (0x01 << 3) | 0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
Index: svn/src/mainboard/intel/eagleheights/mainboard.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/mainboard.c
+++ svn/src/mainboard/intel/eagleheights/mainboard.c
@@ -21,23 +21,13 @@
 
 
 #include <device/device.h>
-#include <console/console.h>
-#include <boot/tables.h>
 #include "chip.h"
 
-/* in northbridge/intel/i945/northbridge.c */
-extern uint64_t uma_memory_base, uma_memory_size;
-
 int add_mainboard_resources(struct lb_memory *mem)
 {
-	printk_debug("Adding UMA memory area\n");
-	lb_add_memory_range(mem, LB_MEM_RESERVED, 
-		uma_memory_base, uma_memory_size);
-
-	return 0;
 }
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("Kontron 986LCD-M Mainboard")
+	CHIP_NAME("Intel Eagle Heights Mainboard")
 };
 
Index: svn/src/mainboard/intel/eagleheights/mptable.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/mptable.c
+++ svn/src/mainboard/intel/eagleheights/mptable.c
@@ -20,21 +20,63 @@
  */
 
 
-#include <device/device.h>
-#include <device/pci.h>
 #include <console/console.h>
+#include <arch/io.h>
 #include <arch/smp/mpspec.h>
+#include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
 
+// Generate MP-table IRQ numbers for PCI devices.
+#define IO_APIC0 2
+
+#define INT_A	0
+#define INT_B	1
+#define INT_C	2
+#define INT_D	3
+#define PCI_IRQ(dev, intLine)	(((dev)<<2) | intLine)
+
+#define PIRQ_A 16
+#define PIRQ_B 17
+#define PIRQ_C 18
+#define PIRQ_D 19
+#define PIRQ_E 20
+#define PIRQ_F 21
+#define PIRQ_G 22
+#define PIRQ_H 23
+
+// RCBA
+#define RCBA 0xF0
+
+#define RCBA_D31IP 0x3100
+#define RCBA_D30IP 0x3104
+#define RCBA_D29IP 0x3108
+#define RCBA_D28IP 0x310C
+#define RCBA_D31IR 0x3140
+#define RCBA_D30IR 0x3142
+#define RCBA_D29IR 0x3144
+#define RCBA_D28IR 0x3146
+
 void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "COREBOOT";
-        static const char productid[12] = "986LCD-M    ";
+        static const char oem[8] = "Intel   ";
+        static const char productid[12] = "EagleHeights";
         struct mp_config_table *mc;
+	unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
+	unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
 	int i;
-	int max_pci_bus, isa_bus;
+	uint32_t pin, route;
+	device_t dev;
+	struct resource *res;
+	unsigned long rcba;
+
+	dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
+	res = find_resource(dev, RCBA);
+	if (!res) {
+	  return;
+	}
+	rcba = res->base;
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
         memset(mc, 0, sizeof(*mc));
@@ -55,77 +97,220 @@ void *smp_write_config_table(void *v)
 
         smp_write_processors(mc);
 
-	max_pci_bus = 5; // XXX read me from bridges.
-
-	/* ISA bus follows */
-	isa_bus = max_pci_bus + 1;
+	/* Get bus numbers */
+	bus_chipset = 0;
 
-	/* Bus:		Bus ID	Type */
-	for (i=0; i <= max_pci_bus; i++)
-		smp_write_bus(mc, i, "PCI   ");
+	/* PCI */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
+	if (dev) {
+	  bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	  bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+	  bus_isa++;
+	} else {
+	  printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+	  bus_pci = 6;
+	  bus_isa = 7;
+	}
+
+	dev = dev_find_slot(0, PCI_DEVFN(2,0));
+	if(dev) {
+	  bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	} else {
+	  printk_debug("ERROR - could not find PCIe Port A  0:2.0, using defaults\n");
+	  bus_pcie_a = 1;
+	}
+
+	dev = dev_find_slot(0, PCI_DEVFN(3,0));
+	if(dev) {
+	  bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	} else {
+	  printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+	  bus_pcie_a1 = 2;
+	}
+
+	dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));
+	if(dev) {
+	  bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	} else {
+	  printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+	  bus_pcie_b = 3;
+	}
+
+	/*Bus: Bus ID Type*/
+	for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+	  smp_write_bus(mc, bus_num, "PCI   ");
+	}
+	smp_write_bus(mc, bus_isa, "ISA   ");
 
-	smp_write_bus(mc, isa_bus, "ISA   ");
-
-	/* I/O APICs:	APIC ID	Version	State		Address */
+	/*I/O APICs: APIC ID Version State Address*/
 	smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+	/*
+	{
+		device_t dev;
+		struct resource *res;
+		dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
+		if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 3, 0x20, res->base);
+			}
+		}
+		dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
+		if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 4, 0x20, res->base);
+			}
+		}
+                dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 5, 0x20, res->base);
+			}
+                }
+                dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
+                if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_0);
+			if (res) {
+				smp_write_ioapic(mc, 8, 0x20, res->base);
+			}
+                }
+	}
+	*/
+	/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	/* IRQ0 8254 Counter 0, MNT0 */
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  0);
+	/* IRQ1 Keyboard */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  1, IO_APIC0,  1);
+	/* IRQ2 8259 cascade only */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  2);
+	/* IRQ3 COM2, Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  3, IO_APIC0,  3);
+	/* IRQ4 COM1, Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  4, IO_APIC0,  4);
+	/* IRQ5 Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  5, IO_APIC0,  5);
+	/* IRQ6 Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  6, IO_APIC0,  6);
+	/* IRQ7 OPtion for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  7, IO_APIC0,  7);
+	/* IRQ8# RTC, MNT1 */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_EDGE   |MP_IRQ_POLARITY_HIGH,    bus_isa,  8, IO_APIC0,  8);
+	/* IRQ9 Option for PIRQx, SCI, TCO */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  9, IO_APIC0,  9);
+	/* IRQ10 Option for PIRQx, SCI, TCO */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 10);
+	/* IRQ11 Option for PIRQx, SCI, TCO, MMT2 */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 11);
+	/* IRQ12 Mouse, Option for PIRQx */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 12);
+	/* IRQ13 Floating point interrupt generated off of the processor assertion of FERR# */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 13, IO_APIC0, 13);
+	/* IRQ14 PIRQx Sata primary (legacy mode) */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 14, IO_APIC0, 14);
+	/* IRQ15 PIRQx Sata secondary (legacy mode) */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 15, IO_APIC0, 15);
+
+	/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
+	smp_write_intsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
+
+	/* Internal PCI device for i3100 */
+
+	/* EDMA
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A);
+
+	/* PCIe Port A
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A);
+
+	/* PCIe Port A1
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A);
+
+	/* PCIe Port B
+	 */
+	for(i = 0; i < 4; i++) {
+	  pin = (readl(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+	  if(pin > 0) {
+	    pin -= 1;
+	    route = PIRQ_A + ((readw(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
+	  }
+	}
+
+	/* USB 1.1 : device 29, function 0, 1
+	 */
+	for(i = 0; i < 2; i++) {
+	  pin = (readl(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+	  if(pin > 0) {
+	    pin -= 1;
+	    route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+	  }
+	}
+
+	/* USB 2.0 : device 29, function 7
+	*/
+	pin = (readl(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
+	if(pin > 0) {
+	  pin -= 1;
+	  route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+	  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+	}
+
+	/* SATA : device 31 function 2
+	   SMBus : device 31 function 3
+	   Performance counters : device 31 function 4
+	 */
+	for(i = 2; i < 5; i++) {
+	  pin = (readl(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+	  if(pin > 0) {
+	    pin -= 1;
+	    route = PIRQ_A + ((readw(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
+	  }
+	}
+
+	/* SLOTS */
+
+	/* PCIe 4x slot A
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+	/* PCIe 4x slot A1
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+	/* PCIe 4x slot B
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+	/* PCI slot
+	 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
 
-	/* Legacy Interrupts */
-
-	/* I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */	
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
-
-	/* Builtin devices on Bus 0 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
-
-	/* Firewire 4:0.0 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
-
-	/* Old riser card */
-	// riser slot top 5:8.0
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
-	// riser slot middle 5:9.0
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
-	// riser slot bottom 5:a.0
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
-
-	/* New Riser Card */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
-
-	/* Onboard Ethernet */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
-
-	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-
-	printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
 
Index: svn/src/mainboard/intel/eagleheights/reset.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/reset.c
+++ svn/src/mainboard/intel/eagleheights/reset.c
@@ -20,14 +20,43 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#ifndef __ROMCC__
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+#define PCI_DEV_INVALID 0
+
+static inline device_t pci_locate_device(unsigned pci_id, device_t from)
+{
+	return dev_find_device(pci_id >> 16, pci_id & 0xffff, from);
+}
+#endif
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 void hard_reset(void)
 {
-        outb(0x02, 0xcf9);
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }
+
+void full_reset(void)
+{
+	device_t dev;
+	/* Enable power on after power fail... */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_LPC), 0);
+	if (dev != PCI_DEV_INVALID) {
+		unsigned byte;
+		byte = pci_read_config8(dev, 0xa4);
+		byte &= 0xfe;
+		pci_write_config8(dev, 0xa4, byte);
+	}
+	outb(0x0e, 0xcf9);
+}
+
Index: svn/targets/intel/eagleheights/Config.lb
===================================================================
--- svn.orig/targets/intel/eagleheights/Config.lb
+++ svn/targets/intel/eagleheights/Config.lb
@@ -17,24 +17,16 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-target mtarvon
-mainboard intel/mtarvon
+target eagleheights
+mainboard intel/eagleheights
 
 ## ROM_SIZE is the total number of bytes allocated for coreboot use
 ## (normal AND fallback images and payloads).
-option ROM_SIZE = 2 * 1024 * 1024
-
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option ROM_IMAGE_SIZE = 128 * 1024
-
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image
-## (including payload) will use
-option FALLBACK_SIZE = ROM_SIZE
+option ROM_SIZE = 1024 * 1024
 
 romimage "fallback"
 	option USE_FALLBACK_IMAGE=1
-	payload /tmp/filo.elf
+	payload ../payload.elf
 end
 
 buildrom ./coreboot.rom ROM_SIZE "fallback"
