Index: cbv2/src/console/usbdebug_direct_console.c
===================================================================
--- cbv2.orig/src/console/usbdebug_direct_console.c
+++ cbv2/src/console/usbdebug_direct_console.c
@@ -53,7 +53,7 @@ static void dbgp_init(void)
 	 * debug_info data structure to our version defined above. */
 
 	dbg_infox = (struct ehci_debug_info *)
-		((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info));
+		((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
 
 	memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info));
 }
Index: cbv2/src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- cbv2.orig/src/cpu/amd/car/cache_as_ram.inc
+++ cbv2/src/cpu/amd/car/cache_as_ram.inc
@@ -246,7 +246,7 @@ clear_fixed_var_mtrr_out:
 	/* enable memory access for first MBs using top_mem */
 	movl	$TOP_MEM, %ecx
 	xorl	%edx, %edx
-	movl	$(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
+	movl	$(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
 	wrmsr
 #endif /*  CONFIG_USE_FAILOVER_IMAGE == 1*/
 
Index: cbv2/src/cpu/amd/car/clear_init_ram.c
===================================================================
--- cbv2.orig/src/cpu/amd/car/clear_init_ram.c
+++ cbv2/src/cpu/amd/car/clear_init_ram.c
@@ -9,15 +9,15 @@ static void __attribute__((noinline)) cl
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
-	clear_memory( CONFIG_RAMBASE,  (CONFIG_LB_MEM_TOPK << 10) -  CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
+	clear_memory( CONFIG_RAMBASE,  (CONFIG_RAMTOP) -  CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
 #else
-        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE));
+        clear_memory(0,  ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
 #endif
 }
 
 /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
 static void set_init_ram_access(void)
 {
-	set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, MTRR_TYPE_WRBACK);
+	set_var_mtrr(0, 0x00000000,CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 }
 
Index: cbv2/src/cpu/amd/car/post_cache_as_ram.c
===================================================================
--- cbv2.orig/src/cpu/amd/car/post_cache_as_ram.c
+++ cbv2/src/cpu/amd/car/post_cache_as_ram.c
@@ -76,14 +76,14 @@ static void post_cache_as_ram(void)
         );
 #endif
 
-        memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
-//        dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+        memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
+//        dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
         __asm__ volatile (
                 /* set new esp */ /* before CONFIG_RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
         ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
 #if 0
         __asm__ volatile (
@@ -102,10 +102,10 @@ static void post_cache_as_ram(void)
 	disable_cache_as_ram_bsp();  
 
         print_debug("Clearing initial memory region: ");
-        clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
+        clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
         print_debug("Done\r\n");
 
-//	dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+//	dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
 #ifndef CONFIG_MEM_TRAIN_SEQ
 #define CONFIG_MEM_TRAIN_SEQ 0
@@ -113,7 +113,7 @@ static void post_cache_as_ram(void)
         set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
 #if CONFIG_MEM_TRAIN_SEQ == 1
-//	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+//	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         // wait for ap memory to trained
 //        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
Index: cbv2/src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- cbv2.orig/src/cpu/amd/model_fxx/model_fxx_init.c
+++ cbv2/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -33,7 +33,7 @@
 void cpus_ready_for_init(void)
 {
 #if CONFIG_MEM_TRAIN_SEQ == 1
-        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
         // wait for ap memory to trained
         wait_all_core0_mem_trained(sysinfox);
 #endif
@@ -182,7 +182,7 @@ static void set_init_ecc_mtrrs(void)
 	msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
 	wrmsr(MTRRphysBase_MSR(0), msr);
 	msr.hi = 0x000000ff;
-	msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
+	msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
 	wrmsr(MTRRphysMask_MSR(0), msr);
 
 	/* Set the default type to write combining */
Index: cbv2/src/cpu/amd/mtrr/amd_earlymtrr.c
===================================================================
--- cbv2.orig/src/cpu/amd/mtrr/amd_earlymtrr.c
+++ cbv2/src/cpu/amd/mtrr/amd_earlymtrr.c
@@ -38,7 +38,7 @@ static void do_amd_early_mtrr_init(const
 
         /* Enable memory access for 0 - 1MB using top_mem */
         msr.hi = 0;
-        msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
+        msr.lo = (((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
         wrmsr(TOP_MEM, msr);
 
 #if defined(CONFIG_XIP_ROM_SIZE)
Index: cbv2/src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- cbv2.orig/src/cpu/x86/lapic/lapic_cpu_init.c
+++ cbv2/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -252,10 +252,10 @@ int start_cpu(device_t cpu)
 	} else {
 		// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
 		stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
-#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
+#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP)
 		#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
 #endif
-		if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
+		if(stack_end > (CONFIG_RAMTOP)) {
 			printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
 			die("Can not go on\n");
 		}
Index: cbv2/src/cpu/x86/pae/pgtbl.c
===================================================================
--- cbv2.orig/src/cpu/x86/pae/pgtbl.c
+++ cbv2/src/cpu/x86/pae/pgtbl.c
@@ -62,10 +62,10 @@ void *map_2M_page(unsigned long page) 
 	struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M
 
 	unsigned x_end = 0x100000 + sizeof(struct pg_table) * CONFIG_MAX_CPUS;
-#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
+#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP)
                 #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n"
 #endif
-	if(x_end > (CONFIG_LB_MEM_TOPK<<10)) {
+	if(x_end > (CONFIG_RAMTOP)) {
                         printk_debug("map_2M_page: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", x_end>>10);
                         die("Can not go on");
 	}
Index: cbv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/amd/serengeti_cheetah/apc_auto.c
+++ cbv2/src/mainboard/amd/serengeti_cheetah/apc_auto.c
@@ -75,7 +75,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
+++ cbv2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
@@ -74,7 +74,7 @@
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/asus/m2v-mx_se/mainboard.c
===================================================================
--- cbv2.orig/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ cbv2/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -40,7 +40,7 @@ int add_mainboard_resources(struct lb_me
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
-		CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE));
+		CONFIG_RAMBASE, ((CONFIG_RAMTOP) - CONFIG_RAMBASE));
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE);
 #endif
Index: cbv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
+++ cbv2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
@@ -89,7 +89,7 @@ static void post_code(uint8_t value) {
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/gigabyte/m57sli/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/gigabyte/m57sli/apc_auto.c
+++ cbv2/src/mainboard/gigabyte/m57sli/apc_auto.c
@@ -87,7 +87,7 @@ static void post_code(uint8_t value) {
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/msi/ms7260/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/msi/ms7260/apc_auto.c
+++ cbv2/src/mainboard/msi/ms7260/apc_auto.c
@@ -63,7 +63,7 @@ void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
 				    CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) -
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) -
 				     CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/nvidia/l1_2pvv/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/nvidia/l1_2pvv/apc_auto.c
+++ cbv2/src/mainboard/nvidia/l1_2pvv/apc_auto.c
@@ -87,7 +87,7 @@ static void post_code(uint8_t value) {
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/supermicro/h8dme/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/supermicro/h8dme/apc_auto.c
+++ cbv2/src/mainboard/supermicro/h8dme/apc_auto.c
@@ -95,7 +95,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/supermicro/h8dmr/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/supermicro/h8dmr/apc_auto.c
+++ cbv2/src/mainboard/supermicro/h8dmr/apc_auto.c
@@ -95,7 +95,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
+++ cbv2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
@@ -95,7 +95,7 @@ static inline unsigned get_nodes(void)
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/tyan/s2912/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2912/apc_auto.c
+++ cbv2/src/mainboard/tyan/s2912/apc_auto.c
@@ -76,7 +76,7 @@
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/mainboard/tyan/s2912_fam10/apc_auto.c
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2912_fam10/apc_auto.c
+++ cbv2/src/mainboard/tyan/s2912_fam10/apc_auto.c
@@ -76,7 +76,7 @@
 void hardwaremain(int ret_addr)
 {
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 
 	struct node_core_id id;
 
Index: cbv2/src/northbridge/amd/amdfam10/amdfam10_acpi.c
===================================================================
--- cbv2.orig/src/northbridge/amd/amdfam10/amdfam10_acpi.c
+++ cbv2/src/northbridge/amd/amdfam10/amdfam10_acpi.c
@@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned lo
 	/* fill the first 8 byte with that num */
 	/* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
 
-	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	u8 *ln = sysinfox->ln;
 
 
Index: cbv2/src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- cbv2.orig/src/northbridge/amd/amdfam10/northbridge.c
+++ cbv2/src/northbridge/amd/amdfam10/northbridge.c
@@ -806,7 +806,7 @@ static void disable_hoist_memory(unsigne
 	u32 hole_sizek;
 
 	u32 one_DCT;
-	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 	struct mem_info *meminfo;
 	meminfo = &sysinfox->meminfo[i];
 
@@ -1065,7 +1065,7 @@ static void pci_domain_set_resources(dev
 				#if CONFIG_AMDMCT == 0
 				#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 				if(reset_memhole) {
-					struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+					struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
 					struct mem_info *meminfo;
 					meminfo = &sysinfox->meminfo[i];
 					sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes);
Index: cbv2/src/northbridge/amd/amdk8/raminit_f_dqs.c
===================================================================
--- cbv2.orig/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ cbv2/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -2096,7 +2096,7 @@ static void copy_and_run_ap_code_in_car(
 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
 {
 	if(coreid) return; // only do it on core0
-	struct sys_info *sysinfox = (void*)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfox = (void*)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	wait_till_sysinfo_in_ram(); // use pci to get it
 
 	if(sysinfox->mem_trained[nodeid] == 0x80) {
Index: cbv2/src/pc80/usbdebug_direct_serial.c
===================================================================
--- cbv2.orig/src/pc80/usbdebug_direct_serial.c
+++ cbv2/src/pc80/usbdebug_direct_serial.c
@@ -45,7 +45,7 @@ void usbdebug_direct_ram_tx_byte(unsigne
 
 	/* "Find" dbg_info structure in RAM */
 	dbg_info = (struct ehci_debug_info *)
-	    ((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info));
+	    ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
 
 	if (dbg_info->ehci_debug) {
 		dbgp_bulk_write_x(dbg_info, &data, 1);
Index: cbv2/src/cpu/x86/mtrr/earlymtrr.c
===================================================================
--- cbv2.orig/src/cpu/x86/mtrr/earlymtrr.c
+++ cbv2/src/cpu/x86/mtrr/earlymtrr.c
@@ -75,7 +75,7 @@ static void cache_lbmem(int type)
 {
 	/* Enable caching for 0 - 1MB using variable mtrr */
 	disable_cache();
-	set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type);
+	set_var_mtrr(0, 0x00000000,CONFIG_RAMTOP, type);
 	enable_cache();
 }
 
