Index: cbv2/src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ cbv2/src/mainboard/amd/serengeti_cheetah/Options.lb
@@ -80,7 +80,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -107,7 +107,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ cbv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -98,7 +98,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_PCI_BUS_SEGN_BITS
 
@@ -135,7 +135,7 @@ default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
 #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
-default CONFIG_LB_MEM_TOPK=16384
+default CONFIG_RAMTOP=16384*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/asus/a8v-e_se/Options.lb
+++ cbv2/src/mainboard/asus/a8v-e_se/Options.lb
@@ -41,7 +41,7 @@ uses CONFIG_XIP_ROM_BASE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
 # uses CONFIG_USE_OPTION_TABLE
-# uses CONFIG_LB_MEM_TOPK
+# uses CONFIG_RAMTOP
 uses CONFIG_GENERATE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
 uses CONFIG_LB_CKS_RANGE_START
@@ -147,7 +147,7 @@ default CONFIG_ROM_IMAGE_SIZE = 64 * 102
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 256 * 1024
 # More 1M for pgtbl.
-# default CONFIG_LB_MEM_TOPK = 2048
+# default CONFIG_RAMTOP = 2048*1024
 default CONFIG_RAMBASE = 0x00004000
 # default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 default CONFIG_ROM_PAYLOAD = 1
Index: cbv2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/asus/m2v-mx_se/Options.lb
+++ cbv2/src/mainboard/asus/m2v-mx_se/Options.lb
@@ -41,7 +41,7 @@ uses CONFIG_XIP_ROM_BASE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
 uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_GENERATE_ACPI_TABLES
 uses CONFIG_HAVE_MAINBOARD_RESOURCES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -151,7 +151,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_V
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 256 * 1024
 # More 1M for pgtbl.
-default CONFIG_LB_MEM_TOPK = 32768
+default CONFIG_RAMTOP = 32768*1024
 # to 1MB
 default CONFIG_RAMBASE = 0x1F00000
 default CONFIG_USE_OPTION_TABLE = 0
Index: cbv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ cbv2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
@@ -105,7 +105,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -135,7 +135,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/gigabyte/m57sli/Options.lb
+++ cbv2/src/mainboard/gigabyte/m57sli/Options.lb
@@ -105,7 +105,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -136,7 +136,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Set-up automatic fan control
Index: cbv2/src/mainboard/hp/dl145_g3/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/hp/dl145_g3/Options.lb
+++ cbv2/src/mainboard/hp/dl145_g3/Options.lb
@@ -102,7 +102,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -121,7 +121,7 @@ default CONFIG_ROM_SIZE=524288
 default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/intel/truxton/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/intel/truxton/Options.lb
+++ cbv2/src/mainboard/intel/truxton/Options.lb
@@ -35,7 +35,7 @@ uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE
@@ -157,9 +157,9 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_RAMBASE=0x00100000
 
 ##
-## in order to have coreboot running at 0x100000, TOPK has to be set
+## in order to have coreboot running at 0x100000, RAMTOP has to be set
 ##
-default CONFIG_LB_MEM_TOPK = 2*1024*1024
+default CONFIG_RAMTOP = 2*1024*1024
 
 ##
 ## Load the payload from the ROM
Index: cbv2/src/mainboard/iwill/dk8_htx/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/iwill/dk8_htx/Options.lb
+++ cbv2/src/mainboard/iwill/dk8_htx/Options.lb
@@ -80,7 +80,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -109,7 +109,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/msi/ms7260/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/msi/ms7260/Options.lb
+++ cbv2/src/mainboard/msi/ms7260/Options.lb
@@ -91,7 +91,7 @@ uses CONFIG_ENABLE_APIC_EXT_ID
 uses CONFIG_APIC_ID_OFFSET
 uses CONFIG_LIFT_BSP_APIC_ID
 uses CONFIG_PCI_64BIT_PREF_MEM
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_AP_CODE_IN_CAR
 uses CONFIG_MEM_TRAIN_SEQ
 uses CONFIG_WAIT_BEFORE_CPUS_INIT
@@ -100,7 +100,7 @@ uses CONFIG_USE_PRINTK_IN_CAR
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_FAILOVER_SIZE = 4 * 1024
-default CONFIG_LB_MEM_TOPK = 2048	# 1MB more for pgtbl.
+default CONFIG_RAMTOP = 2048*1024	# 1MB more for pgtbl.
 default CONFIG_HAVE_FALLBACK_BOOT = 1
 default CONFIG_HAVE_FAILOVER_BOOT = 1
 default CONFIG_HAVE_HARD_RESET = 1
Index: cbv2/src/mainboard/msi/ms9185/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/msi/ms9185/Options.lb
+++ cbv2/src/mainboard/msi/ms9185/Options.lb
@@ -101,7 +101,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_USE_PRINTK_IN_CAR
 
 ###
@@ -118,7 +118,7 @@ default CONFIG_ROM_SIZE=524288
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ cbv2/src/mainboard/nvidia/l1_2pvv/Options.lb
@@ -103,7 +103,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -133,7 +133,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/supermicro/h8dme/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/supermicro/h8dme/Options.lb
+++ cbv2/src/mainboard/supermicro/h8dme/Options.lb
@@ -104,7 +104,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -137,7 +137,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/supermicro/h8dmr/Options.lb
+++ cbv2/src/mainboard/supermicro/h8dmr/Options.lb
@@ -102,7 +102,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -130,7 +130,7 @@ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/supermicro/h8dmr_fam10/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/supermicro/h8dmr_fam10/Options.lb
+++ cbv2/src/mainboard/supermicro/h8dmr_fam10/Options.lb
@@ -99,7 +99,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_UNCOMPRESSED
 
@@ -132,7 +132,7 @@ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_
 default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=16384
+default CONFIG_RAMTOP=16384*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/tyan/s2895/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2895/Options.lb
+++ cbv2/src/mainboard/tyan/s2895/Options.lb
@@ -80,7 +80,7 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
@@ -95,7 +95,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/tyan/s2912/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2912/Options.lb
+++ cbv2/src/mainboard/tyan/s2912/Options.lb
@@ -103,7 +103,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_AP_CODE_IN_CAR
 
@@ -133,7 +133,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_RAMTOP=2048*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/tyan/s2912_fam10/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2912_fam10/Options.lb
+++ cbv2/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -101,7 +101,7 @@ uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 
 uses CONFIG_PCI_BUS_SEGN_BITS
 
@@ -135,7 +135,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_RO
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=16384
+default CONFIG_RAMTOP=16384*1024
 
 ##
 ## Build code for the fallback boot
Index: cbv2/src/mainboard/via/epia-n/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/via/epia-n/Options.lb
+++ cbv2/src/mainboard/via/epia-n/Options.lb
@@ -34,7 +34,7 @@ uses CONFIG_MAINBOARD_VENDOR
 uses CONFIG_MAINBOARD_PART_NUMBER
 uses COREBOOT_EXTRA_VERSION
 uses CONFIG_ARCH
-uses CONFIG_LB_MEM_TOPK
+uses CONFIG_RAMTOP
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
@@ -73,7 +73,7 @@ uses CONFIG_EPIA_VT8237R_INIT
 uses CONFIG_HAVE_MAINBOARD_RESOURCES
 
 default CONFIG_EPIA_VT8237R_INIT = 1
-#default CONFIG_LB_MEM_TOPK = 4 * 1024
+#default CONFIG_RAMTOP = 4 * 1024*1024
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_COMPRESS = 1
 default CONFIG_IOAPIC = 1
Index: cbv2/src/Kconfig
===================================================================
--- cbv2.orig/src/Kconfig
+++ cbv2/src/Kconfig
@@ -134,9 +134,9 @@ config MMCONF_SUPPORT
 	bool
 	default n
 
-config LB_MEM_TOPK
+config RAMTOP
 	hex
-	default 0x800
+	default 0x200000
 
 config COMPRESSED_PAYLOAD_LZMA
 	bool
Index: cbv2/src/config/Options.lb
===================================================================
--- cbv2.orig/src/config/Options.lb
+++ cbv2/src/config/Options.lb
@@ -360,11 +360,11 @@ define CONFIG_UNCOMPRESSED
 	export always
 	comment "Set for uncompressed image"
 end
-define CONFIG_LB_MEM_TOPK
+define CONFIG_RAMTOP
 	format "%d"
-	default 2048
+	default 2048*1024
 	export always
-	comment "Kilobytes of memory to initialized before executing code from RAM"
+	comment "Highest RAM that coreboot_ram will use"
 end
 define CONFIG_HAVE_OPTION_TABLE
 	default 0
Index: cbv2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
===================================================================
--- cbv2.orig/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
+++ cbv2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
@@ -95,9 +95,9 @@ config AMD_UCODE_PATCH_FILE
 	default "mc_patch_01000095.h"
 	depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
 
-config LB_MEM_TOPK
+config RAMTOP
 	hex
-	default 0x4000
+	default 0x1000000
 	depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
 
 config HEAP_SIZE
Index: cbv2/src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/asus/a8n_e/Options.lb
+++ cbv2/src/mainboard/asus/a8n_e/Options.lb
@@ -93,7 +93,6 @@ uses CONFIG_HT_CHAIN_UNITID_BASE
 uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_LB_MEM_TOPK
 uses CONFIG_USE_PRINTK_IN_CAR
 
 default CONFIG_ROM_SIZE = 512 * 1024
Index: cbv2/src/mainboard/msi/ms7135/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/msi/ms7135/Options.lb
+++ cbv2/src/mainboard/msi/ms7135/Options.lb
@@ -99,9 +99,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
-
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ## ---> 512 Kbytes 
 default CONFIG_ROM_SIZE=(512*1024)
Index: cbv2/src/mainboard/tyan/s2885/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2885/Options.lb
+++ cbv2/src/mainboard/tyan/s2885/Options.lb
@@ -68,8 +68,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
 ###
 ### Build options
 ###
Index: cbv2/src/mainboard/tyan/s2891/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2891/Options.lb
+++ cbv2/src/mainboard/tyan/s2891/Options.lb
@@ -77,8 +77,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=512*1024
 
Index: cbv2/src/mainboard/tyan/s2892/Options.lb
===================================================================
--- cbv2.orig/src/mainboard/tyan/s2892/Options.lb
+++ cbv2/src/mainboard/tyan/s2892/Options.lb
@@ -71,8 +71,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
-uses CONFIG_LB_MEM_TOPK
-
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 
