Index: svn/src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- svn.orig/src/cpu/amd/model_10xxx/init_cpus.c
+++ svn/src/cpu/amd/model_10xxx/init_cpus.c
@@ -473,8 +473,8 @@ static void start_node(u8 node)
 	/* Enable routing table */
 	printk_debug("Start node %02x", node);
 
-#if CONFIG_CAR_FAM10 == 1
-	/* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
+	/* For FAM10 support, we need to set Dram base/limit for the new node */
 	pci_write_config32(NODE_MP(node), 0x44, 0);
 	pci_write_config32(NODE_MP(node), 0x40, 3);
 #endif
Index: svn/src/config/Options.lb
===================================================================
--- svn.orig/src/config/Options.lb
+++ svn/src/config/Options.lb
@@ -299,11 +299,6 @@ define CONFIG_USE_DCACHE_RAM
 	export always
 	comment "Use data cache as temporary RAM if possible"
 end
-define CONFIG_CAR_FAM10
-	default 0
-	export always
-	comment "AMD family 10 CAR requires additional setup"
-end
 define CONFIG_DCACHE_RAM_BASE
 	default 0xc0000
 	format "0x%x"
Index: svn/src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- svn.orig/src/cpu/amd/car/cache_as_ram.inc
+++ svn/src/cpu/amd/car/cache_as_ram.inc
@@ -24,7 +24,7 @@
 /* leave some space for global variable to pass to RAM stage */
 #define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 
-/* for CONFIG_CAR_FAM10 */
+/* for CAR with FAM10 */
 #define CacheSizeAPStack 0x400 /* 1K */
 
 #define MSR_FAM10      0xC001102A
Index: svn/src/cpu/amd/socket_AM2r2/Config.lb
===================================================================
--- svn.orig/src/cpu/amd/socket_AM2r2/Config.lb
+++ svn/src/cpu/amd/socket_AM2r2/Config.lb
@@ -27,7 +27,6 @@ uses CONFIG_CPU_SOCKET_TYPE
 uses CONFIG_CBB
 uses CONFIG_CDB
 uses CONFIG_PCI_BUS_SEGN_BITS
-uses CONFIG_CAR_FAM10
 
 config chip.h
 
@@ -39,8 +38,6 @@ default CONFIG_EXT_CONF_SUPPORT=0
 default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
 default CONFIG_CPU_SOCKET_TYPE=0x11
 
-default CONFIG_CAR_FAM10=1
-
 if CONFIG_EXT_RT_TBL_SUPPORT
 	default CONFIG_CBB=0xff
 	default CONFIG_CDB=0
Index: svn/src/cpu/amd/socket_AM2r2/Kconfig
===================================================================
--- svn.orig/src/cpu/amd/socket_AM2r2/Kconfig
+++ svn/src/cpu/amd/socket_AM2r2/Kconfig
@@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_AM2R2
 	bool
 	select CPU_AMD_MODEL_10XXX
 	select HT3_SUPPORT
-	select CAR_FAM10
 
 config CPU_SOCKET_TYPE
 	hex
Index: svn/src/cpu/amd/socket_F_1207/Config.lb
===================================================================
--- svn.orig/src/cpu/amd/socket_F_1207/Config.lb
+++ svn/src/cpu/amd/socket_F_1207/Config.lb
@@ -27,7 +27,6 @@ uses CONFIG_CPU_SOCKET_TYPE
 uses CONFIG_CBB
 uses CONFIG_CDB
 uses CONFIG_PCI_BUS_SEGN_BITS
-uses CONFIG_CAR_FAM10
 
 config chip.h
 
@@ -39,8 +38,6 @@ default CONFIG_EXT_CONF_SUPPORT=0
 default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
 default CONFIG_CPU_SOCKET_TYPE=0x10
 
-default CONFIG_CAR_FAM10=1
-
 if CONFIG_EXT_RT_TBL_SUPPORT
 	default CONFIG_CBB=0xff
 	default CONFIG_CDB=0
Index: svn/src/cpu/amd/socket_F_1207/Kconfig
===================================================================
--- svn.orig/src/cpu/amd/socket_F_1207/Kconfig
+++ svn/src/cpu/amd/socket_F_1207/Kconfig
@@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_F_1207
 	bool
 	select CPU_AMD_MODEL_10XXX
 	select PCI_IO_CFG_EXT
-	select CAR_FAM10
 
 config CPU_SOCKET_TYPE
 	hex
Index: svn/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- svn.orig/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ svn/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -111,7 +111,6 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_CAR_FAM10
 uses CONFIG_AMD_UCODE_PATCH_FILE
 
 ###
Index: svn/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
===================================================================
--- svn.orig/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
+++ svn/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
@@ -49,7 +49,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -87,7 +87,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
Index: svn/src/mainboard/supermicro/h8dmr_fam10/Options.lb
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr_fam10/Options.lb
+++ svn/src/mainboard/supermicro/h8dmr_fam10/Options.lb
@@ -114,7 +114,6 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_CAR_FAM10
 uses CONFIG_AMD_UCODE_PATCH_FILE
 
 ###
Index: svn/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
+++ svn/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
@@ -49,7 +49,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10
+		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -88,7 +88,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR_FAM10
+		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
Index: svn/src/mainboard/tyan/s2912_fam10/Options.lb
===================================================================
--- svn.orig/src/mainboard/tyan/s2912_fam10/Options.lb
+++ svn/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -114,7 +114,6 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_CAR_FAM10
 uses CONFIG_AMD_UCODE_PATCH_FILE
 
 ###
