<html><head><style type="text/css"><!-- DIV {margin:0px;} --></style></head><body><div style="font-family:"Times New Roman [monotype]", "new york", "times", serif;font-size:12pt"><DIV>Hi Myles,</DIV><DIV><BR></DIV><DIV>Thank you for hint. I found this place too. Apparently it is not correct for vx800 platform.<BR></DIV><DIV>I tried to modify this output in src/boot/hardwaremain.c to have different POST code. And I still have the same sequence "00"->''10"->"80" after complete rebuild of the image.</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">Ok. It looks that I need more understanding about what is the sequence of execution of coreboot.</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">Here is the quote from documentation/POSTCODES</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">----------------------------------------</DIV><DIV
style="font-family:times new roman, new york, times, serif;font-size:12pt">0x10 Entry into protected mode<BR>0x01 Entry into 'crt0.s' reset code jumps to here<BR>0x11 Start copying LinuxBIOS to RAM with decompression if compressed<BR>0x12 Copy/decompression finished jumping to RAM<BR>0x80 Entry into LinuxBIOS in RAM<BR>0x13 Entry into c_start<BR>0xfe Pre call to hardwaremain()<BR>0x39 Console is initialized<BR>0x40 Console boot message succeeded<BR>0x66 Devices have been enumerated<BR>0x88 Devices have been configured<BR>0x89 Devices have been enabled<BR>0xf8 Entry into elf boot<BR>0xf3 Jumping to payload<BR>----------------------------------------<BR></DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt"><BR></DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">From this quote I see that boot sequence for vx800 lacks decompression/copy stages and goes directly to entry in RAM. Supposedly
code 0x80 is outputted in function hardwaremain which called from c_start.S. But I see in sources that some motherboards/northbridges have their own version of hardwaremain function. vx800 has one too. But it is in examples and looks that it is not used.</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt"><BR></DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">So my question is:</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">What is the sequence of coreboot start-up for 32-bits x86 after entry32.inc (post code 0x10). What code is executed next before hardwaremain.</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt"><BR></DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">Thank you,</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt">Konstantin
Lazarev.</DIV><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt"><BR><DIV style="font-family:times new roman, new york, times, serif;font-size:12pt"><FONT size="2" face="Tahoma"><HR size="1"><B><SPAN style="font-weight: bold;">From:</SPAN></B> Myles Watson <mylesgw@gmail.com><BR><B><SPAN style="font-weight: bold;">To:</SPAN></B> Konstantin Lazarev <klazarev@sbcglobal.net><BR><B><SPAN style="font-weight: bold;">Cc:</SPAN></B> coreboot@coreboot.org<BR><B><SPAN style="font-weight: bold;">Sent:</SPAN></B> Thursday, October 22, 2009 8:04:49 PM<BR><B><SPAN style="font-weight: bold;">Subject:</SPAN></B> Re: [coreboot] Post code 0x80<BR></FONT><BR>
<BR><BR><DIV class="gmail_quote">On Thu, Oct 22, 2009 at 6:29 PM, Konstantin Lazarev <SPAN dir="ltr"><<A rel="nofollow" ymailto="mailto:klazarev@sbcglobal.net" target="_blank" href="mailto:klazarev@sbcglobal.net">klazarev@sbcglobal.net</A>></SPAN> wrote:<BR><BLOCKQUOTE class="gmail_quote" style="border-left:1px solid rgb(204, 204, 204);margin:0pt 0pt 0pt 0.8ex;padding-left:1ex;">
<DIV><DIV style=""><DIV>Hello,<BR></DIV><DIV><BR></DIV><DIV>I am working on booting up VIA VX800 board with coreboot.</DIV><DIV>I have coreboot (r4824) stuck on POST code 0x80 (sequence was "00" -> "10" -> "80") with this board.</DIV>
<DIV>Could somebody please let me know where (in which source file in coreboot) this code is outputted in port 0x80?</DIV></DIV></DIV></BLOCKQUOTE><DIV>src/boot/hardwaremain.c, right before console_init.<BR><BR>Hopefully you'll quickly get to the point where you can use serial output, it's much more informative.<BR>
<BR>Thanks,<BR>Myles <BR></DIV></DIV><BR>
</DIV></DIV></div></body></html>