Index: src/southbridge/nvidia/ck804/Kconfig
===================================================================
--- src/southbridge/nvidia/ck804/Kconfig	(revision 4958)
+++ src/southbridge/nvidia/ck804/Kconfig	(working copy)
@@ -3,3 +3,7 @@
 	select HAVE_HARD_RESET
 	select IOAPIC
 
+config ID_SECTION_OFFSET
+	hex
+	default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
+
Index: src/southbridge/nvidia/ck804/id.inc
===================================================================
--- src/southbridge/nvidia/ck804/id.inc	(revision 4958)
+++ src/southbridge/nvidia/ck804/id.inc	(working copy)
@@ -1,15 +0,0 @@
-	.section ".id", "a", @progbits
-
-	.globl __id_start
-__id_start:
-vendor:
-	.asciz CONFIG_MAINBOARD_VENDOR
-part:
-	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x80 - vendor       /* Reverse offset to the vendor ID */
-.long __id_end + 0x80 - part         /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE                /* Size of this ROM image */
-	.globl __id_end
-
-__id_end:
-.previous
Index: src/southbridge/nvidia/ck804/id.lds
===================================================================
--- src/southbridge/nvidia/ck804/id.lds	(revision 4958)
+++ src/southbridge/nvidia/ck804/id.lds	(working copy)
@@ -1,6 +0,0 @@
-SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
-	.id (.): {
-		*(.id)
-	}
-}
Index: src/southbridge/nvidia/mcp55/Kconfig
===================================================================
--- src/southbridge/nvidia/mcp55/Kconfig	(revision 4958)
+++ src/southbridge/nvidia/mcp55/Kconfig	(working copy)
@@ -1,2 +1,6 @@
 config SOUTHBRIDGE_NVIDIA_MCP55
 	bool
+
+config ID_SECTION_OFFSET
+	hex
+	default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
Index: src/southbridge/nvidia/mcp55/id.inc
===================================================================
--- src/southbridge/nvidia/mcp55/id.inc	(revision 4958)
+++ src/southbridge/nvidia/mcp55/id.inc	(working copy)
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	.section ".id", "a", @progbits
-
-	.globl __id_start
-__id_start:
-vendor:
-	.asciz CONFIG_MAINBOARD_VENDOR
-part:
-	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
-.long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE           /* Size of this romimage */
-	.globl __id_end
-
-__id_end:
-.previous
Index: src/southbridge/nvidia/mcp55/id.lds
===================================================================
--- src/southbridge/nvidia/mcp55/id.lds	(revision 4958)
+++ src/southbridge/nvidia/mcp55/id.lds	(working copy)
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
-	.id (.): {
-		*(.id)
-	}
-}
Index: src/southbridge/sis/sis966/Kconfig
===================================================================
--- src/southbridge/sis/sis966/Kconfig	(revision 4958)
+++ src/southbridge/sis/sis966/Kconfig	(working copy)
@@ -1,2 +1,6 @@
 config SOUTHBRIDGE_SIS_SIS966
 	bool
+
+config ID_SECTION_OFFSET
+	hex
+	default 0x80 if SOUTHBRIDGE_SIS_SIS966
Index: src/southbridge/sis/sis966/id.inc
===================================================================
--- src/southbridge/sis/sis966/id.inc	(revision 4958)
+++ src/southbridge/sis/sis966/id.inc	(working copy)
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	.section ".id", "a", @progbits
-
-	.globl __id_start
-__id_start:
-vendor:
-	.asciz CONFIG_MAINBOARD_VENDOR
-part:
-	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
-.long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE           /* Size of this romimage */
-	.globl __id_end
-
-__id_end:
-.previous
Index: src/southbridge/sis/sis966/id.lds
===================================================================
--- src/southbridge/sis/sis966/id.lds	(revision 4958)
+++ src/southbridge/sis/sis966/id.lds	(working copy)
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
-	.id (.): {
-		*(.id)
-	}
-}
Index: src/Kconfig
===================================================================
--- src/Kconfig	(revision 4958)
+++ src/Kconfig	(working copy)
@@ -467,3 +467,7 @@
 config WARNINGS_ARE_ERRORS
 	bool
 	default n
+
+config ID_SECTION_OFFSET
+	hex
+	default 0x10
Index: src/mainboard/Makefile.k8_ck804.inc
===================================================================
--- src/mainboard/Makefile.k8_ck804.inc	(revision 4958)
+++ src/mainboard/Makefile.k8_ck804.inc	(working copy)
@@ -39,7 +39,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/ck804/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/ck804/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -47,7 +47,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/ck804/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/ck804/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
Index: src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- src/mainboard/supermicro/h8dmr/Config.lb	(revision 4958)
+++ src/mainboard/supermicro/h8dmr/Config.lb	(working copy)
@@ -110,8 +110,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/supermicro/h8dmr/Makefile.inc
===================================================================
--- src/mainboard/supermicro/h8dmr/Makefile.inc	(revision 4958)
+++ src/mainboard/supermicro/h8dmr/Makefile.inc	(working copy)
@@ -33,7 +33,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
Index: src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- src/mainboard/supermicro/h8dmr/Options.lb	(revision 4958)
+++ src/mainboard/supermicro/h8dmr/Options.lb	(working copy)
@@ -112,6 +112,8 @@
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -345,5 +347,7 @@
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/supermicro/h8dme/Config.lb
===================================================================
--- src/mainboard/supermicro/h8dme/Config.lb	(revision 4958)
+++ src/mainboard/supermicro/h8dme/Config.lb	(working copy)
@@ -108,8 +108,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/supermicro/h8dme/Makefile.inc
===================================================================
--- src/mainboard/supermicro/h8dme/Makefile.inc	(revision 4958)
+++ src/mainboard/supermicro/h8dme/Makefile.inc	(working copy)
@@ -34,7 +34,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -42,7 +42,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
Index: src/mainboard/supermicro/h8dme/Options.lb
===================================================================
--- src/mainboard/supermicro/h8dme/Options.lb	(revision 4958)
+++ src/mainboard/supermicro/h8dme/Options.lb	(working copy)
@@ -114,6 +114,8 @@
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/Makefile.inc	(revision 4958)
+++ src/mainboard/supermicro/h8dmr_fam10/Makefile.inc	(working copy)
@@ -33,7 +33,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
Index: src/mainboard/supermicro/h8dmr_fam10/Options.lb
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/Options.lb	(revision 4958)
+++ src/mainboard/supermicro/h8dmr_fam10/Options.lb	(working copy)
@@ -115,6 +115,7 @@
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
+uses CONFIG_ID_SECTION_OFFSET
 
 ###
 ### Build options
@@ -356,5 +357,7 @@
 default CONFIG_USE_FAILOVER_IMAGE=0
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
+
+default CONFIG_ID_SECTION_OFFSET=0x80
 ### End Options.lb
 end
Index: src/mainboard/supermicro/h8dmr_fam10/Config.lb
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/Config.lb	(revision 4958)
+++ src/mainboard/supermicro/h8dmr_fam10/Config.lb	(working copy)
@@ -112,8 +112,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/gigabyte/m57sli/Makefile.inc
===================================================================
--- src/mainboard/gigabyte/m57sli/Makefile.inc	(revision 4958)
+++ src/mainboard/gigabyte/m57sli/Makefile.inc	(working copy)
@@ -36,7 +36,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -44,7 +44,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
Index: src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- src/mainboard/gigabyte/m57sli/Options.lb	(revision 4958)
+++ src/mainboard/gigabyte/m57sli/Options.lb	(working copy)
@@ -116,6 +116,8 @@
 uses CONFIG_USE_PRINTK_IN_CAR
 
 uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
+
+uses CONFIG_ID_SECTION_OFFSET
 ###
 ### Build options
 ###
@@ -356,5 +358,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- src/mainboard/gigabyte/m57sli/Config.lb	(revision 4958)
+++ src/mainboard/gigabyte/m57sli/Config.lb	(working copy)
@@ -111,8 +111,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/Config.lb	(revision 4958)
+++ src/mainboard/gigabyte/ga_2761gxdk/Config.lb	(working copy)
@@ -113,8 +113,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/sis/sis966/id.inc
-ldscript /southbridge/sis/sis966/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc	(revision 4958)
+++ src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc	(working copy)
@@ -33,14 +33,14 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/sis/sis966/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/sis/sis966/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
Index: src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/Options.lb	(revision 4958)
+++ src/mainboard/gigabyte/ga_2761gxdk/Options.lb	(working copy)
@@ -115,6 +115,8 @@
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,6 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
 ### End Options.lb
 end
Index: src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	(revision 4958)
+++ src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	(working copy)
@@ -113,6 +113,8 @@
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -357,5 +359,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/tyan/s2912/Makefile.inc
===================================================================
--- src/mainboard/tyan/s2912/Makefile.inc	(revision 4958)
+++ src/mainboard/tyan/s2912/Makefile.inc	(working copy)
@@ -33,7 +33,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
Index: src/mainboard/tyan/s2912/Options.lb
===================================================================
--- src/mainboard/tyan/s2912/Options.lb	(revision 4958)
+++ src/mainboard/tyan/s2912/Options.lb	(working copy)
@@ -113,6 +113,8 @@
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/tyan/s2912/Config.lb
===================================================================
--- src/mainboard/tyan/s2912/Config.lb	(revision 4958)
+++ src/mainboard/tyan/s2912/Config.lb	(working copy)
@@ -111,8 +111,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/tyan/s2891/Options.lb
===================================================================
--- src/mainboard/tyan/s2891/Options.lb	(revision 4958)
+++ src/mainboard/tyan/s2891/Options.lb	(working copy)
@@ -77,6 +77,8 @@
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=512*1024
 
@@ -294,5 +296,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/tyan/s2891/Config.lb
===================================================================
--- src/mainboard/tyan/s2891/Config.lb	(revision 4958)
+++ src/mainboard/tyan/s2891/Config.lb	(working copy)
@@ -77,8 +77,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
Index: src/mainboard/tyan/s2892/Options.lb
===================================================================
--- src/mainboard/tyan/s2892/Options.lb	(revision 4958)
+++ src/mainboard/tyan/s2892/Options.lb	(working copy)
@@ -71,6 +71,8 @@
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 
@@ -282,5 +284,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/tyan/s2892/Config.lb
===================================================================
--- src/mainboard/tyan/s2892/Config.lb	(revision 4958)
+++ src/mainboard/tyan/s2892/Config.lb	(working copy)
@@ -78,8 +78,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
Index: src/mainboard/tyan/s2895/Options.lb
===================================================================
--- src/mainboard/tyan/s2895/Options.lb	(revision 4958)
+++ src/mainboard/tyan/s2895/Options.lb	(working copy)
@@ -82,6 +82,8 @@
 
 uses CONFIG_RAMTOP
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 
@@ -303,5 +305,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/tyan/s2895/Config.lb
===================================================================
--- src/mainboard/tyan/s2895/Config.lb	(revision 4958)
+++ src/mainboard/tyan/s2895/Config.lb	(working copy)
@@ -90,8 +90,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
Index: src/mainboard/tyan/s2912_fam10/Makefile.inc
===================================================================
--- src/mainboard/tyan/s2912_fam10/Makefile.inc	(revision 4958)
+++ src/mainboard/tyan/s2912_fam10/Makefile.inc	(working copy)
@@ -33,7 +33,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
Index: src/mainboard/tyan/s2912_fam10/Options.lb
===================================================================
--- src/mainboard/tyan/s2912_fam10/Options.lb	(revision 4958)
+++ src/mainboard/tyan/s2912_fam10/Options.lb	(working copy)
@@ -115,6 +115,7 @@
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
+uses CONFIG_ID_SECTION_OFFSET
 
 ###
 ### Build options
@@ -355,5 +356,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/tyan/s2912_fam10/Config.lb
===================================================================
--- src/mainboard/tyan/s2912_fam10/Config.lb	(revision 4958)
+++ src/mainboard/tyan/s2912_fam10/Config.lb	(working copy)
@@ -111,8 +111,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/msi/ms7135/Config.lb
===================================================================
--- src/mainboard/msi/ms7135/Config.lb	(revision 4958)
+++ src/mainboard/msi/ms7135/Config.lb	(working copy)
@@ -107,8 +107,8 @@
 ##
 ## Include an ID string (for safe flashing).
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
Index: src/mainboard/msi/ms7135/Options.lb
===================================================================
--- src/mainboard/msi/ms7135/Options.lb	(revision 4958)
+++ src/mainboard/msi/ms7135/Options.lb	(working copy)
@@ -99,6 +99,8 @@
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ## ---> 512 Kbytes 
 default CONFIG_ROM_SIZE=(512*1024)
@@ -313,5 +315,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/msi/ms9282/Config.lb
===================================================================
--- src/mainboard/msi/ms9282/Config.lb	(revision 4958)
+++ src/mainboard/msi/ms9282/Config.lb	(working copy)
@@ -94,8 +94,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/msi/ms9282/Makefile.inc
===================================================================
--- src/mainboard/msi/ms9282/Makefile.inc	(revision 4958)
+++ src/mainboard/msi/ms9282/Makefile.inc	(working copy)
@@ -35,14 +35,14 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
Index: src/mainboard/msi/ms9282/Options.lb
===================================================================
--- src/mainboard/msi/ms9282/Options.lb	(revision 4958)
+++ src/mainboard/msi/ms9282/Options.lb	(working copy)
@@ -99,6 +99,8 @@
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes
 default CONFIG_ROM_SIZE=524288
@@ -303,5 +305,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/msi/ms7260/Config.lb
===================================================================
--- src/mainboard/msi/ms7260/Config.lb	(revision 4958)
+++ src/mainboard/msi/ms7260/Config.lb	(working copy)
@@ -93,8 +93,8 @@
   end
 end
 
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 # ROMSTRAP table for MCP55.
 if CONFIG_HAVE_FAILOVER_BOOT
Index: src/mainboard/msi/ms7260/Makefile.inc
===================================================================
--- src/mainboard/msi/ms7260/Makefile.inc	(revision 4958)
+++ src/mainboard/msi/ms7260/Makefile.inc	(working copy)
@@ -33,14 +33,14 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
Index: src/mainboard/msi/ms7260/Options.lb
===================================================================
--- src/mainboard/msi/ms7260/Options.lb	(revision 4958)
+++ src/mainboard/msi/ms7260/Options.lb	(working copy)
@@ -96,6 +96,7 @@
 uses CONFIG_MEM_TRAIN_SEQ
 uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_ID_SECTION_OFFSET
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
@@ -182,5 +183,6 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_ID_SECTION_OFFSET=0x80
 
 end
Index: src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- src/mainboard/sunw/ultra40/Config.lb	(revision 4958)
+++ src/mainboard/sunw/ultra40/Config.lb	(working copy)
@@ -62,8 +62,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
Index: src/mainboard/sunw/ultra40/Options.lb
===================================================================
--- src/mainboard/sunw/ultra40/Options.lb	(revision 4958)
+++ src/mainboard/sunw/ultra40/Options.lb	(working copy)
@@ -69,6 +69,8 @@
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
 #default CONFIG_ROM_SIZE=524288
@@ -272,5 +274,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/nvidia/l1_2pvv/Makefile.inc
===================================================================
--- src/mainboard/nvidia/l1_2pvv/Makefile.inc	(revision 4958)
+++ src/mainboard/nvidia/l1_2pvv/Makefile.inc	(working copy)
@@ -33,7 +33,7 @@
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
Index: src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- src/mainboard/nvidia/l1_2pvv/Options.lb	(revision 4958)
+++ src/mainboard/nvidia/l1_2pvv/Options.lb	(working copy)
@@ -113,6 +113,8 @@
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -345,5 +347,7 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
Index: src/mainboard/nvidia/l1_2pvv/Config.lb
===================================================================
--- src/mainboard/nvidia/l1_2pvv/Config.lb	(revision 4958)
+++ src/mainboard/nvidia/l1_2pvv/Config.lb	(working copy)
@@ -141,8 +141,8 @@
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
Index: src/mainboard/asus/a8n_e/Config.lb
===================================================================
--- src/mainboard/asus/a8n_e/Config.lb	(revision 4958)
+++ src/mainboard/asus/a8n_e/Config.lb	(working copy)
@@ -78,8 +78,8 @@
 	end
 end
 # Include an ID string (for safe flashing).
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 # ROMSTRAP table for CK804.
 if CONFIG_HAVE_FAILOVER_BOOT
 	if CONFIG_USE_FAILOVER_IMAGE
Index: src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- src/mainboard/asus/a8n_e/Options.lb	(revision 4958)
+++ src/mainboard/asus/a8n_e/Options.lb	(working copy)
@@ -94,6 +94,7 @@
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_ID_SECTION_OFFSET
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
@@ -162,5 +163,6 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_ID_SECTION_OFFSET = 0x80
 
 end
Index: src/config/Options.lb
===================================================================
--- src/config/Options.lb	(revision 4958)
+++ src/config/Options.lb	(working copy)
@@ -1132,3 +1132,8 @@
 	comment "Leave a hole for PCIe config space in the device allocator"
 end
 
+define CONFIG_ID_SECTION_OFFSET
+	default 0x10
+	export always
+	comment "Offset of the .id section. Only needs to change if something like a romstrap is in the way"
+end
Index: src/arch/i386/lib/id.inc
===================================================================
--- src/arch/i386/lib/id.inc	(revision 4958)
+++ src/arch/i386/lib/id.inc	(working copy)
@@ -6,9 +6,9 @@
 	.asciz CONFIG_MAINBOARD_VENDOR
 part:		
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + 0x10 - vendor  /* Reverse offset to the vendor id */
-.long __id_end + 0x10 - part    /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE           /* Size of this romimage */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor  /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part    /* Reverse offset to the part number */
+.long CONFIG_ROM_SIZE                               /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
Index: src/arch/i386/lib/id.lds
===================================================================
--- src/arch/i386/lib/id.lds	(revision 4958)
+++ src/arch/i386/lib/id.lds	(working copy)
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
