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<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>I found a dram
compatibility issue of coreboot.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>My platform setup
is Atom+945GSE+ICH7M+IT8718.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>I have two
SO-DIMMs. First one is PC2-5300, 512MB, and made by Apacer. Second one
is the PC2-4200, 512MB, and made by Nanya .</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>My coreboot with the
first SO-DIMM can boot until the payload stage. System will received a software
reset and reset itself repeat again.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>My coreboot with the
second slow SO-DIMM can boot and load my payload
successfully.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>So I think it
is a compatibility issue.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>Is there anyone can
explain the issue in case same infinite reset loop happen
again.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009>Thanks.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>Here are the partial
log:</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>First
SO-DIMM:</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009>======================================</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>coreboot-2.0.0-r Thu
Dec 3 18:06:23 CST 2009 starting...</SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>Mobile Intel(R)
82945GMS/GU Express Chipset<BR>(G)MCH capable of up to FSB 667 MHz<BR>(G)MCH
capable of up to DDR2-533<BR>Setting up static southbridge registers... GPIOS...
done.<BR>Disabling Watchdog reboot... done.<BR>Setting up static northbridge
registers... done.<BR>Waiting for MCHBAR to come up...ok<BR>PM1_CNT:
00001c00<BR>SMBus controller enabled.</SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>dimm 50<BR>00: 80 08
08 0e 0a 60 40 00 05 30 45 00 82 08 00 00 <BR>10: 0c 04 38 01 04 00 03 3d 50 50
60 3c 1e 3c 2d 80 <BR>20: 20 27 10 17 3c 1e 1e 00 00 3c 69 80 18 22 00 53
<BR>30: 78 4a 39 26 26 2b 1b 4a 20 22 00 00 00 00 12 df <BR>40: 7f 7a 00 00 00
00 00 00 00 37 38 2e 39 32 47 36 <BR>50: 33 2e 41 46 32 ff ff ff ff ff ff 00 00
08 49 02 <BR>60: 30 84 95 00 00 00 00 00 00 00 00 00 00 00 00 00 <BR>70: 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 <BR>80: ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff <BR>90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
<BR>a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff <BR>b0: ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff <BR>c0: ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff <BR>d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff <BR>e0: ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff <BR>f0: ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff </SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>dimm 51<BR>00: bad
device: 01</SPAN></FONT></DIV>
<DIV> </DIV><SPAN class=984273006-14122009>
<DIV><BR><FONT size=2 face=新細明體>dimm 52<BR>00: bad device: 01</FONT></DIV>
<DIV><FONT size=2 face=新細明體></FONT> </DIV>
<DIV><BR><FONT size=2 face=新細明體>dimm 53<BR>00: bad device: 01</FONT></DIV>
<DIV><FONT size=2 face=新細明體></FONT> </DIV>
<DIV><FONT size=2 face=新細明體>SLP S4# Assertion Width Violation.<BR>Setting up RAM
controller.<BR>This mainboard supports Dual Channel Operation.<BR>DDR II Channel
0 Socket 0: x8DS<BR>DDR II Channel 1 Socket 0: N/A<BR>lowest common cas =
3<BR>Probing Speed 1<BR> DIMM: 0<BR> Current CAS mask:
0038; idx=2, tCLK=50, tAC=60: Not fast
enough!<BR> Current CAS mask: 0030; idx=1, tCLK=3d,
tAC=50: OK<BR> DIMM: 1<BR> DIMM: 2<BR> DIMM:
3<BR> freq_cas_mask for speed 1: 0030<BR>Memory will be driven at 533MHz
with CAS=4 clocks<BR>tRAS = 12 cycles<BR>tRP = 4 cycles<BR>tRCD = 4
cycles<BR>Refresh: 7.8us<BR>tWR = 4 cycles<BR>DIMM 0 side 0 = 512
MB</FONT></DIV>
<DIV><FONT size=2 face=新細明體></FONT> </DIV>
<DIV><FONT size=2 face=新細明體>tRFC = 28 cycles<BR>Setting Graphics Frequency...
<BR>FSB: 533 MHz Voltage: 1.05V Render: 166Mhz Display: 200MHz<BR>Setting Memory
Frequency... CLKCFG=0x00010021, CLKCFG=0x00010031, ok<BR>Setting mode of
operation for memory channels...Single Channel 0
only.<BR>DCC=0x00000400<BR>Programming Clock Crossing...MEM=533 FSB=533...
ok<BR>Setting RAM size... <BR>C0DRB = 0x10101010<BR>C1DRB = 0x00000000<BR>TOLUD
= 0x0020<BR>Setting row attributes... <BR>C0DRA = 0x0003<BR>C1DRA =
0x0000<BR>one dimm per channel config.. <BR>Initializing System Memory IO...
<BR>Programming Dual Channel RCOMP<BR>Table Index: 9<BR>Programming DLL
Timings... <BR>Enabling System Memory IO... <BR>jedec enable sequence: bank
0<BR>Apply NOP<BR> Sending RAM command
0x00010400...done<BR> ram read: 00000000<BR>All Banks
Precharge<BR> Sending RAM command 0x00020400...done<BR>
ram read: 00000000<BR>Extended Mode Register Set(2)<BR> Sending RAM
command 0x00240400...done<BR> ram read: 00000000<BR>Extended Mode
Register Set(3)<BR> Sending RAM command
0x00440400...done<BR> ram read: 00000000<BR>Extended Mode Register
Set<BR> Sending RAM command 0x00040400...done<BR> ram
read: 00000200<BR>MRS: Reset DLLs<BR> Sending RAM command
0x00030400...done<BR> ram read: 00003a58<BR>All Banks
Precharge<BR> Sending RAM command 0x00020400...done<BR>
ram read: 00000000<BR>CAS before RAS<BR> Sending RAM command
0x00060400...done<BR> ram read: 00000000<BR> ram read:
00000000<BR>MRS: Enable DLLs<BR> Sending RAM command
0x00030400...done<BR> ram read: 00003258<BR>Extended Mode Register
Set: ODT/OCD<BR> Sending RAM command
0x00040400...done<BR> ram read: 00001e00<BR>Extended Mode Register
Set: OCD Exit<BR> Sending RAM command
0x00040400...done<BR> ram read: 00000200<BR>Normal
Operation<BR> Sending RAM command
0x000f0400...done<BR>receive_enable_autoconfig() for channel 0<BR>
find_strobes_low()<BR> set_receive_enable() medium=0x3,
coarse=0x4<BR> set_receive_enable() medium=0x1,
coarse=0x4<BR> set_receive_enable() medium=0x1,
coarse=0x4<BR> find_strobes_edge()<BR>
set_receive_enable() medium=0x1, coarse=0x4<BR> add_quarter_clock()
mediumcoarse=11 fine=80<BR> set_receive_enable() medium=0x3,
coarse=0x4<BR> find_preamble()<BR> set_receive_enable()
medium=0x3, coarse=0x3<BR> set_receive_enable() medium=0x3,
coarse=0x2<BR> add_quarter_clock() mediumcoarse=0b fine=00<BR>
normalize()<BR> set_receive_enable() medium=0x0,
coarse=0x3<BR>Weird. No C0WL0REOST</FONT></DIV>
<DIV><FONT size=2>RAM initialization finished.</FONT></DIV>
<DIV><SPAN class=984273006-14122009><FONT size=2
face=新細明體>....</FONT></SPAN></DIV>
<DIV><SPAN class=984273006-14122009><FONT size=2 face=新細明體>Jumping to boot code
at 100080<BR>entry = 0x00100080<BR>lb_start =
0x00100000<BR>lb_size = 0x00042000<BR>adjust =
0x1f5be000<BR>buffer = 0x1f558090<BR>
elf_boot_notes = 0x0012fa48<BR>adjusted_boot_notes =
0x1f6eda48<BR>F</FONT></SPAN></DIV>
<DIV><FONT size=2 face=新細明體></FONT> </DIV>
<DIV><SPAN class=984273006-14122009><FONT size=2 face=新細明體>coreboot-2.0.0-r Thu
Dec 3 18:06:23 CST 2009 starting...<BR>soft reset
detected.</FONT></SPAN></DIV>
<DIV><SPAN class=984273006-14122009><FONT size=2
face=新細明體>======================================</FONT></SPAN></DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009>Second SO-DIMM:</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009></SPAN></FONT> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009><SPAN
class=984273006-14122009><FONT size=2
face=新細明體>======================================</FONT></SPAN></SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>coreboot-2.0.0-r Thu
Dec 3 18:06:23 CST 2009 starting...</SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>Mobile Intel(R)
82945GMS/GU Express Chipset<BR>(G)MCH capable of up to FSB 667 MHz<BR>(G)MCH
capable of up to DDR2-533<BR>Setting up static southbridge registers... GPIOS...
done.<BR>Disabling Watchdog reboot... done.<BR>Setting up static northbridge
registers... done.<BR>Waiting for MCHBAR to come up...ok<BR>PM1_CNT:
00001c00<BR>SMBus controller enabled.</SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>dimm 50<BR>00: 80 08
08 0d 0a 61 40 00 05 3d 50 00 82 10 00 00 <BR>10: 0c 04 38 01 04 00 01 3d 50 50
60 3c 28 3c 2d 40 <BR>20: 25 37 10 22 3c 1e 1e 00 00 3c 69 80 1e 28 00 50
<BR>30: 76 7b 2d 25 1f 24 16 4a 22 31 00 00 00 00 12 10 <BR>40: 7f 7f 7f 0b 00
00 00 00 0d 4e 54 35 31 32 54 36 <BR>50: 34 55 48 38 41 31 46 4e 2d 33 37 42 00
05 39 d2 <BR>60: 6e 2f 24 88 00 00 00 00 00 00 00 00 00 00 00 00 <BR>70: 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 <BR>80: 00 00 00 00 00 00 00 4d 4d 30
35 39 32 30 30 42 <BR>90: 43 00 00 00 00 00 00 44 4e 54 35 33 39 32 31 30
<BR>a0: 34 00 00 00 00 00 00 39 4e 54 44 32 00 32 2d 31 <BR>b0: 32 00 00 00 00
00 00 00 00 00 00 00 00 00 80 00 <BR>c0: 00 00 00 00 00 00 00 00 00 00 00 80 00
00 00 00 <BR>d0: 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 <BR>e0: 00 00
00 00 00 80 00 00 00 01 00 00 00 00 00 00 <BR>f0: 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 88 </SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>dimm 51<BR>00: bad
device: 01</SPAN></FONT></DIV>
<DIV> </DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>
<DIV><BR>dimm 52<BR>00: bad device: 01</DIV>
<DIV> </DIV>
<DIV><BR>dimm 53<BR>00: bad device: 01</DIV>
<DIV> </DIV>
<DIV>SLP S4# Assertion Width Violation.<BR>Setting up RAM controller.<BR>This
mainboard supports Dual Channel Operation.<BR>DDR II Channel 0 Socket 0:
x16DS<BR>DDR II Channel 1 Socket 0: N/A<BR>lowest common cas = 3<BR>Probing
Speed 1<BR> DIMM: 0<BR> Current CAS mask: 0038; idx=2,
tCLK=50, tAC=60: Not fast enough!<BR>
Current CAS mask: 0030; idx=1, tCLK=3d, tAC=50: OK<BR>
DIMM: 1<BR> DIMM: 2<BR> DIMM: 3<BR> freq_cas_mask for speed 1:
0030<BR>Memory will be driven at 533MHz with CAS=4 clocks<BR>tRAS = 12
cycles<BR>tRP = 4 cycles<BR>tRCD = 4 cycles<BR>Refresh: 7.8us<BR>tWR = 4
cycles<BR>DIMM 0 side 0 = 256 MB<BR>DIMM 0 side 1 = 256 MB<BR>tRFC = 28
cycles<BR>Setting Graphics Frequency... <BR>FSB: 533 MHz Voltage: 1.05V Render:
166Mhz Display: 200MHz<BR>Setting Memory Frequency... CLKCFG=0x00010021,
CLKCFG=0x00010031, ok<BR>Setting mode of operation for memory channels...Single
Channel 0 only.<BR>DCC=0x00000400<BR>Programming Clock Crossing...MEM=533
FSB=533... ok<BR>Setting RAM size... <BR>C0DRB = 0x10101008<BR>C1DRB =
0x00000000<BR>TOLUD = 0x0020<BR>Setting row attributes... <BR>C0DRA =
0x0033<BR>C1DRA = 0x0000<BR>one dimm per channel config.. <BR>Initializing
System Memory IO... <BR>Programming Dual Channel RCOMP<BR>Table Index:
4<BR>Programming DLL Timings... <BR>Enabling System Memory IO... <BR>jedec
enable sequence: bank 0<BR>Apply NOP<BR> Sending RAM command
0x00010400...done<BR> ram read: 00000000<BR>All Banks
Precharge<BR> Sending RAM command 0x00020400...done<BR>
ram read: 00000000<BR>Extended Mode Register Set(2)<BR> Sending RAM
command 0x00240400...done<BR> ram read: 00000000<BR>Extended Mode
Register Set(3)<BR> Sending RAM command
0x00440400...done<BR> ram read: 00000000<BR>Extended Mode Register
Set<BR> Sending RAM command 0x00040400...done<BR> ram
read: 00000200<BR>MRS: Reset DLLs<BR> Sending RAM command
0x00030400...done<BR> ram read: 00003a58<BR>All Banks
Precharge<BR> Sending RAM command 0x00020400...done<BR>
ram read: 00000000<BR>CAS before RAS<BR> Sending RAM command
0x00060400...done<BR> ram read: 00000000<BR> ram read:
00000000<BR>MRS: Enable DLLs<BR> Sending RAM command
0x00030400...done<BR> ram read: 00003258<BR>Extended Mode Register
Set: ODT/OCD<BR> Sending RAM command
0x00040400...done<BR> ram read: 00001e00<BR>Extended Mode Register
Set: OCD Exit<BR> Sending RAM command
0x00040400...done<BR> ram read: 00000200<BR>jedec enable sequence:
bank 1<BR>bankaddr from bank size of rank 0<BR>Apply NOP<BR> Sending
RAM command 0x00010400...done<BR> ram read: 10000000<BR>All Banks
Precharge<BR> Sending RAM command 0x00020400...done<BR>
ram read: 10000000<BR>Extended Mode Register Set(2)<BR> Sending RAM
command 0x00240400...done<BR> ram read: 10000000<BR>Extended Mode
Register Set(3)<BR> Sending RAM command
0x00440400...done<BR> ram read: 10000000<BR>Extended Mode Register
Set<BR> Sending RAM command 0x00040400...done<BR> ram
read: 10000200<BR>MRS: Reset DLLs<BR> Sending RAM command
0x00030400...done<BR> ram read: 10003a58<BR>All Banks
Precharge<BR> Sending RAM command 0x00020400...done<BR>
ram read: 10000000<BR>CAS before RAS<BR> Sending RAM command
0x00060400...done<BR> ram read: 10000000<BR> ram read:
10000000<BR>MRS: Enable DLLs<BR> Sending RAM command
0x00030400...done<BR> ram read: 10003258<BR>Extended Mode Register
Set: ODT/OCD<BR> Sending RAM command
0x00040400...done<BR> ram read: 10001e00<BR>Extended Mode Register
Set: OCD Exit<BR> Sending RAM command
0x00040400...done<BR> ram read: 10000200<BR>Normal
Operation<BR> Sending RAM command
0x000f0400...done<BR>receive_enable_autoconfig() for channel 0<BR>
find_strobes_low()<BR> set_receive_enable() medium=0x3,
coarse=0x4<BR> set_receive_enable() medium=0x1,
coarse=0x4<BR> find_strobes_edge()<BR>
set_receive_enable() medium=0x1, coarse=0x4<BR> add_quarter_clock()
mediumcoarse=11 fine=b1<BR> set_receive_enable() medium=0x3,
coarse=0x4<BR> find_preamble()<BR> set_receive_enable()
medium=0x3, coarse=0x3<BR> set_receive_enable() medium=0x3,
coarse=0x2<BR> add_quarter_clock() mediumcoarse=0b fine=31<BR>
normalize()<BR> set_receive_enable() medium=0x0,
coarse=0x3<BR>RAM initialization finished.</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN
class=984273006-14122009>....</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009>Jumping to boot code
at 100080<BR>entry = 0x00100080<BR>lb_start =
0x00100000<BR>lb_size = 0x00042000<BR>adjust =
0x1f5be000<BR>buffer = 0x1f558090<BR>
elf_boot_notes = 0x0012fa48<BR>adjusted_boot_notes = 0x1f6eda48<BR>FILO version
0.6.0 (<A href="mailto:scott@scott-laptop">scott@scott-laptop</A>) Wed Oct 28
21:33:51 CST 2009<BR>No USB stack in libpayload.<BR>menu:
hda3:/boot/filo/menu.lst</SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體><SPAN class=984273006-14122009><SPAN
class=984273006-14122009><FONT size=2
face=新細明體>======================================</FONT></SPAN></SPAN></FONT></DIV>
<DIV><FONT size=2 face=新細明體></FONT> </DIV>
<DIV><FONT size=2 face=新細明體></FONT> </DIV>
<DIV><FONT size=2 face=新細明體></FONT> </DIV>
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