Index: src/cpu/intel/model_106cx/cache_as_ram.inc =================================================================== --- src/cpu/intel/model_106cx/cache_as_ram.inc (revision 4995) +++ src/cpu/intel/model_106cx/cache_as_ram.inc (working copy) @@ -114,7 +114,13 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#undef CONFIG_XIP_ROM_BASE + movl $CONFIG_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax +#else movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax +#endif wrmsr movl $MTRRphysMask_MSR(1), %ecx Index: src/cpu/intel/model_106cx/cache_as_ram_disable.c =================================================================== --- src/cpu/intel/model_106cx/cache_as_ram_disable.c (revision 4995) +++ src/cpu/intel/model_106cx/cache_as_ram_disable.c (working copy) @@ -25,6 +25,7 @@ { unsigned int cpu_reset = 0; +#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK #if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { @@ -46,6 +47,7 @@ ); fallback_image: #endif +#endif real_main(bist); Index: src/cpu/intel/model_6ex/cache_as_ram.inc =================================================================== --- src/cpu/intel/model_6ex/cache_as_ram.inc (revision 4995) +++ src/cpu/intel/model_6ex/cache_as_ram.inc (working copy) @@ -104,7 +104,13 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#undef CONFIG_XIP_ROM_BASE + movl $CONFIG_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax +#else movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax +#endif wrmsr movl $MTRRphysMask_MSR(1), %ecx Index: src/cpu/intel/model_6ex/cache_as_ram_disable.c =================================================================== --- src/cpu/intel/model_6ex/cache_as_ram_disable.c (revision 4995) +++ src/cpu/intel/model_6ex/cache_as_ram_disable.c (working copy) @@ -27,6 +27,7 @@ { unsigned int cpu_reset = 0; +#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK #if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { @@ -48,6 +49,7 @@ ); fallback_image: #endif +#endif real_main(bist); Index: src/cpu/intel/model_6fx/cache_as_ram.inc =================================================================== --- src/cpu/intel/model_6fx/cache_as_ram.inc (revision 4995) +++ src/cpu/intel/model_6fx/cache_as_ram.inc (working copy) @@ -111,7 +111,13 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#undef CONFIG_XIP_ROM_BASE + movl $CONFIG_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax +#else movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax +#endif wrmsr movl $MTRRphysMask_MSR(1), %ecx Index: src/cpu/intel/model_6fx/cache_as_ram_disable.c =================================================================== --- src/cpu/intel/model_6fx/cache_as_ram_disable.c (revision 4995) +++ src/cpu/intel/model_6fx/cache_as_ram_disable.c (working copy) @@ -27,6 +27,7 @@ { unsigned int cpu_reset = 0; +#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK #if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { @@ -48,6 +49,7 @@ ); fallback_image: #endif +#endif real_main(bist);