Index: src/cpu/intel/model_106cx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram_disable.c	(revision 4995)
+++ src/cpu/intel/model_106cx/cache_as_ram_disable.c	(working copy)
@@ -25,6 +25,7 @@
 {
 	unsigned int cpu_reset = 0;
 
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -46,6 +47,7 @@
                 );
  fallback_image:
 #endif
+#endif
 
 	real_main(bist);
 
Index: src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram.inc	(revision 4995)
+++ src/cpu/intel/model_106cx/cache_as_ram.inc	(working copy)
@@ -114,7 +114,13 @@
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
Index: src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram_disable.c	(revision 4995)
+++ src/cpu/intel/model_6ex/cache_as_ram_disable.c	(working copy)
@@ -27,6 +27,7 @@
 {
 	unsigned int cpu_reset = 0;
 
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
                 );
  fallback_image:
 #endif
+#endif
 
 	real_main(bist);
 
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram.inc	(revision 4995)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc	(working copy)
@@ -104,7 +104,13 @@
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
Index: src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram_disable.c	(revision 4995)
+++ src/cpu/intel/model_6fx/cache_as_ram_disable.c	(working copy)
@@ -27,6 +27,7 @@
 {
 	unsigned int cpu_reset = 0;
 
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
 #if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
                 );
  fallback_image:
 #endif
+#endif
 
 	real_main(bist);
 
Index: src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram.inc	(revision 4995)
+++ src/cpu/intel/model_6fx/cache_as_ram.inc	(working copy)
@@ -111,7 +111,13 @@
 	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
-        movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
Index: src/arch/i386/Makefile.tinybootblock.inc
===================================================================
--- src/arch/i386/Makefile.tinybootblock.inc	(revision 4995)
+++ src/arch/i386/Makefile.tinybootblock.inc	(working copy)
@@ -67,13 +67,13 @@
 # Build the romstage
 $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $(initobjs) $(obj)/romstage/ldscript.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
+	printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld
 	$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
 	$(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
 	printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
 	$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
 	cat $(obj)/location.txt >> $(obj)/location.ld
-	printf ";\n" >> $(obj)/location.ld
+	printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld
 	$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
 	$(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
 	$(OBJCOPY) -O binary $(obj)/romstage.elf $@
