added w83627hf_set_16_bit_addr_qual() to w83627_early_serial.c
   Reason: Enabled by default on PL-6064 with stock BIOS
   	   not sure if this needs to be in early_serial
	   or early_init
added w83627hf_set_clksel_48() to w83627_early_serial.c
   Reason: The Win Ent platforms are using the 83627HG part, this 
           part does not appear to enable 48MHz clock by default 
	   as claimed in the datasheet.
Added support for Win Enterprises PL-6064/64 platforms

Signed-off-by: Anish K Patel <anishp@win-ent.com>

Index: src/superio/winbond/w83627hf/w83627hf_early_serial.c
===================================================================
--- src/superio/winbond/w83627hf/w83627hf_early_serial.c	(revision 5117)
+++ src/superio/winbond/w83627hf/w83627hf_early_serial.c	(working copy)
@@ -4,6 +4,7 @@
  * Copyright (C) 2000 AG Electronics Ltd.
  * Copyright (C) 2003-2004 Linux Networx
  * Copyright (C) 2004 Tyan By LYH change from PC87360
+ * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -36,6 +37,26 @@
 	outb(0xaa, port);
 }
 
+static void w83627hf_set_clksel_48(device_t dev)
+{
+      unsigned port = dev >> 8;
+      pnp_enter_ext_func_mode(dev);
+      outb(0x24, port);
+      /* set clk input to 48MHz */
+      outb(inb(port + 1) | 0x40, port + 1);
+      pnp_exit_ext_func_mode(dev);
+}
+
+static void w83627hf_16_bit_addr_qual(device_t dev)
+{
+      unsigned port = dev >> 8;
+      pnp_enter_ext_func_mode(dev);
+      outb(0x24, port);
+      /* enable 16 bit address qualification */
+      outb(inb(port + 1) | 0x80, port + 1);
+      pnp_exit_ext_func_mode(dev);
+}
+
 static void w83627hf_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_ext_func_mode(dev);
Index: src/mainboard/Kconfig
===================================================================
--- src/mainboard/Kconfig	(revision 5117)
+++ src/mainboard/Kconfig	(working copy)
@@ -94,6 +94,8 @@
 	bool "Tyan"
 config VENDOR_VIA
 	bool "VIA"
+config VENDOR_WINENT
+	bool "Win Enterprises"
 
 endchoice
 
@@ -352,6 +354,11 @@
 	default 0x1019
 	depends on VENDOR_VIA
 
+config MAINBOARD_VENDOR
+	string
+	default "Win Enterprise"
+	depends on VENDOR_WINENT
+
 source "src/mainboard/a-trend/Kconfig"
 source "src/mainboard/abit/Kconfig"
 source "src/mainboard/advantech/Kconfig"
@@ -397,6 +404,7 @@
 source "src/mainboard/thomson/Kconfig"
 source "src/mainboard/tyan/Kconfig"
 source "src/mainboard/via/Kconfig"
+source "src/mainboard/winent/Kconfig"
 
 config BOARD_ROMSIZE_KB_128
 	bool
Index: src/mainboard/winent/Kconfig
===================================================================
--- src/mainboard/winent/Kconfig	(revision 0)
+++ src/mainboard/winent/Kconfig	(revision 0)
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_WINENT
+
+source "src/mainboard/winent/pl6064/Kconfig"
+
+endchoice
+
Index: src/mainboard/winent/pl6064/Kconfig
===================================================================
--- src/mainboard/winent/pl6064/Kconfig	(revision 0)
+++ src/mainboard/winent/pl6064/Kconfig	(revision 0)
@@ -0,0 +1,38 @@
+config BOARD_WINENT_PL6064
+	bool "PL6064"
+	select ARCH_X86
+	select CPU_AMD_LX
+	select NORTHBRIDGE_AMD_LX
+	select SOUTHBRIDGE_AMD_CS5536
+	select SUPERIO_WINBOND_W83627HF
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select USE_DCACHE_RAM
+	select USE_PRINTK_IN_CAR
+	select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+	string
+	default winent/pl6064
+	depends on BOARD_WINENT_PL6064
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "PL6064"
+	depends on BOARD_WINENT_PL6064
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_WINENT_PL6064
+
+config IRQ_SLOT_COUNT
+	int
+	default 7
+	depends on BOARD_WINENT_PL6064
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_WINENT_PL6064
Index: src/mainboard/winent/pl6064/devicetree.cb
===================================================================
--- src/mainboard/winent/pl6064/devicetree.cb	(revision 0)
+++ src/mainboard/winent/pl6064/devicetree.cb	(revision 0)
@@ -0,0 +1,77 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end				# Northbridge
+		device pci 1.1 on end				# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+			register "lpc_serirq_enable" = "0x0000105a"
+			register "lpc_serirq_polarity" = "0x0000EFA5"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "1"	# 0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			
+			device pci d.0 on end			# Ethernet
+			device pci a.0 on end			# Ethernet
+			device pci b.0 on end			# Ethernet
+			device pci c.0 on end			# Ethernet
+			device pci e.0 on end			# Slot1
+			device pci f.0 on			# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 off	# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on	# Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+
+					device pnp 2e.3 on	# Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end	# CIR
+					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
+					device pnp 2e.8 off end	# GPIO2
+					device pnp 2e.9 off end	# GPIO3
+					device pnp 2e.a off end	# ACPI
+					device pnp 2e.b off end	# HW Monitor
+				end
+			end
+			device pci f.2 on end			# IDE Controller
+			device pci f.3 off end			# Audio
+			device pci f.4 on end			# OHCI
+			device pci f.5 on end			# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+end
+
Index: src/mainboard/winent/pl6064/romstage.c
===================================================================
--- src/mainboard/winent/pl6064/romstage.c	(revision 0)
+++ src/mainboard/winent/pl6064/romstage.c	(revision 0)
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Win Enterprises, Inc (anishp@win-ent.com)
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __PRE_RAM__
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "lib/ramtest.c"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/geode_post_code.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+#define POST_CODE(x) outb(x, 0x80)
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
+#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#define ManualConf 0		/* Do automatic strapped PLL config */
+#define PLLMSRhi 0x00001490	/* Manual settings for the PLL */
+#define PLLMSRlo 0x02000030
+#define DIMM0 0xA0
+#define DIMM1 0xA2
+
+#include "northbridge/amd/lx/raminit.h"
+#include "northbridge/amd/lx/pll_reset.c"
+#include "northbridge/amd/lx/raminit.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/model_lx/cpureginit.c"
+#include "cpu/amd/model_lx/syspreinit.c"
+
+struct msrinit {
+            u32 msrnum;
+            msr_t msr;
+      };
+
+static const struct msrinit msr_table[] = 
+{
+       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
+                                                                  * Rom Properties: Write Serialize, WriteProtect.
+                                                                  * RomBase: 0xFFFC0
+                                                                  * SysTop to RomBase Properties: Write Serialize, Cache Disable.
+                                                                  * SysTop: 0x000A0 
+                                                                  * System Memory Properties:  (Write Back) */
+       {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
+       {CPU_RCONF_C0_DF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
+       {CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
+       
+       /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
+       {MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
+       {MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
+       {MSR_GLIU0_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
+       {MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
+       {MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
+       {MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
+};
+
+
+static void msr_init(void)
+{
+  int i;
+       for (i = 0; i < ARRAY_SIZE(msr_table); i++)
+                           wrmsr(msr_table[i].msrnum, msr_table[i].msr);
+}
+
+static void mb_gpio_init(void)
+{
+	/* Early mainboard specific GPIO setup. */
+}
+
+void cache_as_ram_main(void)
+{
+	POST_CODE(0x01);
+
+	static const struct mem_controller memctrl[] = {
+		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+	};
+
+	SystemPreInit();
+	msr_init();
+
+	cs5536_early_setup();
+
+	/* Note: must do this AFTER the early_setup! It is counting on some
+	 * early MSR setup for CS5536.
+	 */
+	w83627hf_16_bit_addr_qual(SERIAL_DEV);
+	w83627hf_set_clksel_48(SERIAL_DEV);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	mb_gpio_init();
+	uart_init();
+	console_init();
+
+	pll_reset(ManualConf);
+
+	cpuRegInit();
+
+	sdram_initialize(1, memctrl);
+
+	/* Check memory. */
+	/* ram_check(0x00000000, 640 * 1024); */
+
+	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+	return;
+}
Index: src/mainboard/winent/pl6064/Makefile.inc
===================================================================
--- src/mainboard/winent/pl6064/Makefile.inc	(revision 0)
+++ src/mainboard/winent/pl6064/Makefile.inc	(revision 0)
@@ -0,0 +1,21 @@
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+crt0s := $(src)/cpu/x86/16bit/entry16.inc
+crt0s += $(src)/cpu/x86/32bit/entry32.inc
+crt0s += $(src)/cpu/x86/16bit/reset16.inc
+crt0s += $(src)/arch/i386/lib/id.inc
+crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+
+ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscripts += $(src)/cpu/x86/16bit/entry16.lds
+ldscripts += $(src)/cpu/x86/16bit/reset16.lds
+ldscripts += $(src)/arch/i386/lib/id.lds
+ldscripts += $(src)/arch/i386/lib/failover.lds
+
Index: src/mainboard/winent/pl6064/irq_tables.c
===================================================================
--- src/mainboard/winent/pl6064/irq_tables.c	(revision 0)
+++ src/mainboard/winent/pl6064/irq_tables.c	(revision 0)
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Win Enterprises, Inc (anishp@win-ent.com)
+ 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 10
+#define PIRQB 11
+#define PIRQC 10
+#define PIRQD 11
+
+/* Map */
+#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA	 1		/* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB	 2		/* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC	 3		/* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD	 4		/* Means Slot INTx# Connects To Chipset INTD# */
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version   */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+	0x00,			/* Where the interrupt router lies (bus) */
+	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
+	0x00,			/* IRQs devoted exclusively to PCI usage */
+	0x100B,			/* Vendor */
+	0x002B,			/* Device */
+	0,			/* Crap (miniport) */
+	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
+	0x00,			/*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
+	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
+	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
+	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0},	/* slot1 */
+	 }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
Index: src/mainboard/winent/pl6064/chip.h
===================================================================
--- src/mainboard/winent/pl6064/chip.h	(revision 0)
+++ src/mainboard/winent/pl6064/chip.h	(revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+	int nothing;
+};
Index: src/mainboard/winent/pl6064/cmos.layout
===================================================================
--- src/mainboard/winent/pl6064/cmos.layout	(revision 0)
+++ src/mainboard/winent/pl6064/cmos.layout	(revision 0)
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
Index: src/mainboard/winent/pl6064/mainboard.c
===================================================================
--- src/mainboard/winent/pl6064/mainboard.c	(revision 0)
+++ src/mainboard/winent/pl6064/mainboard.c	(revision 0)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Win Enterprises, Inc. (anishp@win-ent.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include "chip.h"
+
+static void init(struct device *dev)
+{
+	printk_debug("Win Enterprises PL-6064/65 ENTER %s\n", __func__);
+	printk_debug("Win Enterprises PL-6064/65 EXIT%s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+	dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Win Enterprises PL-6064/65 Mainboard")
+	.enable_dev = enable_dev,
+};
