Index: src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- src/cpu/x86/lapic/lapic_cpu_init.c	(revision 5180)
+++ src/cpu/x86/lapic/lapic_cpu_init.c	(working copy)
@@ -246,26 +246,8 @@
 	index = ++last_cpu_index;
 
 	/* Find end of the new processors stack */
-#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
-	if(index<1) { // only keep bsp on low
-		stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
-	} else {
-		// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
-		stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
-#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP)
-		#warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
-#endif
-		if(stack_end > (CONFIG_RAMTOP)) {
-			printk_debug("start_cpu: Please increase the CONFIG_RAMTOP more than %luK\n", stack_end);
-			die("Can not go on\n");
-		}
-		stack_end -= sizeof(struct cpu_info);
-	}
-#else
 	stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
-#endif
 
-
 	/* Record the index and which cpu structure we are using */
 	info = (struct cpu_info *)stack_end;
 	info->index = index;
Index: src/mainboard/technexion/tim5690/Kconfig
===================================================================
--- src/mainboard/technexion/tim5690/Kconfig	(revision 5180)
+++ src/mainboard/technexion/tim5690/Kconfig	(working copy)
@@ -127,5 +127,5 @@
 
 config RAMBASE
 	hex
-	default 0x4000
+	default 0x100000
 	depends on BOARD_TECHNEXION_TIM5690
Index: src/arch/i386/coreboot_ram.ld
===================================================================
--- src/arch/i386/coreboot_ram.ld	(revision 5180)
+++ src/arch/i386/coreboot_ram.ld	(working copy)
@@ -100,11 +100,11 @@
 	_ebss = .;
 	_end = .;
 	. = ALIGN(CONFIG_STACK_SIZE);
+
 	_stack = .;
 	.stack . : {
 		/* Reserve a stack for each possible cpu */
-		/* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/
-		. += ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
+		. += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE;
 	}
 	_estack = .;
         _heap = .;
@@ -114,6 +114,10 @@
                 . = ALIGN(4);
         }
         _eheap = .;
+
+	/* Avoid running into 0xa0000-0xfffff */
+	_bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB");
+
 	/* The ram segment
  	 * This is all address of the memory resident copy of coreboot.
 	 */
