Index: src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
===================================================================
--- src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c	(revision 5256)
+++ src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c	(working copy)
@@ -3,8 +3,6 @@
  *  by yinghai.lu@amd.com
  */
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
 static void bcm5785_enable_rom(void)
 {
         unsigned char byte;
@@ -42,9 +40,7 @@
         byte |=(1<<1)|(1<<0);
         pci_write_config8(dev, 0x48, byte);
 }
-#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
 
-
 static void bcm5785_enable_wdt_port_cf9(void)
 {
         device_t dev;
Index: src/Kconfig
===================================================================
--- src/Kconfig	(revision 5256)
+++ src/Kconfig	(working copy)
@@ -272,22 +272,6 @@
 	int
 	default 0
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default y
-
-config USE_FALLBACK_IMAGE
-	bool
-	default y
-
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-
 config HAVE_HARD_RESET
 	bool
 	default y if BOARD_HAS_HARD_RESET
Index: src/include/fallback.h
===================================================================
--- src/include/fallback.h	(revision 5256)
+++ src/include/fallback.h	(working copy)
@@ -3,12 +3,7 @@
 
 #ifndef ASSEMBLY
 
-#if CONFIG_HAVE_FALLBACK_BOOT == 1
 void set_boot_successful(void);
-#else
-#define set_boot_successful()
-#endif
-
 void boot_successful(void);
 
 #endif /* ASSEMBLY */
Index: src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- src/cpu/amd/car/cache_as_ram.inc	(revision 5256)
+++ src/cpu/amd/car/cache_as_ram.inc	(working copy)
@@ -71,9 +71,6 @@
 	cvtsi2sd %eax, %xmm2
 	cvtsd2si %xmm3, %ebx
 
-	/* hope we can skip the double set for normal part */
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 	/* check if cpu_init_detected */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
@@ -248,16 +245,7 @@
 	xorl	%edx, %edx
 	movl	$(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
 	wrmsr
-#endif /*  CONFIG_USE_FAILOVER_IMAGE == 1*/
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
-	/* disable cache */
-	movl	%cr0, %eax
-	orl	$(0x1 << 30), %eax
-	movl	%eax, %cr0
-
-#endif
-
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* enable write base caching so we can do execute in place
 	 * on the flash rom.
@@ -283,7 +271,6 @@
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 	/* Set the default memory type and enable fixed and variable MTRRs */
 	movl	$MTRRdefType_MSR, %ecx
 	xorl	%edx, %edx
@@ -296,7 +283,6 @@
 	rdmsr
 	orl	$(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
 	wrmsr
-#endif
 
 	movb	$0xA1, %al
 	outb	%al, $0x80
@@ -318,7 +304,6 @@
 	movb	$0xA2, %al
 	outb	%al, $0x80
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 	/* Read the range with lodsl*/
 	cld
 	movl	$CacheBase, %esi
@@ -331,8 +316,6 @@
 	xorl	%eax, %eax
 	rep	stosl
 
-#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
-
 	/* set up the stack pointer */
 	movl	$(CacheBase + CacheSize - GlobalVarSize), %eax
 	movl	%eax, %esp
Index: src/cpu/x86/car/cache_as_ram.inc
===================================================================
--- src/cpu/x86/car/cache_as_ram.inc	(revision 5256)
+++ src/cpu/x86/car/cache_as_ram.inc	(working copy)
@@ -36,9 +36,6 @@
 	movl	%eax, %ebp
 
 CacheAsRam:
-	/* hope we can skip the double set for normal part */
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
 	// Check whether the processor has HT capability
 	movl	$01, %eax
 	cpuid
@@ -191,14 +188,6 @@
 	simplemask CacheSize, 0
 	wrmsr
 
-#else
-	/* disable cache */
-	movl	%cr0, %eax
-	orl	$(0x1 << 30), %eax
-	movl	%eax, %cr0
-
-#endif /*  CONFIG_USE_FALLBACK_IMAGE == 1*/
-
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
@@ -225,8 +214,6 @@
 	andl	$0x9fffffff, %eax
 	movl	%eax, %cr0
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
 	/* Read the range with lodsl*/
 	movl	$CacheBase, %esi
 	cld
@@ -283,9 +270,7 @@
 .xout1x:
 
 #endif
-#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
 
-
 	movl	$(CacheBase + CacheSize - 4), %eax
 	movl	%eax, %esp
 
@@ -319,7 +304,6 @@
 	.long	0x20C, 0x20D, 0x20E, 0x20F
 	.long	0x000 /* NULL, end of table */
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 	.align 0x1000
 	.code16
 .global LogicalAP_SIPI
@@ -349,5 +333,4 @@
 	hlt
 	jmp	Halt_LogicalAP
 	.code32
-#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
 .CacheAsRam_out:
Index: src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram.inc	(revision 5256)
+++ src/cpu/intel/model_106cx/cache_as_ram.inc	(working copy)
@@ -29,8 +29,6 @@
 	movl    %eax, %ebp
 
 cache_as_ram:
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
 	post_code(0x20)
 
 	/* Send INIT IPI to all excluding ourself */
@@ -134,7 +132,6 @@
         movl	%cr0, %eax
 	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
 	movl	%eax, %cr0
-#endif
 
 	/* Set up stack pointer */
 #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram.inc	(revision 5256)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc	(working copy)
@@ -29,8 +29,6 @@
 	movl    %eax, %ebp
 
 cache_as_ram:
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
 	post_code(0x20)
 
 	/* Send INIT IPI to all excluding ourself */
@@ -123,7 +121,6 @@
         movl	%cr0, %eax
 	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
 	movl	%eax, %cr0
-#endif
 
 	/* Set up stack pointer */
 #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
Index: src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram.inc	(revision 5256)
+++ src/cpu/intel/model_6fx/cache_as_ram.inc	(working copy)
@@ -29,8 +29,6 @@
 	movl    %eax, %ebp
 
 cache_as_ram:
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
 	post_code(0x20)
 
 	/* Send INIT IPI to all excluding ourself */
@@ -130,7 +128,6 @@
         movl	%cr0, %eax
 	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
 	movl	%eax, %cr0
-#endif
 
 	/* Set up stack pointer */
 #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
Index: src/mainboard/iwill/dk8_htx/romstage.c
===================================================================
--- src/mainboard/iwill/dk8_htx/romstage.c	(revision 5258)
+++ src/mainboard/iwill/dk8_htx/romstage.c	(working copy)
@@ -32,21 +32,17 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
 
 
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -128,13 +124,10 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -260,4 +253,3 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif
Index: src/mainboard/iwill/dk8s2/romstage.c
===================================================================
--- src/mainboard/iwill/dk8s2/romstage.c	(revision 5258)
+++ src/mainboard/iwill/dk8s2/romstage.c	(working copy)
@@ -32,21 +32,17 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
 
 
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -128,13 +124,10 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -260,4 +253,3 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif
Index: src/mainboard/iwill/dk8x/romstage.c
===================================================================
--- src/mainboard/iwill/dk8x/romstage.c	(revision 5258)
+++ src/mainboard/iwill/dk8x/romstage.c	(working copy)
@@ -32,21 +32,16 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
 
-
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -128,13 +123,10 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -260,4 +252,3 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif
Index: src/mainboard/supermicro/h8dmr/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/romstage.c	(revision 5258)
+++ src/mainboard/supermicro/h8dmr/romstage.c	(working copy)
@@ -55,7 +55,6 @@
 // for enable the FAN
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -67,15 +66,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -137,8 +132,6 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -167,8 +160,6 @@
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
@@ -291,5 +282,3 @@
 
 }
 
-
-#endif
Index: src/mainboard/supermicro/h8dme/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/romstage.c	(revision 5258)
+++ src/mainboard/supermicro/h8dme/romstage.c	(working copy)
@@ -52,7 +52,6 @@
 // for enable the FAN
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -64,15 +63,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -191,8 +186,6 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -225,8 +218,6 @@
 #define RC0 (2<<8)
 #define RC1 (1<<8)
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
@@ -371,4 +362,3 @@
 
 }
 
-#endif
Index: src/mainboard/supermicro/h8dmr_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c	(revision 5258)
+++ src/mainboard/supermicro/h8dmr_fam10/romstage.c	(working copy)
@@ -54,7 +54,6 @@
 	outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -65,15 +64,11 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -133,8 +128,6 @@
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -163,7 +156,6 @@
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -317,5 +309,3 @@
 
 }
 
-
-#endif
Index: src/mainboard/supermicro/h8qme_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/romstage.c	(revision 5258)
+++ src/mainboard/supermicro/h8qme_fam10/romstage.c	(working copy)
@@ -54,7 +54,6 @@
 	outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -65,15 +64,11 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -136,8 +131,6 @@
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -166,7 +159,6 @@
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -360,5 +352,3 @@
 
 }
 
-
-#endif
Index: src/mainboard/kontron/986lcd-m/romstage.c
===================================================================
--- src/mainboard/kontron/986lcd-m/romstage.c	(revision 5256)
+++ src/mainboard/kontron/986lcd-m/romstage.c	(working copy)
@@ -352,9 +352,7 @@
 	RCBA32(0x2034) = reg32;
 }
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
 
 #include <cbmem.h>
 
Index: src/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- src/mainboard/gigabyte/m57sli/Kconfig	(revision 5256)
+++ src/mainboard/gigabyte/m57sli/Kconfig	(working copy)
@@ -78,16 +78,6 @@
         default n
 	depends on BOARD_GIGABYTE_M57SLI
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default n
-	depends on BOARD_GIGABYTE_M57SLI
-
-config USE_FALLBACK_IMAGE
-	bool
-	default n
-	depends on BOARD_GIGABYTE_M57SLI
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
Index: src/mainboard/gigabyte/m57sli/romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/romstage.c	(revision 5258)
+++ src/mainboard/gigabyte/m57sli/romstage.c	(working copy)
@@ -54,7 +54,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -148,8 +143,6 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -175,8 +168,6 @@
 }
 
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
@@ -316,5 +307,3 @@
 
 }
 
-
-#endif
Index: src/mainboard/gigabyte/ga_2761gxdk/Kconfig
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/Kconfig	(revision 5256)
+++ src/mainboard/gigabyte/ga_2761gxdk/Kconfig	(working copy)
@@ -75,16 +75,6 @@
         default n
 	depends on BOARD_GIGABYTE_GA_2761GXDK
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default n
-	depends on BOARD_GIGABYTE_GA_2761GXDK
-
-config USE_FALLBACK_IMAGE
-	bool
-	default n
-	depends on BOARD_GIGABYTE_GA_2761GXDK
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
Index: src/mainboard/gigabyte/ga_2761gxdk/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(revision 5258)
+++ src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(working copy)
@@ -56,7 +56,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -73,15 +72,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -150,8 +145,6 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 
@@ -175,8 +168,6 @@
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
@@ -303,5 +294,3 @@
 
 }
 
-
-#endif
Index: src/mainboard/amd/serengeti_cheetah/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/romstage.c	(revision 5258)
+++ src/mainboard/amd/serengeti_cheetah/romstage.c	(working copy)
@@ -43,21 +43,18 @@
 #endif
 }
 #endif
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
 
 
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -152,13 +149,10 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -336,4 +330,3 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif
Index: src/mainboard/amd/mahogany_fam10/romstage.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/romstage.c	(revision 5258)
+++ src/mainboard/amd/mahogany_fam10/romstage.c	(working copy)
@@ -58,14 +58,12 @@
 	outb(value, 0x80);
 }
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
 #include "arch/i386/lib/console.c"
 #include "pc80/serial.c"
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -80,8 +78,6 @@
 #include "cpu/x86/bist.h"
 
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
@@ -128,13 +124,10 @@
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
 
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 
-#if (CONFIG_USE_FAILOVER_IMAGE==0)
 //#include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -306,5 +299,3 @@
 	post_code(0x43);	// Should never see this post code.
 }
 
-
-#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */
Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(revision 5258)
+++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(working copy)
@@ -58,7 +58,6 @@
 	outb(value, 0x80);
 }
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
 #include "arch/i386/lib/console.c"
 #include "pc80/serial.c"
 #include "lib/ramtest.c"
@@ -66,7 +65,6 @@
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -80,8 +78,6 @@
 #include "cpu/x86/bist.h"
 
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-
 #include "northbridge/amd/amdfam10/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -141,13 +137,10 @@
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
 
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-#if (CONFIG_USE_FAILOVER_IMAGE==0)
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -316,5 +309,3 @@
 
 }
 
-
-#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */
Index: src/mainboard/hp/dl145_g3/romstage.c
===================================================================
--- src/mainboard/hp/dl145_g3/romstage.c	(revision 5258)
+++ src/mainboard/hp/dl145_g3/romstage.c	(working copy)
@@ -61,7 +61,6 @@
 #include "pc80/mc146818rtc_early.c"
 
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -73,8 +72,6 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
@@ -83,8 +80,6 @@
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -153,8 +148,6 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 #if 0
@@ -195,8 +188,6 @@
 }
 #endif
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -312,4 +303,3 @@
 
 }
 
-#endif
Index: src/mainboard/tyan/s2912/Kconfig
===================================================================
--- src/mainboard/tyan/s2912/Kconfig	(revision 5256)
+++ src/mainboard/tyan/s2912/Kconfig	(working copy)
@@ -76,16 +76,6 @@
         default n
 	depends on BOARD_TYAN_S2912
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2912
-
-config USE_FALLBACK_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2912
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
Index: src/mainboard/tyan/s2912/romstage.c
===================================================================
--- src/mainboard/tyan/s2912/romstage.c	(revision 5258)
+++ src/mainboard/tyan/s2912/romstage.c	(working copy)
@@ -54,7 +54,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -146,8 +141,6 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -174,8 +167,6 @@
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
@@ -299,5 +290,3 @@
 
 }
 
-
-#endif
Index: src/mainboard/tyan/s2895/romstage.c
===================================================================
--- src/mainboard/tyan/s2895/romstage.c	(revision 5258)
+++ src/mainboard/tyan/s2895/romstage.c	(working copy)
@@ -19,7 +19,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -32,8 +31,6 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
@@ -42,8 +39,6 @@
 
 #define SUPERIO_GPIO_IO_BASE 0x400
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -114,8 +109,6 @@
 
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#endif
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -147,8 +140,6 @@
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
@@ -226,4 +217,3 @@
 
 	post_cache_as_ram();
 }
-#endif
Index: src/mainboard/tyan/s2912_fam10/Kconfig
===================================================================
--- src/mainboard/tyan/s2912_fam10/Kconfig	(revision 5256)
+++ src/mainboard/tyan/s2912_fam10/Kconfig	(working copy)
@@ -38,26 +38,6 @@
 	default 0x04000
 	depends on BOARD_TYAN_S2912_FAM10
 
-config USE_FALLBACK_IMAGE
-	bool
-	default y
-	depends on BOARD_TYAN_S2912_FAM10
-
-config HAVE_FALLBACK_BOOT
-	bool
-	default y
-	depends on BOARD_TYAN_S2912_FAM10
-
-config CONFIG_USE_FAILOVER_IMAGE
-	bool
-	default y
-	depends on BOARD_TYAN_S2912_FAM10
-
-config CONFIG_HAVE_FAILOVER_BOOT
-	bool
-	default y
-	depends on BOARD_TYAN_S2912_FAM10
-
 config APIC_ID_OFFSET
 	hex
 	default 0
@@ -98,16 +78,6 @@
 	default n
 	depends on BOARD_TYAN_S2912_FAM10
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2912_FAM10
-
-config USE_FALLBACK_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2912_FAM10
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
Index: src/mainboard/tyan/s2912_fam10/romstage.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/romstage.c	(revision 5258)
+++ src/mainboard/tyan/s2912_fam10/romstage.c	(working copy)
@@ -53,7 +53,6 @@
 	outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -68,15 +67,11 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -142,8 +137,6 @@
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -168,7 +161,6 @@
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -317,5 +309,3 @@
 	post_code(0x43);	// Should never see this post code.
 }
 
-
-#endif
Index: src/mainboard/roda/rk886ex/romstage.c
===================================================================
--- src/mainboard/roda/rk886ex/romstage.c	(revision 5256)
+++ src/mainboard/roda/rk886ex/romstage.c	(working copy)
@@ -259,9 +259,7 @@
 	RCBA32(0x2034) = reg32;
 }
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
 
 static void init_artec_dongle(void)
 {
Index: src/mainboard/msi/ms7135/romstage.c
===================================================================
--- src/mainboard/msi/ms7135/romstage.c	(revision 5258)
+++ src/mainboard/msi/ms7135/romstage.c	(working copy)
@@ -47,8 +47,6 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 /* Used by ck804_early_setup(). */
 #define CK804_NUM 1
 #define CK804_USE_NIC 1
@@ -98,8 +96,6 @@
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#endif	/* CONFIG_USE_FAILOVER_IMAGE */
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -121,7 +117,6 @@
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -204,4 +199,3 @@
 
 	post_cache_as_ram();
 }
-#endif /* CONFIG_USE_FAILOVER_IMAGE */
Index: src/mainboard/msi/ms9282/Kconfig
===================================================================
--- src/mainboard/msi/ms9282/Kconfig	(revision 5256)
+++ src/mainboard/msi/ms9282/Kconfig	(working copy)
@@ -70,16 +70,6 @@
         default n
 	depends on BOARD_MSI_MS9282
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default n
-	depends on BOARD_MSI_MS9282
-
-config USE_FALLBACK_IMAGE
-	bool
-	default n
-	depends on BOARD_MSI_MS9282
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
Index: src/mainboard/msi/ms9652_fam10/Kconfig
===================================================================
--- src/mainboard/msi/ms9652_fam10/Kconfig	(revision 5256)
+++ src/mainboard/msi/ms9652_fam10/Kconfig	(working copy)
@@ -42,26 +42,6 @@
 	default 0x1F
 	depends on BOARD_MSI_MS9652_FAM10
 
-config USE_FALLBACK_IMAGE
-	bool
-	default y
-	depends on BOARD_MSI_MS9652_FAM10
-
-config HAVE_FALLBACK_BOOT
-	bool
-	default y
-	depends on BOARD_MSI_MS9652_FAM10
-
-config CONFIG_USE_FAILOVER_IMAGE
-	bool
-	default y
-	depends on BOARD_MSI_MS9652_FAM10
-
-config CONFIG_HAVE_FAILOVER_BOOT
-	bool
-	default y
-	depends on BOARD_MSI_MS9652_FAM10
-
 config GENERATE_PIRQ_TABLE
 	bool
 	default y
Index: src/mainboard/msi/ms9652_fam10/romstage.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/romstage.c	(revision 5258)
+++ src/mainboard/msi/ms9652_fam10/romstage.c	(working copy)
@@ -54,7 +54,6 @@
 	outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
@@ -68,14 +67,10 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -143,8 +138,6 @@
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -163,7 +156,6 @@
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -323,5 +315,3 @@
 	post_code(0x43);	// Should never see this post code.
 }
 
-
-#endif
Index: src/mainboard/msi/ms7260/Kconfig
===================================================================
--- src/mainboard/msi/ms7260/Kconfig	(revision 5256)
+++ src/mainboard/msi/ms7260/Kconfig	(working copy)
@@ -76,16 +76,6 @@
         default n
 	depends on BOARD_MSI_MS7260
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default n
-	depends on BOARD_MSI_MS7260
-
-config USE_FALLBACK_IMAGE
-	bool
-	default n
-	depends on BOARD_MSI_MS7260
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
Index: src/mainboard/msi/ms7260/romstage.c
===================================================================
--- src/mainboard/msi/ms7260/romstage.c	(revision 5258)
+++ src/mainboard/msi/ms7260/romstage.c	(working copy)
@@ -58,8 +58,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -73,15 +71,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -129,8 +123,6 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -152,8 +144,6 @@
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -282,4 +272,3 @@
 	post_cache_as_ram();
 }
 
-#endif
Index: src/mainboard/nvidia/l1_2pvv/Kconfig
===================================================================
--- src/mainboard/nvidia/l1_2pvv/Kconfig	(revision 5256)
+++ src/mainboard/nvidia/l1_2pvv/Kconfig	(working copy)
@@ -76,16 +76,6 @@
         default n
 	depends on BOARD_NVIDIA_L1_2PVV
 
-config HAVE_FALLBACK_BOOT
-	bool
-	default n
-	depends on BOARD_NVIDIA_L1_2PVV
-
-config USE_FALLBACK_IMAGE
-	bool
-	default n
-	depends on BOARD_NVIDIA_L1_2PVV
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
Index: src/mainboard/nvidia/l1_2pvv/romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/romstage.c	(revision 5258)
+++ src/mainboard/nvidia/l1_2pvv/romstage.c	(working copy)
@@ -54,7 +54,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -148,8 +143,6 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -175,7 +168,6 @@
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
@@ -301,5 +293,3 @@
 
 }
 
-
-#endif
Index: src/mainboard/intel/d945gclf/romstage.c
===================================================================
--- src/mainboard/intel/d945gclf/romstage.c	(revision 5256)
+++ src/mainboard/intel/d945gclf/romstage.c	(working copy)
@@ -216,9 +216,7 @@
 	RCBA32(0x2034) = reg32;
 }
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
 
 #include <cbmem.h>
 
Index: src/mainboard/intel/eagleheights/romstage.c
===================================================================
--- src/mainboard/intel/eagleheights/romstage.c	(revision 5256)
+++ src/mainboard/intel/eagleheights/romstage.c	(working copy)
@@ -121,9 +121,7 @@
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i3100/cmos_failover.c"
-#endif
 
 void early_config(void) {
 	device_t dev;
Index: src/mainboard/asus/a8n_e/romstage.c
===================================================================
--- src/mainboard/asus/a8n_e/romstage.c	(revision 5258)
+++ src/mainboard/asus/a8n_e/romstage.c	(working copy)
@@ -47,8 +47,6 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 /* Used by ck894_early_setup(). */
 #define CK804_NUM 1
 
@@ -96,8 +94,6 @@
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#endif	/* CONFIG_USE_FAILOVER_IMAGE */
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -118,7 +114,6 @@
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -200,4 +195,3 @@
 
 	post_cache_as_ram();
 }
-#endif /* CONFIG_USE_FAILOVER_IMAGE */
Index: src/lib/fallback_boot.c
===================================================================
--- src/lib/fallback_boot.c	(revision 5256)
+++ src/lib/fallback_boot.c	(working copy)
@@ -5,7 +5,6 @@
 #include <arch/io.h>
 
 
-#if CONFIG_HAVE_FALLBACK_BOOT == 1
 void set_boot_successful(void)
 {
 	/* Remember I succesfully booted by setting
@@ -26,7 +25,6 @@
 		byte &= 0x0f;
 	outb(byte, RTC_PORT(1));
 }
-#endif
 
 void boot_successful(void)
 {
