<div>hi Rudolf,</div>
<div> Since <font color="#0066cc">mass-porting to AMD 780 series mainboards </font><font color="#000000">is taken included in GSoC 2010, the further work may be completed between this summer. </font></div>
<div><font color="#000000">I would like to take all of your consideration as Reference for my application.<br></font></div>
<p><font color="#000000">best wishes.</font></p>
<div><font color="#000000">Wang Qing Pei</font></div>
<div><br></div>
<div class="gmail_quote">On Sun, Mar 21, 2010 at 8:28 PM, Rudolf Marek <span dir="ltr"><<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>></span> wrote:<br>
<blockquote style="BORDER-LEFT: #ccc 1px solid; MARGIN: 0px 0px 0px 0.8ex; PADDING-LEFT: 1ex" class="gmail_quote">Hi all,<br><br>I went bit more through the code, looks overall very good! Thanks AMD!<br><br>Before we start the porting efforts here is the list of stuff needs to be done.<br>
<br>Is there anyone with spare time?<br><br>1) move fadt.c into sb700 directory<br><br>2) split ACPI dsl into smaller chunks, similar as we have for ICH7/945<br><br>3) Check why resourcemap.c is needed. The only change from default is change for<br>
maximum bus number settings which is set to 8. Not sure if we really need any<br>limit here?<br><br>4) some DSDT methods are doing checks for Linux and do something with AC97<br>codec, I think it does not work anyway because Linux tells it is Windows to ACPI<br>
:) Some DSDT values should be generated using ACPIgen namely HPET and something<br>else I forgot already. The ITE code should go to separate file, the _PTS method<br>is doing something to SMI, which we don't want because we dont have any SMI trap<br>
handler.<br><br>5) The GFX reset stuff<br><br>The Mahagony board has separate GFX reset GPIO because some PCIe 16x are shared<br>with displayport. I think this has to be checked for each board if such GPIO<br>reset is needed.<br>
<br>6) GPIO for IDE cable<br> This is also board dependent and must be find out.<br><br>7) PCIe lanes setup. The RS780 has very flexible setup for PCIe lanes, some for<br>them can be multiplexed for Display Port, some for HDMI etc... There is<br>
something written in the DS of RS780 but it is hard to understand that how it<br>suppose to work.<br><br>#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)<br>#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)<br>
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,<br># 1: the system allows a PCIE link to be established on<br>Dev2 or Dev3.<br>#Define gfx_dual_slot, 0: single slot, 1: dual slot<br>
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable<br>#Define gfx_tmds, 0: didn't support TMDS, 1: support<br>#Define gfx_compliance, 0: didn't support compliance, 1: support<br>#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long<br>
reconfiguration<br>#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not<br>supported), 6: x16<br><br>Each board can setup this differently, gpp_configuration = 0 means read it from<br>STRAP which is good because we dont have to set it up.<br>
<br><br>Is dual_slot - crossfire?<br><br>Does TMDS here means DVI/HDMI?<br><br>I try to get more ideas how this is supposed to work, maybe AMD folks can also<br>help ;)<br><br>Rudolf<br><font color="#888888"><br><br>-- <br>
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</font></blockquote></div><br><br clear="all"><br>-- <br>Wang Qing Pei <br><a href="mailto:MSN%3Awangqingpei@hotmail.com">MSN:wangqingpei@hotmail.com</a><br><a href="mailto:Gmail%3Awangqingpei@gmail.com">Gmail:wangqingpei@gmail.com</a><br>
Phone:86+13426369984<br>