use printk(BIOS_FOO, ...) instead of printk_foo(...) all over the tree...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Index: src/southbridge/via/vt8237r/vt8237r.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r.c	(revision 5263)
+++ src/southbridge/via/vt8237r/vt8237r.c	(working copy)
@@ -30,7 +30,7 @@
 
 void hard_reset(void)
 {
-	printk_err("NO HARD RESET ON VT8237R! FIX ME!\n");
+	printk(BIOS_ERR, "NO HARD RESET ON VT8237R! FIX ME!\n");
 }
 
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7
@@ -61,10 +61,10 @@
 	int i, j;
 
 	for (i = 0; i < 256; i += 16) {
-		printk_debug("%02x: ", i);
+		printk(BIOS_DEBUG, "%02x: ", i);
 		for (j = 0; j < 16; j++)
-			printk_debug("%02x ", pci_read_config8(dev, i + j));
-		printk_debug("\n");
+			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j));
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 
Index: src/southbridge/via/vt8237r/vt8237r_ide.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_ide.c	(revision 5263)
+++ src/southbridge/via/vt8237r/vt8237r_ide.c	(working copy)
@@ -40,15 +40,15 @@
 	device_t lpc_dev;
 	int i, j;
 
-	printk_info("%s IDE interface %s\n", "Primary",
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
 		    sb->ide0_enable ? "enabled" : "disabled");
-	printk_info("%s IDE interface %s\n", "Secondary",
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
 		    sb->ide1_enable ? "enabled" : "disabled");
 	enables = pci_read_config8(dev, IDE_CS) & ~0x3;
 	enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
 	pci_write_config8(dev, IDE_CS, enables);
 	enables = pci_read_config8(dev, IDE_CS);
-	printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
 
 	/* Enable only compatibility mode. */
 	enables = pci_read_config8(dev, 0x09);
@@ -59,7 +59,7 @@
 	enables &= ~0xc0;
 	pci_write_config8(dev, IDE_CONF_II, enables);
 	enables = pci_read_config8(dev, IDE_CONF_II);
-	printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
 
 	/* Enable prefetch buffers. */
 	enables = pci_read_config8(dev, IDE_CONF_I);
Index: src/southbridge/via/vt8237r/vt8237r_sata.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_sata.c	(revision 5263)
+++ src/southbridge/via/vt8237r/vt8237r_sata.c	(working copy)
@@ -28,7 +28,7 @@
 {
 	u8 reg;
 
-	printk_debug("Configuring VIA SATA controller\n");
+	printk(BIOS_DEBUG, "Configuring VIA SATA controller\n");
 
 	/* Class IDE Disk */
 	reg = pci_read_config8(dev, SATA_MISC_CTRL);
Index: src/southbridge/via/vt8237r/vt8237r_usb.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_usb.c	(revision 5263)
+++ src/southbridge/via/vt8237r/vt8237r_usb.c	(working copy)
@@ -34,16 +34,16 @@
 #if CONFIG_EPIA_VT8237R_INIT
 	u8 reg8;
 
-	printk_debug("Entering %s\n", __func__);
+	printk(BIOS_DEBUG, "Entering %s\n", __func__);
 
-	printk_spew("%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
+	printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
 
 	reg8 = pci_read_config8(dev, 0x04);
 
 	reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 	pci_write_config8(dev, 0x04, reg8);
 
-	printk_spew("%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8);
+	printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8);
 
 	/* Set Cache Line Size and Latency Timer */
 	pci_write_config8(dev, 0x0c, 0x08);
@@ -74,7 +74,7 @@
 	struct resource *res;
 	u8 function = (u8) dev->path.pci.devfn & 0x7;
 
-	printk_spew("VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]);
+	printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]);
 
 	/* Fix the I/O Resources of the USB1.1 Interfaces */
 	/* Auto PCI probe seems to size the resources     */
@@ -98,7 +98,7 @@
 #if CONFIG_EPIA_VT8237R_INIT
 	u8 reg8;
 
-	printk_debug("Entering %s\n", __func__);
+	printk(BIOS_DEBUG, "Entering %s\n", __func__);
 
 	/* Set memory Write and Invalidate */
 	reg8 = pci_read_config8(dev, 0x04);
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c	(revision 5263)
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	(working copy)
@@ -238,7 +238,7 @@
 	tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
-	printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
+	printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
 #endif
 	/* clear sleep */
 	tmp &= ~(7 << 10);
@@ -251,7 +251,7 @@
 	u8 enables, reg8;
 	
 #if CONFIG_EPIA_VT8237R_INIT
-	printk_spew("Entering vt8237r_init, for EPIA.\n");
+	printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
 	/*
 	 * TODO: Looks like stock BIOS can do this but causes a hang
 	 * Enable SATA LED, disable special CPU Frequency Change -
@@ -277,7 +277,7 @@
 	pci_write_config8(dev, 0x4E, enables);
 
 #else 
-	printk_spew("Entering vt8237r_init.\n");
+	printk(BIOS_SPEW, "Entering vt8237r_init.\n");
 	/*
 	 * Enable SATA LED, disable special CPU Frequency Change -
 	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
@@ -318,7 +318,7 @@
 	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
 #endif
 
-	printk_spew("Leaving %s.\n", __func__);
+	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
 static void vt8237s_init(struct device *dev)
Index: src/southbridge/via/k8t890/k8t890_pcie.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_pcie.c	(revision 5263)
+++ src/southbridge/via/k8t890/k8t890_pcie.c	(working copy)
@@ -28,7 +28,7 @@
 {
 	u8 reg;
 
-	printk_debug("Configuring PCIe PEG\n");
+	printk(BIOS_DEBUG, "Configuring PCIe PEG\n");
 	dump_south(dev);
 
 	/* Disable link. */
@@ -68,7 +68,7 @@
 {
 	u8 reg;
 
-	printk_debug("Configuring PCIe PEXs\n");
+	printk(BIOS_DEBUG, "Configuring PCIe PEXs\n");
 	dump_south(dev);
 
 	/* Disable link. */
Index: src/southbridge/via/k8t890/k8t890_dram.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_dram.c	(revision 5263)
+++ src/southbridge/via/k8t890/k8t890_dram.c	(working copy)
@@ -82,7 +82,7 @@
 	unsigned int *fbsize = (unsigned int *) gp;
 	uint64_t proposed_base = res->base + res->size - *fbsize;
 
-	printk_debug("get_memres: res->base=%llx res->size=%llx %d %d %d\n",
+	printk(BIOS_DEBUG, "get_memres: res->base=%llx res->size=%llx %d %d %d\n",
 			res->base, res->size, (res->size > *fbsize), 
 			(!(proposed_base & (*fbsize - 1))),
 			(proposed_base < ((uint64_t) 0xffffffff)));
@@ -99,7 +99,7 @@
 	if ((high_tables_base) && ((high_tables_base > proposed_base) &&
 			(high_tables_base < (res->base + res->size)))) {
 		high_tables_base = proposed_base - high_tables_size;
-		printk_debug("Moving the high_tables_base pointer to "
+		printk(BIOS_DEBUG, "Moving the high_tables_base pointer to "
 				"new base %llx\n", high_tables_base);
 	}
 #endif
@@ -140,12 +140,12 @@
 
 	ret = get_option(&fbbits, "videoram_size");
 	if (ret) {
-		printk_warning("Failed to get videoram size (error %d), using default.\n", ret);
+		printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret);
 		fbbits = 5;
  	}
 
 	if ((fbbits < 1) || (fbbits > 7)) {
-		printk_warning("Invalid videoram size (%d), using default.\n",
+		printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n",
 			       4 << fbbits);
 		fbbits = 5;
 	}
@@ -159,14 +159,14 @@
 
 	/* no space for FB */
 	if (!resmax) {
-		printk_err("VIA FB: no space for framebuffer in RAM\n");
+		printk(BIOS_ERR, "VIA FB: no space for framebuffer in RAM\n");
 		return;
 	}
 
 	proposed_base = resmax->base + resmax->size - fbsize;
 	resmax->size -= fbsize;
 
-	printk_info("K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
+	printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
 
 	/* Step 1: enable UMA but no FB */
 	pci_write_config8(dev, 0xa1, 0x80);
Index: src/southbridge/via/k8t890/k8t890_early_car.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_early_car.c	(revision 5263)
+++ src/southbridge/via/k8t890/k8t890_early_car.c	(working copy)
@@ -114,7 +114,7 @@
 
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
 	
-	printk_debug("Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
+	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 	switch (size) {
 	case 1:
 		outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
@@ -149,6 +149,6 @@
 		nvram_pos +=4;
 		break;
 	}
-	printk_debug("Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
+	printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
 	return nvram_pos;
 }
Index: src/southbridge/via/k8t890/k8m890_chrome.c
===================================================================
--- src/southbridge/via/k8t890/k8m890_chrome.c	(revision 5263)
+++ src/southbridge/via/k8t890/k8m890_chrome.c	(working copy)
@@ -125,7 +125,7 @@
 
 	fb_size = k8m890_host_fb_size_get();
 	if (!fb_size) {
-		printk_warning("Chrome: Device has not been initialised in the"
+		printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
 			       " ramcontroller!\n");
 		return;
 	}
@@ -133,11 +133,11 @@
 	fb_address = pci_read_config32(dev, 0x10);
 	fb_address &= ~0x0F;
 	if (!fb_address) {
-		printk_warning("Chrome: No FB BAR assigned!\n");
+		printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n");
 		return;
 	}
 
-	printk_info("Chrome: Using %dMB Framebuffer at 0x%08X.\n",
+	printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
 		    fb_size, fb_address);
 
 	//k8m890_host_fb_direct_set(fb_address);
@@ -154,7 +154,7 @@
 	vga_console_init();
 #endif
 
-	printk_info("Chrome VGA Textmode initialized.\n");
+	printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n");
 
 #if CONFIG_CONSOLE_VGA == 0
 	/* if we don't have console, at least print something... */
Index: src/southbridge/via/vt8231/vt8231_nic.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_nic.c	(revision 5263)
+++ src/southbridge/via/vt8231/vt8231_nic.c	(working copy)
@@ -12,7 +12,7 @@
 {
 	uint8_t		byte;
 
-	printk_debug("Configuring VIA LAN\n");
+	printk(BIOS_DEBUG, "Configuring VIA LAN\n");
 
 	/* We don't need stepping - though the device supports it */
 	byte = pci_read_config8(dev, PCI_COMMAND);
Index: src/southbridge/via/vt8231/vt8231_acpi.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_acpi.c	(revision 5263)
+++ src/southbridge/via/vt8231/vt8231_acpi.c	(working copy)
@@ -6,7 +6,7 @@
 
 static void acpi_init(struct device *dev)
 {
-	printk_debug("Configuring VIA ACPI\n");
+	printk(BIOS_DEBUG, "Configuring VIA ACPI\n");
 
 	// Set ACPI base address to IO 0x4000
 	pci_write_config32(dev, 0x48, 0x4001);
Index: src/southbridge/via/vt8231/vt8231_lpc.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_lpc.c	(revision 5263)
+++ src/southbridge/via/vt8231/vt8231_lpc.c	(working copy)
@@ -23,7 +23,7 @@
 static void pci_routing_fixup(struct device *dev)
 {
 
-	printk_info("%s: dev is %p\n", __func__, dev);
+	printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
 	if (dev) {
 		/* initialize PCI interupts - these assignments depend
 		   on the PCB routing of PINTA-D 
@@ -39,17 +39,17 @@
 	}
 
 	// Standard southbridge components
-	printk_info("setting southbridge\n");
+	printk(BIOS_INFO, "setting southbridge\n");
 	pci_assign_irqs(0, 0x11, southbridgeIrqs);
 
 	// Ethernet built into southbridge
-	printk_info("setting ethernet\n");
+	printk(BIOS_INFO, "setting ethernet\n");
 	pci_assign_irqs(0, 0x12, enetIrqs);
 
 	// PCI slot
-	printk_info("setting pci slot\n");
+	printk(BIOS_INFO, "setting pci slot\n");
 	pci_assign_irqs(0, 0x14, slotIrqs);
-	printk_info("%s: DONE\n", __func__);
+	printk(BIOS_INFO, "%s: DONE\n", __func__);
 }
 
 static void vt8231_init(struct device *dev)
@@ -57,7 +57,7 @@
 	unsigned char enables;
 	struct southbridge_via_vt8231_config *conf = dev->chip_info;
 
-	printk_debug("vt8231 init\n");
+	printk(BIOS_DEBUG, "vt8231 init\n");
 
 	// enable the internal I/O decode
 	enables = pci_read_config8(dev, 0x6C);
@@ -102,18 +102,18 @@
 	// First do some more things to devfn (17,0)
 	// note: this should already be cleared, according to the book. 
 	enables = pci_read_config8(dev, 0x50);
-	printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
+	printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
 	enables &= ~8; // need manifest constant here!
-	printk_debug("set IDE reg. 50 to 0x%x\n", enables);
+	printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
 	pci_write_config8(dev, 0x50, enables);
 	
 	// set default interrupt values (IDE)
 	enables = pci_read_config8(dev, 0x4c);
-	printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
+	printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
 	// clear out whatever was there. 
 	enables &= ~0xf;
 	enables |= 4;
-	printk_debug("setting reg. 4c to 0x%x\n", enables);
+	printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
 	pci_write_config8(dev, 0x4c, enables);
 	
 	// set up the serial port interrupts. 
Index: src/southbridge/via/vt8231/vt8231.c
===================================================================
--- src/southbridge/via/vt8231/vt8231.c	(revision 5263)
+++ src/southbridge/via/vt8231/vt8231.c	(working copy)
@@ -14,7 +14,7 @@
 
 void hard_reset(void)
 {
-        printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
+        printk(BIOS_ERR, "NO HARD RESET ON VT8231! FIX ME!\n");
 }
 
 static void keyboard_on(void)
Index: src/southbridge/via/vt8231/vt8231_ide.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_ide.c	(revision 5263)
+++ src/southbridge/via/vt8231/vt8231_ide.c	(working copy)
@@ -19,22 +19,22 @@
 		*/
 
 		/*		
-		printk_info("%s: enabling compatibility IDE addresses\n", __func__);
+		printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__);
 		enables = pci_read_config8(dev, 0x42);
-		printk_debug("enables in reg 0x42 0x%x\n", enables);
+		printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
 		enables &= ~0xc0;		// compatability mode
 		pci_write_config8(dev, 0x42, enables);
 		enables = pci_read_config8(dev, 0x42);
-		printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
+		printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables);
 		*/
 	}
 	
 	enables = pci_read_config8(dev, 0x40);
-	printk_debug("enables in reg 0x40 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
 	enables |= 3;
 	pci_write_config8(dev, 0x40, enables);
 	enables = pci_read_config8(dev, 0x40);
-	printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
 	
 	// Enable prefetch buffers
 	enables = pci_read_config8(dev, 0x41);
@@ -58,7 +58,7 @@
 	// kevinh@ispiri.com - the standard linux drivers seem ass slow when 
 	// used in native mode - I've changed back to classic
 	enables = pci_read_config8(dev, 0x9);
-	printk_debug("enables in reg 0x9 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
 	// by the book, set the low-order nibble to 0xa. 
 	if (conf->enable_native_ide) {
 		enables &= ~0xf;
@@ -70,11 +70,11 @@
 	
 	pci_write_config8(dev, 0x9, enables);
 	enables = pci_read_config8(dev, 0x9);
-	printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
 	
 	// standard bios sets master bit. 
 	enables = pci_read_config8(dev, 0x4);
-	printk_debug("command in reg 0x4 0x%x\n", enables);
+	printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
 	enables |= 7;
 	
 	// No need for stepping - kevinh@ispiri.com
@@ -82,7 +82,7 @@
 	
 	pci_write_config8(dev, 0x4, enables);
 	enables = pci_read_config8(dev, 0x4);
-	printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
 	
 	if (!conf->enable_native_ide) {
 		// Use compatability mode - per award bios
Index: src/southbridge/via/vt8235/vt8235_nic.c
===================================================================
--- src/southbridge/via/vt8235/vt8235_nic.c	(revision 5263)
+++ src/southbridge/via/vt8235/vt8235_nic.c	(working copy)
@@ -12,7 +12,7 @@
 {
 	uint8_t	byte;
 
-	printk_debug("Configuring VIA Rhine LAN\n");
+	printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n");
 
 	/* We don't need stepping - though the device supports it */
 	byte = pci_read_config8(dev, PCI_COMMAND);
Index: src/southbridge/via/vt8235/vt8235_usb.c
===================================================================
--- src/southbridge/via/vt8235/vt8235_usb.c	(revision 5263)
+++ src/southbridge/via/vt8235/vt8235_usb.c	(working copy)
@@ -9,7 +9,7 @@
 
 static void usb_init(struct device *dev)
 {
-	printk_debug("Configuring VIA USB 1.1\n");
+	printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n");
 
 	/* pci_write_config8(dev, 0x04, 0x07); */
 
Index: src/southbridge/via/vt8235/vt8235_lpc.c
===================================================================
--- src/southbridge/via/vt8235/vt8235_lpc.c	(revision 5263)
+++ src/southbridge/via/vt8235/vt8235_lpc.c	(working copy)
@@ -56,7 +56,7 @@
 
 static void pci_routing_fixup(struct device *dev)
 {
-	printk_info("%s: dev is %p\n", __func__, dev);
+	printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
 
 	/* set up PCI IRQ routing */
 	pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
@@ -65,38 +65,38 @@
 
 
 	// firewire built into southbridge
-	printk_info("setting firewire\n");
+	printk(BIOS_INFO, "setting firewire\n");
 	pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins));
 
 	// Standard usb components
-	printk_info("setting usb\n");
+	printk(BIOS_INFO, "setting usb\n");
 	pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
 
 	// VT8235 + sound hardware
-	printk_info("setting vt8235\n");
+	printk(BIOS_INFO, "setting vt8235\n");
 	pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins));
 
 	// Ethernet built into southbridge
-	printk_info("setting ethernet\n");
+	printk(BIOS_INFO, "setting ethernet\n");
 	pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
 
 	// VGA
-	printk_info("setting vga\n");
+	printk(BIOS_INFO, "setting vga\n");
 	pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
 
 	// PCI slot
-	printk_info("setting pci slot\n");
+	printk(BIOS_INFO, "setting pci slot\n");
 	pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
 
 	// Cardbus slot 
-	printk_info("setting cardbus slot\n");
+	printk(BIOS_INFO, "setting cardbus slot\n");
 	pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
 
 	// Via 2 slot riser card 2nd slot
-	printk_info("setting riser slot\n");
+	printk(BIOS_INFO, "setting riser slot\n");
 	pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
 
-	printk_spew("%s: DONE\n", __func__);
+	printk(BIOS_SPEW, "%s: DONE\n", __func__);
 }
 
 /* 
@@ -154,7 +154,7 @@
 {
 	unsigned char enables;
 	
-	printk_debug("vt8235 init\n");
+	printk(BIOS_DEBUG, "vt8235 init\n");
 
 	// enable the internal I/O decode
 	enables = pci_read_config8(dev, 0x6C);
Index: src/southbridge/via/vt8235/vt8235.c
===================================================================
--- src/southbridge/via/vt8235/vt8235.c	(revision 5263)
+++ src/southbridge/via/vt8235/vt8235.c	(working copy)
@@ -14,7 +14,7 @@
 
 void hard_reset(void) 
 {
-	printk_err("NO HARD RESET ON VT8235! FIX ME!\n");
+	printk(BIOS_ERR, "NO HARD RESET ON VT8235! FIX ME!\n");
 }
 
 static void keyboard_on(struct device *dev)
@@ -34,11 +34,11 @@
 	int i,j;
 	
 	for(i = 0; i < 256; i += 16) {
-		printk_debug("0x%x: ", i);
+		printk(BIOS_DEBUG, "0x%x: ", i);
 		for(j = 0; j < 16; j++) {
-			printk_debug("%02x ", pci_read_config8(dev0, i+j));
+			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev0, i+j));
 		}
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 
@@ -61,7 +61,7 @@
 	vendor = pci_read_config16(dev,0);
 	model = pci_read_config16(dev,0x2);
 
-	printk_debug("In vt8235_enable %04x %04x.\n",vendor,model);
+	printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
 	
 	/* if this is not the southbridge itself just return */
 	/* this is necessary because USB devices are slot 10, whereas this device is slot 11 
@@ -70,7 +70,7 @@
 	if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235))
 		return;
 
-	printk_debug("Initialising Devices\n");
+	printk(BIOS_DEBUG, "Initialising Devices\n");
 
 
 	setup_i8259();   // make sure interupt controller is configured before keyboard init 
Index: src/southbridge/via/vt8235/vt8235_ide.c
===================================================================
--- src/southbridge/via/vt8235/vt8235_ide.c	(revision 5263)
+++ src/southbridge/via/vt8235/vt8235_ide.c	(working copy)
@@ -10,7 +10,7 @@
 	struct southbridge_via_vt8235_config *conf = dev->chip_info;
 	unsigned char enables;
 
-	printk_info("Enabling VIA IDE.\n");
+	printk(BIOS_INFO, "Enabling VIA IDE.\n");
 
 	/*if (!conf->enable_native_ide) { */
 		/*
@@ -18,23 +18,23 @@
 		 * use PCI interrupts.  Using PCI ints confuses linux for some
 		 * reason.
 		 */
-		printk_info("%s: enabling compatibility IDE addresses\n",
+		printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n",
 				__func__);
 		enables = pci_read_config8(dev, 0x42);
-		printk_debug("enables in reg 0x42 0x%x\n", enables);
+		printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
 		enables &= ~0xc0;		// compatability mode
 		pci_write_config8(dev, 0x42, enables);
 		enables = pci_read_config8(dev, 0x42);
-		printk_debug("enables in reg 0x42 read back as 0x%x\n",
+		printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
 				enables);
 	/* } */
 	
 	enables = pci_read_config8(dev, 0x40);
-	printk_debug("enables in reg 0x40 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
 	enables |= 3;
 	pci_write_config8(dev, 0x40, enables);
 	enables = pci_read_config8(dev, 0x40);
-	printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
 	
 	// Enable prefetch buffers
 	enables = pci_read_config8(dev, 0x41);
@@ -58,7 +58,7 @@
 	// kevinh@ispiri.com - the standard linux drivers seem ass slow when 
 	// used in native mode - I've changed back to classic
 	enables = pci_read_config8(dev, 0x9);
-	printk_debug("enables in reg 0x9 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
 	// by the book, set the low-order nibble to 0xa. 
 	if (conf->enable_native_ide) {
 		enables &= ~0xf;
@@ -70,11 +70,11 @@
 	
 	pci_write_config8(dev, 0x9, enables);
 	enables = pci_read_config8(dev, 0x9);
-	printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
 	
 	// standard bios sets master bit. 
 	enables = pci_read_config8(dev, 0x4);
-	printk_debug("command in reg 0x4 0x%x\n", enables);
+	printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
 	enables |= 7;
 	
 	// No need for stepping - kevinh@ispiri.com
@@ -82,7 +82,7 @@
 	
 	pci_write_config8(dev, 0x4, enables);
 	enables = pci_read_config8(dev, 0x4);
-	printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
 	
 	if (!conf->enable_native_ide) {
 		// Use compatability mode - per award bios
Index: src/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- src/southbridge/amd/amd8132/amd8132_bridge.c	(revision 5263)
+++ src/southbridge/amd/amd8132/amd8132_bridge.c	(working copy)
@@ -107,7 +107,7 @@
 	/* How many siblings does this device have? */
 	sibs = info->master_devices - 1;
 
-	printk_debug("%s AMD8132 PCI-X tuning\n", dev_path(dev));
+	printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev));
 	status = pci_read_config32(dev, cap + PCI_X_STATUS);
 	orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
 
@@ -177,7 +177,7 @@
 	info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
 
 	/* Print the PCI-X bus speed */
-	printk_debug("PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
+	printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
 
 
 	/* Examine the bus and find out how loaded it is */
Index: src/southbridge/amd/cs5530/cs5530_vga.c
===================================================================
--- src/southbridge/amd/cs5530/cs5530_vga.c	(revision 5263)
+++ src/southbridge/amd/cs5530/cs5530_vga.c	(working copy)
@@ -460,7 +460,7 @@
 	gx_base = GX_BASE;
 	mode = modes[CONFIG_GX1_VIDEOMODE];
 
-	printk_debug("Setting up video mode %dx%d with %d Hz clock\n",
+	printk(BIOS_DEBUG, "Setting up video mode %dx%d with %d Hz clock\n",
 		mode->visible_pixel, mode->visible_lines, mode->pixel_clock);
 
 	cs5530_set_clock_frequency(io_base, mode->pll_value);
Index: src/southbridge/amd/cs5530/cs5530_ide.c
===================================================================
--- src/southbridge/amd/cs5530/cs5530_ide.c	(revision 5263)
+++ src/southbridge/amd/cs5530/cs5530_ide.c	(working copy)
@@ -55,9 +55,9 @@
 
 	pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
 
-	printk_info("%s IDE interface %s\n", "Primary",
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
 		    conf->ide0_enable ? "enabled" : "disabled");
-	printk_info("%s IDE interface %s\n", "Secondary",
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
 		    conf->ide1_enable ? "enabled" : "disabled");
 }
 
Index: src/southbridge/amd/rs690/rs690_ht.c
===================================================================
--- src/southbridge/amd/rs690/rs690_ht.c	(revision 5263)
+++ src/southbridge/amd/rs690/rs690_ht.c	(working copy)
@@ -53,7 +53,7 @@
 	/* Enable pci error detecting */
 	u32 dword;
 
-	printk_info("pcie_init in rs690_ht.c\n");
+	printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
Index: src/southbridge/amd/rs690/rs690_early_setup.c
===================================================================
--- src/southbridge/amd/rs690/rs690_early_setup.c	(revision 5263)
+++ src/southbridge/amd/rs690/rs690_early_setup.c	(working copy)
@@ -133,23 +133,23 @@
 	u32 eax, ebx, ecx, edx;
 	__asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
 			  :"0"(1));
-	printk_info("get_cpu_rev EAX=0x%x.\n", eax);
+	printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
 	if (eax <= 0xfff)
-		printk_info("CPU Rev is K8_Cx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
 	else if (eax <= 0x10fff)
-		printk_info("CPU Rev is K8_Dx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
 	else if (eax <= 0x20fff)
-		printk_info("CPU Rev is K8_Ex.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
 	else if (eax <= 0x40fff)
-		printk_info("CPU Rev is K8_Fx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
 	else if (eax == 0x60fb1 || eax == 0x60f81)	/*These two IDS are exception, they are G1. */
-		printk_info("CPU Rev is K8_G1.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
 	else if (eax <= 0X60FF0)
-		printk_info("CPU Rev is K8_G0.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
 	else if (eax <= 0x100000)
-		printk_info("CPU Rev is K8_G1.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
 	else
-		printk_info("CPU Rev is K8_10.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
 }
 
 static u8 get_nb_rev(device_t nb_dev)
@@ -197,19 +197,19 @@
 	************************/
 	reg = pci_read_config32(k8_f0, 0x88);
 	k8_ht_freq = (reg & 0xf00) >> 8;
-	printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+	printk(BIOS_SPEW, "rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
 	rs690_f0 = PCI_DEV(0, 0, 0);
 	reg8 = pci_read_config8(rs690_f0, 0x9c);
-	printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+	printk(BIOS_SPEW, "rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
 	/* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
 	 * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
 	 */
 	if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
-		printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+		printk(BIOS_INFO, "rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
 		reg8 |= 0x1;
 		pci_write_config8(rs690_f0, 0x9c, reg8);
 	} else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
-		printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+		printk(BIOS_INFO, "rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
 		reg8 &= ~0x1;
 		pci_write_config8(rs690_f0, 0x9c, reg8);
 	}
@@ -234,7 +234,7 @@
 	device_t k8_f0, k8_f2, k8_f3;
 	msr_t msr;
 
-	printk_info("k8_optimization()\n");
+	printk(BIOS_INFO, "k8_optimization()\n");
 	k8_f0 = PCI_DEV(0, 0x18, 0);
 	k8_f2 = PCI_DEV(0, 0x18, 2);
 	k8_f3 = PCI_DEV(0, 0x18, 3);
@@ -425,7 +425,7 @@
 *****************************************/
 static void rs690_por_init(device_t nb_dev)
 {
-	printk_info("rs690_por_init\n");
+	printk(BIOS_INFO, "rs690_por_init\n");
 	/* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */
 	rs690_por_pcicfg_init(nb_dev);
 
@@ -463,19 +463,19 @@
 static void rs690_early_setup()
 {
 	device_t nb_dev = PCI_DEV(0, 0, 0);
-	printk_info("rs690_early_setup()\n");
+	printk(BIOS_INFO, "rs690_early_setup()\n");
 
 	/*ATINB_PrepareInit */
 	get_cpu_rev();
 	switch (get_nb_rev(nb_dev)) {	/* PCIEMiscInit */
 	case 5:
-		printk_info("NB Revision is A11.\n");
+		printk(BIOS_INFO, "NB Revision is A11.\n");
 		break;
 	case 6:
-		printk_info("NB Revision is A12.\n");
+		printk(BIOS_INFO, "NB Revision is A12.\n");
 		break;
 	case 7:
-		printk_info("NB Revision is A21.\n");
+		printk(BIOS_INFO, "NB Revision is A21.\n");
 		break;
 	}
 
Index: src/southbridge/amd/rs690/rs690_cmn.c
===================================================================
--- src/southbridge/amd/rs690/rs690_cmn.c	(revision 5263)
+++ src/southbridge/amd/rs690/rs690_cmn.c	(working copy)
@@ -50,7 +50,7 @@
 {
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
-	printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+	printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.pci.devfn << 12 | reg;
@@ -63,7 +63,7 @@
 
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
-	/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+	/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);*/
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.pci.devfn << 12 | reg_pos;
@@ -253,7 +253,7 @@
 		mdelay(40);
 		udelay(200);
 		lc_state = nbpcie_p_read_index(dev, 0xa5);	/* lc_state */
-		printk_debug("PcieLinkTraining port=%x:lc current state=%x\n",
+		printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
 			     port, lc_state);
 		current = lc_state & 0x3f;	/* get LC_CURRENT_STATE, bit0-5 */
 
@@ -274,7 +274,7 @@
 			reg =
 			    pci_ext_read_config32(nb_dev, dev,
 						  PCIE_VC0_RESOURCE_STATUS);
-			printk_debug("PcieTrainPort reg=0x%x\n", reg);
+			printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
 			/* check bit1 */
 			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
 				/* set bit8=1, bit0-2=bit4-6 */
Index: src/southbridge/amd/rs690/rs690.c
===================================================================
--- src/southbridge/amd/rs690/rs690.c	(revision 5263)
+++ src/southbridge/amd/rs690/rs690.c	(working copy)
@@ -129,7 +129,7 @@
 	device_t nb_dev = 0, sb_dev = 0;
 	int dev_ind;
 
-	printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
+	printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
 
 	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
@@ -147,7 +147,7 @@
 	dev_ind = dev->path.pci.devfn >> 3;
 	switch (dev_ind) {
 	case 0:		/* bus0, dev0, fun0; */
-		printk_info("Bus-0, Dev-0, Fun-0.\n");
+		printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
 		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
 		config_gpp_core(nb_dev, sb_dev);
 		rs690_gpp_sb_init(nb_dev, sb_dev, 8);
@@ -159,11 +159,11 @@
 		break;
 
 	case 1:		/* bus0, dev1 */
-		printk_info("Bus-0, Dev-1, Fun-0.\n");
+		printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
 		break;
 	case 2:		/* bus0, dev2,3, two GFX */
 	case 3:
-		printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
+		printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
 				       (dev->enabled ? 0 : 1) << dev_ind);
 		if (dev->enabled)
@@ -173,7 +173,7 @@
 	case 5:
 	case 6:
 	case 7:
-		printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
+		printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
 			    dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
 				       (dev->enabled ? 0 : 1) << dev_ind);
@@ -181,7 +181,7 @@
 			rs690_gpp_sb_init(nb_dev, dev, dev_ind);
 		break;
 	case 8:		/* bus0, dev8, SB */
-		printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
+		printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
 				       (dev->enabled ? 1 : 0) << 6);
 		if (dev->enabled)
@@ -189,7 +189,7 @@
 		disable_pcie_bar3(nb_dev);
 		break;
 	default:
-		printk_debug("unknown dev: %s\n", dev_path(dev));
+		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
 	}
 }
 
Index: src/southbridge/amd/rs690/rs690_pcie.c
===================================================================
--- src/southbridge/amd/rs690/rs690_pcie.c	(revision 5263)
+++ src/southbridge/amd/rs690/rs690_pcie.c	(working copy)
@@ -110,7 +110,7 @@
 	/* Enable pci error detecting */
 	u32 dword;
 
-	printk_debug("pcie_init in rs690_pcie.c\n");
+	printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n");
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
@@ -168,7 +168,7 @@
 *****************************************************************/
 void enable_pcie_bar3(device_t nb_dev)
 {
-	printk_debug("enable_pcie_bar3()\n");
+	printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
 	set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
 
@@ -184,7 +184,7 @@
 *****************************************************************/
 void disable_pcie_bar3(device_t nb_dev)
 {
-	printk_debug("disable_pcie_bar3()\n");
+	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
 	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
 	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
@@ -206,7 +206,7 @@
 	device_t sb_dev;
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
-	printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
+	printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
 
 	/* init GPP core */
 	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,
@@ -262,7 +262,7 @@
 			PcieReleasePortTraining(nb_dev, dev, port);
 			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
 				u8 res = PcieTrainPort(nb_dev, dev, port);
-				printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res);
+				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
 				if (res) {
 					AtiPcieCfg.PortDetect |= 1 << port;
 				}
Index: src/southbridge/amd/rs690/rs690_gfx.c
===================================================================
--- src/southbridge/amd/rs690/rs690_gfx.c	(revision 5263)
+++ src/southbridge/amd/rs690/rs690_gfx.c	(working copy)
@@ -45,7 +45,7 @@
 static void clkind_write(device_t dev, u32 index, u32 data)
 {
 	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
-	/* printk_info("gfx bar 2 %02x\n", gfx_bar2); */
+	/* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */
 
 	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
 	*(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
@@ -57,7 +57,7 @@
 */
 static void rs690_gfx_read_resources(device_t dev)
 {
-	printk_info("rs690_gfx_read_resources.\n");
+	printk(BIOS_INFO, "rs690_gfx_read_resources.\n");
 
 	/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
 	   Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
@@ -77,7 +77,7 @@
 	    (struct southbridge_amd_rs690_config *)dev->chip_info;
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
 	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
-	printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
 	     deviceid, vendorid);
 
 	pci_dev_init(dev);
@@ -117,12 +117,12 @@
 	device_t k8_f0 = 0, k8_f2 = 0;
 	device_t nb_dev = dev_find_slot(0, 0);
 
-	printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
+	printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
 		    nb_dev);
 
 	/* set APERTURE_SIZE, 128M. */
 	l_dword = pci_read_config32(nb_dev, 0x8c);
-	printk_info("nb_dev, 0x8c=0x%x\n", l_dword);
+	printk(BIOS_INFO, "nb_dev, 0x8c=0x%x\n", l_dword);
 	l_dword &= 0xffffff8f;
 	pci_write_config32(nb_dev, 0x8c, l_dword);
 
@@ -231,13 +231,13 @@
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
 
-	printk_info("rs690_gfx_init single_port_configuration.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n");
 
 	/* step 12 training, releases hold training for GFX port 0 (device 2) */
 	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0<<4);
 	PcieReleasePortTraining(nb_dev, dev, 2);
 	result = PcieTrainPort(nb_dev, dev, 2);
-	printk_info("rs690_gfx_init single_port_configuration step12.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step12.\n");
 
 	/* step 13 Power Down Control */
 	/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
@@ -257,7 +257,7 @@
 
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
-		printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -274,11 +274,11 @@
 			break;
 		}
 	}
-	printk_info("rs690_gfx_init single_port_configuration step13.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step13.\n");
 
 	/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
 	set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
-	printk_info("rs690_gfx_init single_port_configuration step14.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step14.\n");
 }
 
 /* step 15 ~ step 18 from rpr */
@@ -305,7 +305,7 @@
 
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
-		printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -335,7 +335,7 @@
 
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
-		printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -413,13 +413,13 @@
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
 
-	printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+	printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
 		    nb_dev, dev, port);
 
 	/* step 0, REFCLK_SEL, skip A11 revision */
 	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 9,
 			       cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9);
-	printk_info("rs690_gfx_init step0.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step0.\n");
 
 	/* step 1, lane reversal (only need if CMOS option is enabled) */
 	if (cfg->gfx_lane_reversal) {
@@ -427,13 +427,13 @@
 		if (cfg->gfx_dual_slot)
 			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
 	}
-	printk_info("rs690_gfx_init step1.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step1.\n");
 
 	/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
 	/* AMD calls the configuration CrossFire */
 	if (cfg->gfx_dual_slot)
 		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
-	printk_info("rs690_gfx_init step2.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step2.\n");
 
 	/* step 2, TMDS, (only need if CMOS option is enabled) */
 	if (cfg->gfx_tmds) {
@@ -461,7 +461,7 @@
 
 	/* step 4.6 bring external GFX device out of reset, wait for 1ms */
 	mdelay(1);
-	printk_info("rs690_gfx_init step4.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step4.\n");
 
 	/* step 5 program PCIE memory mapped configuration space */
 	/* done by enable_pci_bar3() before */
@@ -508,7 +508,7 @@
                 set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
         }
 
-        printk_info("rs690_gfx_init step6.\n");
+        printk(BIOS_INFO, "rs690_gfx_init step6.\n");
 
 	/* step 7 compliance state, (only need if CMOS option is enabled) */
 	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
@@ -518,64 +518,64 @@
 		/* release hold training for device 2. GFX initialization is done. */
 		set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
 		dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
-		printk_info("rs690_gfx_init step7.\n");
+		printk(BIOS_INFO, "rs690_gfx_init step7.\n");
 		return;
 	}
 
 	/* step 8 common initialization */
 	/* step 8.1 sets RCB timeout to be 25ms */
 	set_pcie_enable_bits(dev, 0x70, 7 << 16, 3 << 16);
-	printk_info("rs690_gfx_init step8.1.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.1.\n");
 
 	/* step 8.2 disables slave ordering logic */
 	set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
-	printk_info("rs690_gfx_init step8.2.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.2.\n");
 
 	/* step 8.3 sets DMA payload size to 64 bytes */
 	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
-	printk_info("rs690_gfx_init step8.3.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.3.\n");
 
 	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
 	 * time out and go back to Detect Idle.*/
 	set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14);
-	printk_info("rs690_gfx_init step8.4.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.4.\n");
 
 	/* step 8.5 shortens the enumeration timer */
 	set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
-	printk_info("rs690_gfx_init step8.5.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.5.\n");
 
 	/* step 8.6 blocks DMA traffic during C3 state */
 	set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
-	printk_info("rs690_gfx_init step8.6.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.6.\n");
 
 	/* step 8.7 Do not gate the electrical idle form the PHY
 	 * step 8.8 Enables the escape from L1L23 */
 	set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30);
-	printk_info("rs690_gfx_init step8.8.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.8.\n");
 
 	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
 	 * SLOT_IMPLEMENTED@PCIE_CAP */
 	reg16 = pci_read_config16(dev, 0x5a);
 	reg16 |= 0x100;
 	pci_write_config16(dev, 0x5a, reg16);
-	printk_info("rs690_gfx_init step8.9.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.9.\n");
 
 	/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider.
 	 * This will workaround several failures reported by the PCI Compliance test under Vista DTM. */
 	set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 31, 0 << 31);
-	printk_info("rs690_gfx_init step8.10.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.10.\n");
 
 	/* step 8.11 Sets REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. */
 	set_pcie_enable_bits(nb_dev, 0x02, 1 << 0, 1 << 0);
-	printk_info("rs690_gfx_init step8.11.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.11.\n");
 
 	/* step 8.12 Sets REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */
 	set_pcie_enable_bits(nb_dev, 0x02, 1 << 6, 1 << 6);
-	printk_info("rs690_gfx_init step8.12.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.12.\n");
 
 	/* step 8.13 Sets CMGOOD_OVERRIDE. */
 	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
-	printk_info("rs690_gfx_init step8.13.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.13.\n");
 
 	/* step 9 Enable TLP Flushing, for non-AMD GFX devices and Hot-Plug devices only. */
 	/* skip */
@@ -619,7 +619,7 @@
 		dual_port_configuration(nb_dev, dev);
 		break;
 	default:
-		printk_info("Incorrect configuration of external gfx slot.\n");
+		printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n");
 		break;
 	}
 }
Index: src/southbridge/amd/rs780/rs780_ht.c
===================================================================
--- src/southbridge/amd/rs780/rs780_ht.c	(revision 5263)
+++ src/southbridge/amd/rs780/rs780_ht.c	(working copy)
@@ -53,7 +53,7 @@
 	/* Enable pci error detecting */
 	u32 dword;
 
-	printk_info("pcie_init in rs780_ht.c\n");
+	printk(BIOS_INFO, "pcie_init in rs780_ht.c\n");
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
Index: src/southbridge/amd/rs780/rs780_early_setup.c
===================================================================
--- src/southbridge/amd/rs780/rs780_early_setup.c	(revision 5263)
+++ src/southbridge/amd/rs780/rs780_early_setup.c	(working copy)
@@ -147,25 +147,25 @@
 	u32 eax;
 
 	eax = cpuid_eax(1);
-	printk_info("get_cpu_rev EAX=0x%x.\n", eax);
+	printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
 	if (eax <= 0xfff)
-		printk_info("CPU Rev is K8_Cx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
 	else if (eax <= 0x10fff)
-		printk_info("CPU Rev is K8_Dx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
 	else if (eax <= 0x20fff)
-		printk_info("CPU Rev is K8_Ex.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
 	else if (eax <= 0x40fff)
-		printk_info("CPU Rev is K8_Fx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
 	else if (eax == 0x60fb1 || eax == 0x60f81)	/*These two IDS are exception, they are G1. */
-		printk_info("CPU Rev is K8_G1.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
 	else if (eax <= 0X60FF0)
-		printk_info("CPU Rev is K8_G0.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
 	else if (eax <= 0x100000)
-		printk_info("CPU Rev is K8_G1.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
 	else if (eax <= 0x100f00)
-		printk_info("CPU Rev is Fam 10.\n");
+		printk(BIOS_INFO, "CPU Rev is Fam 10.\n");
 	else
-		printk_info("CPU Rev is K8_10.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
 }
 
 static u8 is_famly10()
@@ -246,7 +246,7 @@
 	************************/
 	reg = pci_read_config32(cpu_f0, 0x88);
 	cpu_ht_freq = (reg & 0xf00) >> 8;
-	printk_info("rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
+	printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
 	rs780_f0 = PCI_DEV(0, 0, 0);
 	//set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28);
 
@@ -260,7 +260,7 @@
 	 * So we check 6 only, it would be faster. */
 	if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) ||
 		(cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) {
-		printk_info("rs780_htinit: HT1 mode\n");
+		printk(BIOS_INFO, "rs780_htinit: HT1 mode\n");
 
 		/* HT1 mode, RPR 8.4.2 */
 		/* set IBIAS code */
@@ -268,7 +268,7 @@
 		/* Optimizes chipset HT transmitter drive strength */
 		set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
 	} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
-		printk_info("rs780_htinit: HT3 mode\n");
+		printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
 
 		#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
 		/* HT3 mode, RPR 8.4.3 */
@@ -330,7 +330,7 @@
 	device_t k8_f0, k8_f2, k8_f3;
 	msr_t msr;
 
-	printk_info("k8_optimization()\n");
+	printk(BIOS_INFO, "k8_optimization()\n");
 	k8_f0 = PCI_DEV(0, 0x18, 0);
 	k8_f2 = PCI_DEV(0, 0x18, 2);
 	k8_f3 = PCI_DEV(0, 0x18, 3);
@@ -373,7 +373,7 @@
 	msr_t msr;
 	u32 val;
 
-	printk_info("fam10_optimization()\n");
+	printk(BIOS_INFO, "fam10_optimization()\n");
 
 	cpu_f0 = PCI_DEV(0, 0x18, 0);
 	cpu_f2 = PCI_DEV(0, 0x18, 2);
@@ -612,7 +612,7 @@
 *****************************************/
 static void rs780_por_init(device_t nb_dev)
 {
-	printk_info("rs780_por_init\n");
+	printk(BIOS_INFO, "rs780_por_init\n");
 	/* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */
 	rs780_por_pcicfg_init(nb_dev);
 
@@ -642,20 +642,20 @@
 static void rs780_early_setup()
 {
 	device_t nb_dev = PCI_DEV(0, 0, 0);
-	printk_info("rs780_early_setup()\n");
+	printk(BIOS_INFO, "rs780_early_setup()\n");
 
 	get_cpu_rev();
 
-	/* The printk_info(s) below cause the system unstable. */
+	/* The printk(BIOS_INFO, s) below cause the system unstable. */
 	switch (get_nb_rev(nb_dev)) {
 	case REV_RS780_A11:
-		/* printk_info("NB Revision is A11.\n"); */
+		/* printk(BIOS_INFO, "NB Revision is A11.\n"); */
 		break;
 	case REV_RS780_A12:
-		/* printk_info("NB Revision is A12.\n"); */
+		/* printk(BIOS_INFO, "NB Revision is A12.\n"); */
 		break;
 	case REV_RS780_A13:
-		/* printk_info("NB Revision is A13.\n"); */
+		/* printk(BIOS_INFO, "NB Revision is A13.\n"); */
 		break;
 	}
 
Index: src/southbridge/amd/rs780/rs780_cmn.c
===================================================================
--- src/southbridge/amd/rs780/rs780_cmn.c	(revision 5263)
+++ src/southbridge/amd/rs780/rs780_cmn.c	(working copy)
@@ -48,7 +48,7 @@
 {
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
-	printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+	printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.pci.devfn << 12 | reg;
@@ -61,7 +61,7 @@
 
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
-	/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+	/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);*/
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.pci.devfn << 12 | reg_pos;
@@ -271,7 +271,7 @@
 		mdelay(40);
 		udelay(200);
 		lc_state = nbpcie_p_read_index(dev, 0xa5);	/* lc_state */
-		printk_debug("PcieLinkTraining port=%x:lc current state=%x\n",
+		printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
 			     port, lc_state);
 		current = lc_state & 0x3f;	/* get LC_CURRENT_STATE, bit0-5 */
 
@@ -297,7 +297,7 @@
 			reg |= lane_mask << 8 | lane_mask;
 			reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */
 			nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg);
-			printk_debug("link_width=%x, lane_mask=%x",
+			printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x",
 				     current_link_width, lane_mask);
 			set_pcie_reset();
 			mdelay(1);
@@ -311,7 +311,7 @@
 			reg =
 			    pci_ext_read_config32(nb_dev, dev,
 						  PCIE_VC0_RESOURCE_STATUS);
-			printk_debug("PcieTrainPort reg=0x%x\n", reg);
+			printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
 			/* check bit1 */
 			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
 				/* set bit8=1, bit0-2=bit4-6 */
Index: src/southbridge/amd/rs780/rs780.c
===================================================================
--- src/southbridge/amd/rs780/rs780.c	(revision 5263)
+++ src/southbridge/amd/rs780/rs780.c	(working copy)
@@ -120,9 +120,9 @@
 
 	/* Program NB PCI table. */
 	temp16 = pci_read_config16(nb_dev, 0x04);
-	printk_debug("NB_PCI_REG04 = %x.\n", temp16);
+	printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16);
 	temp32 = pci_read_config32(nb_dev, 0x84);
-	printk_debug("NB_PCI_REG84 = %x.\n", temp32);
+	printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32);
 
 	pci_write_config8(nb_dev, 0x4c, 0x42);
 
@@ -131,7 +131,7 @@
 	pci_write_config8(nb_dev, 0x4e, temp8);
 
 	temp32 = pci_read_config32(nb_dev, 0x4c);
-	printk_debug("NB_PCI_REG4C = %x.\n", temp32);
+	printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
 
 	/* disable GFX debug. */
 	temp8 = pci_read_config8(nb_dev, 0x8d);
@@ -250,7 +250,7 @@
 
 	/* Enable PCIe configuration space. */
 	set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28);
-	printk_info("GC is accessible from now on.\n");
+	printk(BIOS_INFO, "GC is accessible from now on.\n");
 }
 
 /***********************************************
@@ -272,7 +272,7 @@
 	device_t nb_dev = 0, sb_dev = 0;
 	int dev_ind;
 
-	printk_info("rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
+	printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
 
 	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
@@ -290,7 +290,7 @@
 	dev_ind = dev->path.pci.devfn >> 3;
 	switch (dev_ind) {
 	case 0:		/* bus0, dev0, fun0; */
-		printk_info("Bus-0, Dev-0, Fun-0.\n");
+		printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
 		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
 		config_gpp_core(nb_dev, sb_dev);
 		rs780_gpp_sb_init(nb_dev, sb_dev, 8);
@@ -304,12 +304,12 @@
 		break;
 
 	case 1: /* bus0, dev1, APC. */
-		printk_info("Bus-0, Dev-1, Fun-0.\n");
+		printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
 		rs780_nb_gfx_dev_table(nb_dev, dev);
 		break;
 	case 2:		/* bus0, dev2,3, two GFX */
 	case 3:
-		printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
+		printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
 				       (dev->enabled ? 0 : 1) << dev_ind);
 		if (dev->enabled)
@@ -319,7 +319,7 @@
 	case 5:
 	case 6:
 	case 7:
-		printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
+		printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
 			    dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
 				       (dev->enabled ? 0 : 1) << dev_ind);
@@ -327,7 +327,7 @@
 			rs780_gpp_sb_init(nb_dev, dev, dev_ind);
 		break;
 	case 8:		/* bus0, dev8, SB */
-		printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
+		printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
 				       (dev->enabled ? 1 : 0) << 6);
 		if (dev->enabled)
@@ -336,7 +336,7 @@
 		break;
 	case 9:		/* bus 0, dev 9,10, GPP */
 	case 10:
-		printk_info("Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
+		printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
 			    dev->enabled);
 		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
@@ -346,7 +346,7 @@
 		/* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
 		break;
 	default:
-		printk_debug("unknown dev: %s\n", dev_path(dev));
+		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
 	}
 }
 
Index: src/southbridge/amd/rs780/rs780_pcie.c
===================================================================
--- src/southbridge/amd/rs780/rs780_pcie.c	(revision 5263)
+++ src/southbridge/amd/rs780/rs780_pcie.c	(working copy)
@@ -106,7 +106,7 @@
 	/* Enable pci error detecting */
 	u32 dword;
 
-	printk_debug("pcie_init in rs780_pcie.c\n");
+	printk(BIOS_DEBUG, "pcie_init in rs780_pcie.c\n");
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
@@ -216,7 +216,7 @@
 *****************************************************************/
 void enable_pcie_bar3(device_t nb_dev)
 {
-	printk_debug("enable_pcie_bar3()\n");
+	printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
 	set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
 
@@ -232,7 +232,7 @@
 *****************************************************************/
 void disable_pcie_bar3(device_t nb_dev)
 {
-	printk_debug("disable_pcie_bar3()\n");
+	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
 	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
 	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
@@ -255,7 +255,7 @@
 	u32 gfx_gpp_sb_sel;
 	struct southbridge_amd_rs780_config *cfg =
 	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
-	printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port);
+	printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port);
 
 	gfx_gpp_sb_sel = port >= 4 && port <= 8 ?
 				PCIE_CORE_INDEX_GPPSB :		/* 4,5,6,7,8 */
@@ -369,7 +369,7 @@
 			PcieReleasePortTraining(nb_dev, dev, port);
 			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
 				u8 res = PcieTrainPort(nb_dev, dev, port);
-				printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res);
+				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
 				if (res) {
 					AtiPcieCfg.PortDetect |= 1 << port;
 				}
Index: src/southbridge/amd/rs780/rs780_gfx.c
===================================================================
--- src/southbridge/amd/rs780/rs780_gfx.c	(revision 5263)
+++ src/southbridge/amd/rs780/rs780_gfx.c	(working copy)
@@ -55,7 +55,7 @@
 static void clkind_write(device_t dev, u32 index, u32 data)
 {
 	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
-	/* printk_info("gfx bar 2 %02x\n", gfx_bar2); */
+	/* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */
 
 	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
 	*(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
@@ -67,7 +67,7 @@
 */
 static void rs780_gfx_read_resources(device_t dev)
 {
-	printk_info("rs780_gfx_read_resources.\n");
+	printk(BIOS_INFO, "rs780_gfx_read_resources.\n");
 
 	/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
 	   Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
@@ -189,7 +189,7 @@
 		{
 			tempdev = dev_find_slot(Bus, Dev << 3);
 			Value = pci_read_config32(tempdev, 0);
-			printk_debug("Dev ID %x \n", Value);
+			printk(BIOS_DEBUG, "Dev ID %x \n", Value);
 			if((Value & 0xffff) == 0x1102)
 			{//Creative
 				//Found Creative SB
@@ -220,7 +220,7 @@
 						}
 					}
 				}
-				printk_debug(" MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
+				printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
 				if (MMIOStart < MMIOLimit)
 				{
 					Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
@@ -310,7 +310,7 @@
 
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
 	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
-	printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
 	     deviceid, vendorid);
 
 	command = pci_read_config16(dev, 0x04);
@@ -420,7 +420,7 @@
 	vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */
 	vgainfo.ulReserved1[0] = 0;	vgainfo.ulReserved1[1] = 0;
 	value = pci_read_config32(k8_f2, 0x94);
-	printk_debug("MEMCLK = %x\n", value&0x7);
+	printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7);
 	vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */
 	vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */
 	vgainfo.ulMinSidePortClock = 0; /* disable SP. */
@@ -447,14 +447,14 @@
 	vgainfo.usBootUpNBVoltage = 0x1a;
 
 	value = pci_read_config32(nb_dev, 0xd0);
-	printk_debug("NB HT speed = %x.\n", value);
+	printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
 	value = pci_read_config32(k8_f0, 0x88);
-	printk_debug("CPU HT speed = %x.\n", value);
+	printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
 	vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
 
 	/* HT width. */
 	value = pci_read_config32(nb_dev, 0xc8);
-	printk_debug("HT width = %x.\n", value);
+	printk(BIOS_DEBUG, "HT width = %x.\n", value);
 	vgainfo.usMinHTLinkWidth = 16;
 	vgainfo.usMaxHTLinkWidth = 16;
 	vgainfo.usUMASyncStartDelay = 322;
@@ -585,10 +585,10 @@
 	u32 FB_Start, FB_End;
 #endif
 
-	printk_info("rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
+	printk(BIOS_INFO, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
 
 	sysmem = rdmsr(0xc001001a);
-	printk_info("sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
+	printk(BIOS_INFO, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
 
 	/* The system top memory in 780. */
 	pci_write_config32(nb_dev, 0x90, sysmem.lo);
@@ -826,12 +826,12 @@
 	struct southbridge_amd_rs780_config *cfg =
 	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
 
-	printk_info("rs780_gfx_init single_port_configuration.\n");
+	printk(BIOS_INFO, "rs780_gfx_init single_port_configuration.\n");
 
 	/* step 12 training, releases hold training for GFX port 0 (device 2) */
 	PcieReleasePortTraining(nb_dev, dev, 2);
 	result = PcieTrainPort(nb_dev, dev, 2);
-	printk_info("rs780_gfx_init single_port_configuration step12.\n");
+	printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step12.\n");
 
 	/* step 13 Power Down Control */
 	/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
@@ -851,7 +851,7 @@
 		set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
 		reg32 = nbpcie_p_read_index(dev, 0x29);
 		width = reg32 & 0xFF;
-		printk_debug("GFX Inactive Lanes = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -868,11 +868,11 @@
 			break;
 		}
 	}
-	printk_info("rs780_gfx_init single_port_configuration step13.\n");
+	printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step13.\n");
 
 	/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
 	set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
-	printk_info("rs780_gfx_init single_port_configuration step14.\n");
+	printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step14.\n");
 }
 
 static void dual_port_configuration(device_t nb_dev, device_t dev)
@@ -905,7 +905,7 @@
 	} else {		/* step 16.b Link Training was successful */
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
-		printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -983,7 +983,7 @@
 	struct southbridge_amd_rs780_config *cfg =
 	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
 
-	printk_info("rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+	printk(BIOS_INFO, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
 		    nb_dev, dev, port);
 
 	/* GFX Core Initialization */
@@ -995,13 +995,13 @@
 		if (cfg->gfx_dual_slot)
 			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
 	}
-	printk_info("rs780_gfx_init step1.\n");
+	printk(BIOS_INFO, "rs780_gfx_init step1.\n");
 
 	/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
 	/* AMD calls the configuration CrossFire */
 	if (cfg->gfx_dual_slot)
 		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
-	printk_info("rs780_gfx_init step2.\n");
+	printk(BIOS_INFO, "rs780_gfx_init step2.\n");
 
 	/* step 2, TMDS, (only need if CMOS option is enabled) */
 	if (cfg->gfx_tmds) {
@@ -1020,7 +1020,7 @@
 	set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
 			       1 << 6 | 1 << 8 | 1 << 10);
 	reg32 = nbmisc_read_index(nb_dev, 0x28);
-	printk_info("misc 28 = %x\n", reg32);
+	printk(BIOS_INFO, "misc 28 = %x\n", reg32);
 
 	/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
 	set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
@@ -1038,7 +1038,7 @@
 	set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
 			       0);
 	reg32 = nbmisc_read_index(nb_dev, 0x28);
-	printk_info("misc 28 = %x\n", reg32);
+	printk(BIOS_INFO, "misc 28 = %x\n", reg32);
 
 	/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
 	set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
@@ -1079,7 +1079,7 @@
 		/* release hold training for device 2. GFX initialization is done. */
 		set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
 		dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
-		printk_info("rs780_gfx_init step7.\n");
+		printk(BIOS_INFO, "rs780_gfx_init step7.\n");
 		return;
 	}
 
@@ -1087,11 +1087,11 @@
 	/* 5.9.12.1 sets RCB timeout to be 25ms */
 	/* 5.9.12.2. RCB Cpl timeout on link down. */
 	set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
-	printk_info("rs780_gfx_init step5.9.12.1.\n");
+	printk(BIOS_INFO, "rs780_gfx_init step5.9.12.1.\n");
 
 	/* step 5.9.12.3 disables slave ordering logic */
 	set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
-	printk_info("rs780_gfx_init step5.9.12.3.\n");
+	printk(BIOS_INFO, "rs780_gfx_init step5.9.12.3.\n");
 
 	/* step 5.9.12.4 sets DMA payload size to 64 bytes */
 	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
@@ -1113,7 +1113,7 @@
 
 	/* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
 	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
-	printk_info("rs780_gfx_init step5.9.12.9.\n");
+	printk(BIOS_INFO, "rs780_gfx_init step5.9.12.9.\n");
 
 	/* 5.9.12.10 Sets the timer in Config state from 20us to */
 	/* 5.9.12.11 De-asserts RX_EN in L0s. */
@@ -1188,7 +1188,7 @@
 		dual_port_configuration(nb_dev, dev);
 		break;
 	default:
-		printk_info("Incorrect configuration of external gfx slot.\n");
+		printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n");
 		break;
 	}
 }
Index: src/southbridge/amd/cs5535/cs5535.c
===================================================================
--- src/southbridge/amd/cs5535/cs5535.c	(revision 5263)
+++ src/southbridge/amd/cs5535/cs5535.c	(working copy)
@@ -39,14 +39,14 @@
 
 	*flash = 0xf0;
 
-	printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
+	printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
 #endif
 }
 
 	
 static void southbridge_init(struct device *dev)
 {
-	printk_spew("cs5535: %s\n", __func__);
+	printk(BIOS_SPEW, "cs5535: %s\n", __func__);
 	nvram_on(dev);
 }
 
@@ -56,17 +56,17 @@
 	int i, j;
 
 	for(i=0; i<256; i+=16) {
-		printk_debug("0x%02x: ", i);
+		printk(BIOS_DEBUG, "0x%02x: ", i);
 		for(j=0; j<16; j++)
-			printk_debug("%02x ", pci_read_config8(dev, i+j));
-		printk_debug("\n");
+			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 */
 
 static void southbridge_enable(struct device *dev)
 {
-	printk_spew("%s: dev is %p\n", __func__, dev);
+	printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);
 }
 
 static void cs5535_read_resources(device_t dev)
@@ -89,7 +89,7 @@
 
 static void cs5535_pci_dev_enable_resources(device_t dev)
 {
-	printk_spew("cs5535.c: %s()\n", __func__);
+	printk(BIOS_SPEW, "cs5535.c: %s()\n", __func__);
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
 }
Index: src/southbridge/amd/cs5535/cs5535_ide.c
===================================================================
--- src/southbridge/amd/cs5535/cs5535_ide.c	(revision 5263)
+++ src/southbridge/amd/cs5535/cs5535_ide.c	(working copy)
@@ -7,12 +7,12 @@
 
 static void ide_init(struct device *dev)
 {
-	printk_spew("cs5535_ide: %s\n", __func__);
+	printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
 }
 
 static void ide_enable(struct device *dev)
 {
-	printk_spew("cs5535_ide: %s\n", __func__);
+	printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
 }
 
 static struct device_operations ide_ops = {
Index: src/southbridge/amd/cs5536/cs5536.c
===================================================================
--- src/southbridge/amd/cs5536/cs5536.c	(revision 5263)
+++ src/southbridge/amd/cs5536/cs5536.c	(working copy)
@@ -155,10 +155,10 @@
 	int i;
 	int numEnabled = 0;
 
-	printk_debug("ChipsetFlashSetup: Start\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n");
 	for (i = 0; i < FlashInitTableLen; i++) {
 		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
-			printk_debug("Enable CS%d\n", i);
+			printk(BIOS_DEBUG, "Enable CS%d\n", i);
 			/* we need to configure the memory/IO mask */
 			msr = rdmsr(FlashPort[i]);
 			msr.hi = 0;	/* start with the "enabled" bit clear */
@@ -171,14 +171,14 @@
 			else
 				msr.hi &= ~0x00000004;
 			msr.hi |= FlashInitTable[i].fMask;
-			printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
+			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
 				     msr.hi, msr.lo);
 			wrmsr(FlashPort[i], msr);
 
 			/* now write-enable the device */
 			msr = rdmsr(MDD_NORF_CNTRL);
 			msr.lo |= (1 << i);
-			printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
+			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
 				     msr.hi, msr.lo);
 			wrmsr(MDD_NORF_CNTRL, msr);
 
@@ -187,7 +187,7 @@
 		}
 	}
 
-	printk_debug("ChipsetFlashSetup: Finish\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n");
 
 }
 
@@ -566,7 +566,7 @@
 	}
 
 	/*      Flash BAR size Setup */
-	printk_err("%sDoing ChipsetFlashSetup()\n",
+	printk(BIOS_ERR, "%sDoing ChipsetFlashSetup()\n",
 		   sb->enable_ide_nand_flash == 1 ? "" : "Not ");
 	if (sb->enable_ide_nand_flash == 1)
 		ChipsetFlashSetup();
@@ -594,7 +594,7 @@
 	 * unsigned short gpiobase = MDD_GPIO;
 	 */
 
-	printk_err("cs5536: %s\n", __func__);
+	printk(BIOS_ERR, "cs5536: %s\n", __func__);
 	setup_i8259();
 	lpc_init(sb);
 	uarts_init(sb);
@@ -606,7 +606,7 @@
 			(sb->enable_gpio_int_route >> 16));
 	}
 
-	printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __func__,
+	printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__,
 		   sb->enable_ide_nand_flash);
 	if (sb->enable_ide_nand_flash == 1) {
 		enable_ide_nand_flash_header();
@@ -616,7 +616,7 @@
 
 	/* disable unwanted virtual PCI devices */
 	for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
-		printk_debug("Disabling VPCI device: 0x%08X\n",
+		printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n",
 			     sb->unwanted_vpci[i]);
 		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
 		outl(0xDEADBEEF, 0xCFC);
@@ -644,13 +644,13 @@
 
 static void southbridge_enable(struct device *dev)
 {
-	printk_err("cs5536: %s: dev is %p\n", __func__, dev);
+	printk(BIOS_ERR, "cs5536: %s: dev is %p\n", __func__, dev);
 
 }
 
 static void cs5536_pci_dev_enable_resources(device_t dev)
 {
-	printk_err("cs5536: %s()\n", __func__);
+	printk(BIOS_ERR, "cs5536: %s()\n", __func__);
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
 }
Index: src/southbridge/amd/cs5536/cs5536_smbus2.h
===================================================================
--- src/southbridge/amd/cs5536/cs5536_smbus2.h	(revision 5263)
+++ src/southbridge/amd/cs5536/cs5536_smbus2.h	(working copy)
@@ -78,7 +78,7 @@
 		if ((val & SMB_STS_SDAST) != 0)
 			break;
 		if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
-			printk_debug("SMBUS WAIT ERROR %x\n", val);
+			printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val);
 			return SMBUS_ERROR;
 		}
 	} while (--loops);
@@ -171,7 +171,7 @@
 	/* check for bus conflict and NACK */
 	val = inb(smbus_io_base + SMB_STS);
 	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
-		printk_debug("SEND SLAVE ERROR (%x)\n", val);
+		printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val);
 		return SMBUS_ERROR;
 	}
 	return smbus_wait(smbus_io_base);
@@ -250,7 +250,7 @@
 	return;
 
       err:
-	printk_debug("SMBUS READ ERROR (%d): %d\n", index, ret);
+	printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret);
 }
 
 static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
@@ -300,7 +300,7 @@
 	return 0;
 
       err:
-	printk_debug("SMBUS WRITE ERROR: %d\n", ret);
+	printk(BIOS_DEBUG, "SMBUS WRITE ERROR: %d\n", ret);
 	return -1;
 }
 
Index: src/southbridge/amd/cs5536/cs5536_ide.c
===================================================================
--- src/southbridge/amd/cs5536/cs5536_ide.c	(revision 5263)
+++ src/southbridge/amd/cs5536/cs5536_ide.c	(working copy)
@@ -36,7 +36,7 @@
 {
 	uint32_t ide_cfg;
 
-	printk_spew("cs5536_ide: %s\n", __func__);
+	printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
 	/* GPIO and IRQ setup are handled in the main chipset code. */
 
 	// Enable the channel and Post Write Buffer
@@ -49,7 +49,7 @@
 static void ide_enable(struct device *dev)
 {
 
-	printk_spew("cs5536_ide: %s\n", __func__);
+	printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
 
 }
 
Index: src/southbridge/amd/cs5536/cs5536_early_smbus.c
===================================================================
--- src/southbridge/amd/cs5536/cs5536_early_smbus.c	(revision 5263)
+++ src/southbridge/amd/cs5536/cs5536_early_smbus.c	(working copy)
@@ -53,7 +53,7 @@
 		if ((val & SMB_STS_SDAST) != 0)
 			break;
 		if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
-			/*printk_debug("SMBUS WAIT ERROR %x\n", val); */
+			/*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
 			return SMBUS_ERROR;
 		}
 	} while (--loops);
@@ -123,7 +123,7 @@
 	/* check for bus conflict and NACK */
 	val = inb(smbus_io_base + SMB_STS);
 	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
-		/* printk_debug("SEND SLAVE ERROR (%x)\n", val); */
+		/* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
 		return SMBUS_ERROR;
 	}
 	return smbus_wait(smbus_io_base);
Index: src/southbridge/amd/sb600/sb600_sata.c
===================================================================
--- src/southbridge/amd/sb600/sb600_sata.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600_sata.c	(working copy)
@@ -35,22 +35,22 @@
 	while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
 		(byte != (0xA0 + 0x10 * (portnum % 2))) ||
 		((byte2 & 0x88) != 0)) {
-		printk_spew("0x6=%x, 0x7=%x\n", byte, byte2);
+		printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
 		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
 			/* This will happen at the first iteration of this loop
 			 * if the first SATA port is unpopulated and the
 			 * second SATA port is poulated.
 			 */
-			printk_debug("drive no longer selected after %i ms, "
+			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
 				"retrying init\n", i * 10);
 			return 1;
 		} else
-			printk_spew("drive detection not yet completed, "
+			printk(BIOS_SPEW, "drive detection not yet completed, "
 				"waiting...\n");
 		mdelay(10);
 		i++;
 	}
-	printk_spew("drive detection done after %i ms\n", i * 10);
+	printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
 	return 0;
 }
 
@@ -91,12 +91,12 @@
 	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
 	sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
 
-	printk_spew("sata_bar0=%x\n", sata_bar0);	/* 3030 */
-	printk_spew("sata_bar1=%x\n", sata_bar1);	/* 3070 */
-	printk_spew("sata_bar2=%x\n", sata_bar2);	/* 3040 */
-	printk_spew("sata_bar3=%x\n", sata_bar3);	/* 3080 */
-	printk_spew("sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk_spew("sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+	printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
 
 	/* Program the 2C to 0x43801002 */
 	dword = 0x43801002;
@@ -173,13 +173,13 @@
 
 	for (i = 0; i < 4; i++) {
 		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
-		printk_spew("SATA port %i status = %x\n", i, byte);
+		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 		byte &= 0xF;
 
 		if( byte == 0x1 ) {
 			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
 			/* Try to do something about it. */
-			printk_spew("SATA device detected but not talking. Trying lower speed.\n");
+			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
 
 			/* Read in Port-N Serial ATA Control Register */
 			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
@@ -200,7 +200,7 @@
 
 			/* Reread status */
 			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
-			printk_spew("SATA port %i status = %x\n", i, byte);
+			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 			byte &= 0xF;
 		}
 
@@ -209,13 +209,13 @@
 				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
 					break;
 			}
-			printk_debug("%s %s device is %sready after %i tries\n",
+			printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
 					(i / 2) ? "Secondary" : "Primary",
 					(i % 2 ) ? "Slave" : "Master",
 					(j == 10) ? "not " : "",
 					(j == 10) ? j : j + 1);
 		} else {
-			printk_debug("No %s %s SATA drive on Slot%i\n",
+			printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
 					(i / 2) ? "Secondary" : "Primary",
 					(i % 2 ) ? "Slave" : "Master", i);
 		}
@@ -240,7 +240,7 @@
 	/* word = pm_ioread(0x28); */
 	/* byte = pm_ioread(0x29); */
 	/* word |= byte<<8; */
-	/* printk_debug("AcpiGpe0Blk addr = %x\n", word); */
+	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
 	/* write32(word, 0x80000000); */
 }
 
Index: src/southbridge/amd/sb600/sb600_smbus.c
===================================================================
--- src/southbridge/amd/sb600/sb600_smbus.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600_smbus.c	(working copy)
@@ -188,7 +188,7 @@
 	tmp &= ~mask;
 	tmp |= val;
 
-	/* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
 	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
 	outl(tmp, AB_DATA);
 }
Index: src/southbridge/amd/sb600/sb600_usb.c
===================================================================
--- src/southbridge/amd/sb600/sb600_usb.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600_usb.c	(working copy)
@@ -94,7 +94,7 @@
 	/* pci_write_config32(dev, 0xf8, dword); */
 
 	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
-	printk_info("usb2_bar0=0x%x\n", usb2_bar0);
+	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
 
 	/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
 	dword = 0x00020F00;
Index: src/southbridge/amd/sb600/sb600_hda.c
===================================================================
--- src/southbridge/amd/sb600/sb600_hda.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600_hda.c	(working copy)
@@ -86,7 +86,7 @@
 	/* Codec Not found */
 	/* Put HDA back in reset (BAR + 0x8) [0] */
 	set_bits(base + 0x08, 1, 0);
-	printk_debug("No codec!\n");
+	printk(BIOS_DEBUG, "No codec!\n");
 	return 0;
 }
 
@@ -156,9 +156,9 @@
 	device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
 	struct southbridge_amd_sb600_config *cfg =
 	    (struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
-	printk_debug("Dev=%s\n", dev_path(azalia_dev));
-	printk_debug("Default viddid=%x\n", cfg->hda_viddid);
-	printk_debug("Reading viddid=%x\n", viddid);
+	printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev));
+	printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid);
+	printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid);
 	if (!cfg)
 		return 0;
 	if (viddid != cfg->hda_viddid)
@@ -232,15 +232,15 @@
 	dword = read32(base + 0x64);
 
 	/* 2 */
-	printk_debug("codec viddid: %08x\n", dword);
+	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
 	verb_size = find_verb(dword, &verb);
 
 	if (!verb_size) {
-		printk_debug("No verb!\n");
+		printk(BIOS_DEBUG, "No verb!\n");
 		return;
 	}
 
-	printk_debug("verb_size: %d\n", verb_size);
+	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
 	/* 3 */
 	for (i = 0; i < verb_size; i++) {
 		if (wait_for_ready(base) == -1)
@@ -251,7 +251,7 @@
 		if (wait_for_valid(base) == -1)
 			return;
 	}
-	printk_debug("verb loaded!\n");
+	printk(BIOS_DEBUG, "verb loaded!\n");
 }
 
 static void codecs_init(u32 base, u32 codec_mask)
@@ -302,11 +302,11 @@
 		return;
 
 	base = ((u32)res->base);
-	printk_debug("base = 0x%x\n", base);
+	printk(BIOS_DEBUG, "base = 0x%x\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
-		printk_debug("codec_mask = %02x\n", codec_mask);
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
 		codecs_init(base, codec_mask);
 	}
 }
Index: src/southbridge/amd/sb600/sb600_early_setup.c
===================================================================
--- src/southbridge/amd/sb600/sb600_early_setup.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600_early_setup.c	(working copy)
@@ -284,16 +284,16 @@
 	device_t dev;
 	u8 byte;
 
-	printk_info("sb600_devices_por_init()\n");
+	printk(BIOS_INFO, "sb600_devices_por_init()\n");
 	/* SMBus Device, BDF:0-20-0 */
-	printk_info("sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
+	printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
 
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\r\n");
 		/* NOT REACHED */
 	}
-	printk_info("SMBus controller enabled, sb revision is 0x%x\r\n",
+	printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n",
 		    get_sb600_revision());
 
 	/* sbPorAtStartOfTblCfg */
@@ -372,7 +372,7 @@
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
 	/* IDE Device, BDF:0-20-1 */
-	printk_info("sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
+	printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
 	/* Disable prefetch */
 	byte = pci_read_config8(dev, 0x63);
@@ -380,7 +380,7 @@
 	pci_write_config8(dev, 0x63, byte);
 
 	/* LPC Device, BDF:0-20-3 */
-	printk_info("sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
+	printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
 	/* DMA enable */
 	pci_write_config8(dev, 0x40, 0x04);
@@ -417,7 +417,7 @@
 
 	/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
 	 * TODO: I don't know what are their mean? */
-	printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
+	printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
 	/* I don't know why CIM tried to write into a read-only reg! */
 	/*pci_write_config8(dev, 0x0c, 0x20) */ ;
@@ -448,7 +448,7 @@
 	pci_write_config8(dev, 0x50, 0x01);
 
 	/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
-	printk_info("sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
+	printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
 
 	/*PHY Global Control, we are using A14.
@@ -479,7 +479,7 @@
 {
 	u8 byte;
 
-	printk_info("sb600_pmio_por_init()\n");
+	printk(BIOS_INFO, "sb600_pmio_por_init()\n");
 	/* K8KbRstEn, KB_RST# control for K8 system. */
 	byte = pmio_read(0x66);
 	byte |= 0x20;
@@ -676,7 +676,7 @@
 */
 static void sb600_early_setup(void)
 {
-	printk_info("sb600_early_setup()\n");
+	printk(BIOS_INFO, "sb600_early_setup()\n");
 	sb600_por_init();
 }
 
Index: src/southbridge/amd/sb600/sb600_lpc.c
===================================================================
--- src/southbridge/amd/sb600/sb600_lpc.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600_lpc.c	(working copy)
@@ -130,8 +130,7 @@
 						continue;
 					base = res->base;
 					end = resource_end(res);
-					printk_debug
-					    ("sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
 					     dev_path(child), base, end);
 					switch (base) {
 					case 0x60:	/*  KB */
Index: src/southbridge/amd/sb600/sb600_sm.c
===================================================================
--- src/southbridge/amd/sb600/sb600_sm.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600_sm.c	(working copy)
@@ -54,7 +54,7 @@
 	u32 on;
 	u32 nmi_option;
 
-	printk_info("sm_init().\n");
+	printk(BIOS_INFO, "sm_init().\n");
 
 	ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0);	/* some like mem resource, but does not have  enable bit */
 	/* Don't rename APIC ID */
@@ -98,7 +98,7 @@
 	}
 	byte |= 1 << 2;
 	pm_iowrite(0x74, byte);
-	printk_info("set power %s after power fail\n", on ? "on" : "off");
+	printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
 
 	/* sb600 rpr:2.3.3: */
 	byte = pm_ioread(0x9A);
@@ -154,10 +154,10 @@
 	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
 		byte &= ~(1 << 7);	/* set NMI */
-		printk_info("++++++++++set NMI+++++\n");
+		printk(BIOS_INFO, "++++++++++set NMI+++++\n");
 	} else {
 		byte |= (1 << 7);	/* Can not mask NMI from PCI-E and NMI_NOW */
-		printk_info("++++++++++no set NMI+++++\n");
+		printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
 	}
 	byte &= ~(1 << 7);
 	if (byte != byte_old) {
@@ -197,9 +197,9 @@
 	/* 3.12: Enabling AB and BIF Clock Gating */
 	abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
 	abcfg_reg(0x54, 0xFF << 16, 4 << 16);
-	printk_info("3.11, ABCFG:0x54\n");
+	printk(BIOS_INFO, "3.11, ABCFG:0x54\n");
 	abcfg_reg(0x54, 1 << 24, 1 << 24);
-	printk_info("3.12, ABCFG:0x54\n");
+	printk(BIOS_INFO, "3.12, ABCFG:0x54\n");
 	abcfg_reg(0x98, 0x0000FF00, 0x00004700);
 
 	/* 3.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
@@ -211,7 +211,7 @@
 
 	abcfg_reg(0x10098, 0xFFFFFFFF, 0x4000);
 	abcfg_reg(0x04, 0xFFFFFFFF, 0x6);
-	printk_info("sm_init() end\n");
+	printk(BIOS_INFO, "sm_init() end\n");
 
 	/* Enable NbSb virtual channel */
 	axcfg_reg(0x114, 0x3f << 1, 0 << 1);
Index: src/southbridge/amd/sb600/sb600.c
===================================================================
--- src/southbridge/amd/sb600/sb600.c	(revision 5263)
+++ src/southbridge/amd/sb600/sb600.c	(working copy)
@@ -118,7 +118,7 @@
 
 	u32 devfn;
 
-	printk_debug("sb600_enable()\n");
+	printk(BIOS_DEBUG, "sb600_enable()\n");
 
 /*
 *	0:12.0  SATA	bit 8 of sm_dev 0xac : 1 - enable, default         + 32 * 3
@@ -220,7 +220,7 @@
 		index += 32 * 4;
 		break;
 	default:
-		printk_debug("unknown dev: %s deviceid=%4x\n", dev_path(dev),
+		printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev),
 			     deviceid);
 	}
 }
Index: src/southbridge/amd/sb700/sb700_sata.c
===================================================================
--- src/southbridge/amd/sb700/sb700_sata.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700_sata.c	(working copy)
@@ -34,22 +34,22 @@
 	while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
 		(byte != (0xA0 + 0x10 * (portnum % 2))) ||
 		((byte2 & 0x88) != 0)) {
-		printk_spew("0x6=%x, 0x7=%x\n", byte, byte2);
+		printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
 		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
 			/* This will happen at the first iteration of this loop
 			 * if the first SATA port is unpopulated and the
 			 * second SATA port is poulated.
 			 */
-			printk_debug("drive no longer selected after %i ms, "
+			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
 				"retrying init\n", i * 10);
 			return 1;
 		} else
-			printk_spew("drive detection not yet completed, "
+			printk(BIOS_SPEW, "drive detection not yet completed, "
 				"waiting...\n");
 		mdelay(10);
 		i++;
 	}
-	printk_spew("drive detection done after %i ms\n", i * 10);
+	printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
 	return 0;
 }
 
@@ -96,12 +96,12 @@
 	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
 	sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
 
-	printk_spew("sata_bar0=%x\n", sata_bar0);	/* 3030 */
-	printk_spew("sata_bar1=%x\n", sata_bar1);	/* 3070 */
-	printk_spew("sata_bar2=%x\n", sata_bar2);	/* 3040 */
-	printk_spew("sata_bar3=%x\n", sata_bar3);	/* 3080 */
-	printk_spew("sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk_spew("sata_bar5=%p\n", sata_bar5);	/* e0309000 */
+	printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5);	/* e0309000 */
 
 	/* disable combined mode */
 	byte = pci_read_config8(sm_dev, 0xAD);
@@ -199,12 +199,12 @@
 
 	for (i = 0; i < 4; i++) {
 		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
-		printk_spew("SATA port %i status = %x\n", i, byte);
+		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 		byte &= 0xF;
 		if( byte == 0x1 ) {
 			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
 			/* Try to do something about it. */
-			printk_spew("SATA device detected but not talking. Trying lower speed.\n");
+			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
 
 			/* Read in Port-N Serial ATA Control Register */
 			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
@@ -225,7 +225,7 @@
 
 			/* Reread status */
 			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
-			printk_spew("SATA port %i status = %x\n", i, byte);
+			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 			byte &= 0xF;
 		}
 
@@ -234,13 +234,13 @@
 				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
 					break;
 			}
-			printk_debug("%s %s device is %sready after %i tries\n",
+			printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
 					(i / 2) ? "Secondary" : "Primary",
 					(i % 2 ) ? "Slave" : "Master",
 					(j == 10) ? "not " : "",
 					(j == 10) ? j : j + 1);
 		} else {
-			printk_debug("No %s %s SATA drive on Slot%i\n",
+			printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
 					(i / 2) ? "Secondary" : "Primary",
 					(i % 2 ) ? "Slave" : "Master", i);
 		}
@@ -267,7 +267,7 @@
 	/* word = pm_ioread(0x28); */
 	/* byte = pm_ioread(0x29); */
 	/* word |= byte<<8; */
-	/* printk_debug("AcpiGpe0Blk addr = %x\n", word); */
+	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
 	/* write32(word, 0x80000000); */
 }
 
Index: src/southbridge/amd/sb700/sb700_smbus.c
===================================================================
--- src/southbridge/amd/sb700/sb700_smbus.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700_smbus.c	(working copy)
@@ -196,7 +196,7 @@
 	tmp &= ~mask;
 	tmp |= val;
 
-	/* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
 	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
 	outl(tmp, AB_DATA);
 	reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
Index: src/southbridge/amd/sb700/sb700_usb.c
===================================================================
--- src/southbridge/amd/sb700/sb700_usb.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700_usb.c	(working copy)
@@ -82,7 +82,7 @@
 	/* pci_write_config32(dev, 0xf8, dword); */
 
 	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
-	printk_info("usb2_bar0=0x%x\n", usb2_bar0);
+	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
 
 	/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
 	dword = 0x00020F00;
@@ -163,7 +163,7 @@
 		dword |= 1 << 8;
 		dword &= ~(1 << 27); /* 6.23 */
 	}
-	printk_debug("rpr 6.23, final dword=%x\n", dword);
+	printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword);
 #endif
 }
 
Index: src/southbridge/amd/sb700/sb700_hda.c
===================================================================
--- src/southbridge/amd/sb700/sb700_hda.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700_hda.c	(working copy)
@@ -86,7 +86,7 @@
 	/* Codec Not found */
 	/* Put HDA back in reset (BAR + 0x8) [0] */
 	set_bits(base + 0x08, 1, 0);
-	printk_debug("No codec!\n");
+	printk(BIOS_DEBUG, "No codec!\n");
 	return 0;
 }
 
@@ -150,7 +150,7 @@
 	dword = read32(base + 0x64);
 
 	/* 2 */
-	printk_debug("%x(th) codec viddid: %08x\n", addr, dword);
+	printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
 }
 
 static void codecs_init(u32 base, u32 codec_mask)
@@ -203,11 +203,11 @@
 		return;
 
 	base = (u32)res->base;
-	printk_debug("base = 0x%x\n", base);
+	printk(BIOS_DEBUG, "base = 0x%x\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
-		printk_debug("codec_mask = %02x\n", codec_mask);
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
 		codecs_init(base, codec_mask);
 	}
 }
Index: src/southbridge/amd/sb700/sb700_early_setup.c
===================================================================
--- src/southbridge/amd/sb700/sb700_early_setup.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700_early_setup.c	(working copy)
@@ -300,16 +300,16 @@
 	device_t dev;
 	u8 byte;
 
-	printk_info("sb700_devices_por_init()\n");
+	printk(BIOS_INFO, "sb700_devices_por_init()\n");
 	/* SMBus Device, BDF:0-20-0 */
-	printk_info("sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n");
+	printk(BIOS_INFO, "sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
 
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\r\n");
 		/* NOT REACHED */
 	}
-	printk_info("SMBus controller enabled, sb revision is A%x\r\n",
+	printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\r\n",
 		    set_sb700_revision());
 
 	/* sbPorAtStartOfTblCfg */
@@ -378,7 +378,7 @@
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
 	/* IDE Device, BDF:0-20-1 */
-	printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
+	printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
 	/* Disable prefetch */
 	byte = pci_read_config8(dev, 0x63);
@@ -386,7 +386,7 @@
 	pci_write_config8(dev, 0x63, byte);
 
 	/* LPC Device, BDF:0-20-3 */
-	printk_info("sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
+	printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
 	/* DMA enable */
 	pci_write_config8(dev, 0x40, 0x04);
@@ -423,7 +423,7 @@
 
 	/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
 	 */
-	printk_info("sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
+	printk(BIOS_INFO, "sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
 
 	/* Arbiter enable. */
@@ -440,7 +440,7 @@
 	pci_write_config8(dev, 0x50, 0x01);
 
 	/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
-	printk_info("sb700_devices_por_init(): SATA Device, BDF:0-18-0\n");
+	printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
 
 	/*PHY Global Control*/
@@ -457,7 +457,7 @@
 {
 	u8 byte;
 
-	printk_info("sb700_pmio_por_init()\n");
+	printk(BIOS_INFO, "sb700_pmio_por_init()\n");
 	/* K8KbRstEn, KB_RST# control for K8 system. */
 	byte = pmio_read(0x66);
 	byte |= 0x20;
@@ -602,7 +602,7 @@
 */
 static void sb700_early_setup(void)
 {
-	printk_info("sb700_early_setup()\n");
+	printk(BIOS_INFO, "sb700_early_setup()\n");
 	sb700_por_init();
 }
 
Index: src/southbridge/amd/sb700/sb700_lpc.c
===================================================================
--- src/southbridge/amd/sb700/sb700_lpc.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700_lpc.c	(working copy)
@@ -143,8 +143,7 @@
 						continue;
 					base = res->base;
 					end = resource_end(res);
-					printk_debug
-					    ("sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
 					     dev_path(child), base, end);
 					switch (base) {
 					case 0x60:	/*  KB */
Index: src/southbridge/amd/sb700/sb700_sm.c
===================================================================
--- src/southbridge/amd/sb700/sb700_sm.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700_sm.c	(working copy)
@@ -54,7 +54,7 @@
 	u32 on;
 	u32 nmi_option;
 
-	printk_info("sm_init().\n");
+	printk(BIOS_INFO, "sm_init().\n");
 
 	ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0);	/* some like mem resource, but does not have  enable bit */
 	/* Don't rename APIC ID */
@@ -118,7 +118,7 @@
 	}
 	byte |= 1 << 2;
 	pm_iowrite(0x74, byte);
-	printk_info("set power %s after power fail\n", on ? "on" : "off");
+	printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
 
 	byte = pm_ioread(0x68);
 	byte &= ~(1 << 1);
@@ -152,10 +152,10 @@
 	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
 		byte &= ~(1 << 7);	/* set NMI */
-		printk_info("++++++++++set NMI+++++\n");
+		printk(BIOS_INFO, "++++++++++set NMI+++++\n");
 	} else {
 		byte |= (1 << 7);	/* Can not mask NMI from PCI-E and NMI_NOW */
-		printk_info("++++++++++no set NMI+++++\n");
+		printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
 	}
 	byte &= ~(1 << 7);
 	if (byte != byte_old) {
@@ -217,7 +217,7 @@
 	byte &= ~(1 << 1);
 	pm_iowrite(0x59, byte);
 
-	printk_info("sm_init() end\n");
+	printk(BIOS_INFO, "sm_init() end\n");
 
 	/* Enable NbSb virtual channel */
 	axcfg_reg(0x114, 0x3f << 1, 0 << 1);
Index: src/southbridge/amd/sb700/sb700.c
===================================================================
--- src/southbridge/amd/sb700/sb700.c	(revision 5263)
+++ src/southbridge/amd/sb700/sb700.c	(working copy)
@@ -118,7 +118,7 @@
 
 	u32 devfn;
 
-	printk_debug("sb700_enable()\n");
+	printk(BIOS_DEBUG, "sb700_enable()\n");
 
 /*
 *	0:11.0  SATA	bit 8 of sm_dev 0xac : 1 - enable, default         + 32 * 3
@@ -221,7 +221,7 @@
 		index = 4;
 		break;
 	default:
-		printk_debug("unknown dev: %s deviceid=%4x\n", dev_path(dev),
+		printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev),
 			     deviceid);
 	}
 }
Index: src/southbridge/amd/amd8111/amd8111_nic.c
===================================================================
--- src/southbridge/amd/amd8111/amd8111_nic.c	(revision 5263)
+++ src/southbridge/amd/amd8111/amd8111_nic.c	(working copy)
@@ -52,7 +52,7 @@
 	mmio = resource->base;
 
 	/* Hard Reset PHY */
-	printk_debug("Reseting PHY... ");
+	printk(BIOS_DEBUG, "Reseting PHY... ");
 	if (conf->phy_lowreset) {
 		write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
 	} else {
@@ -60,7 +60,7 @@
 	}
 	mdelay(15);
 	write32((mmio + CMD3), RESET_PHY);
-	printk_debug("Done\n");
+	printk(BIOS_DEBUG, "Done\n");
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/amd/amd8111/amd8111_usb2.c
===================================================================
--- src/southbridge/amd/amd8111/amd8111_usb2.c	(revision 5263)
+++ src/southbridge/amd/amd8111/amd8111_usb2.c	(working copy)
@@ -26,7 +26,7 @@
 	// Due to buggy USB2 we force it to disable. 
 	dev->enabled = 0;
 	amd8111_enable(dev);
-	printk_debug("USB2 disabled.\n");
+	printk(BIOS_DEBUG, "USB2 disabled.\n");
 }
 
 static struct device_operations usb2_ops  = {
Index: src/southbridge/amd/amd8111/amd8111_acpi.c
===================================================================
--- src/southbridge/amd/amd8111/amd8111_acpi.c	(revision 5263)
+++ src/southbridge/amd/amd8111/amd8111_acpi.c	(working copy)
@@ -79,7 +79,7 @@
 
 #if 0
 	uint16_t word;
-	printk_debug("ACPI: disabling NMI watchdog.. ");
+	printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
 	byte = pci_read_config8(dev, 0x49);
 	pci_write_config8(dev, 0x49, byte | (1<<2));
 
@@ -91,13 +91,13 @@
 	byte = pci_read_config8(dev, 0x48);
 	pci_write_config8(dev, 0x48, byte | (1<<3));
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 
 
-	printk_debug("ACPI: Routing IRQ 12 to PS2 port.. ");
+	printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. ");
 	word = pci_read_config16(dev, 0x46);
 	pci_write_config16(dev, 0x46, word | (1<<9));
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 
 	/* To enable the register 0xcf9 in the IO space
@@ -119,7 +119,7 @@
 		byte |= 0x40;
 	}
 	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
-	printk_info("set power %s after power fail\n", on?"on":"off");
+	printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
 
 	/* switch serial irq logic from quiet mode to continuous
 	 * mode for Winbond W83627HF Rev. 17
@@ -135,13 +135,13 @@
 		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 		dword = inl(pm10_bar + 0x10);
 		on = 8-on;
-		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
+		printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 				(on*12)+(on>>1),(on&1)*5);
 	}
 
 #if CONFIG_GENERATE_ACPI_TABLES == 1
 	pm_base = pci_read_config16(dev, 0x58) & 0xff00;
-	printk_debug("pm_base: 0x%04x\n",pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
 #endif
 
 }
Index: src/southbridge/amd/amd8111/amd8111_lpc.c
===================================================================
--- src/southbridge/amd/amd8111/amd8111_lpc.c	(revision 5263)
+++ src/southbridge/amd/amd8111/amd8111_lpc.c	(working copy)
@@ -22,7 +22,7 @@
 	
 	pci_write_config32(dev,0xa0, 0xfed00001);
 	hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
-	printk_debug("enabling HPET @0x%lx\n", hpet_address);
+	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
 	
 }
 
Index: src/southbridge/amd/amd8111/amd8111_ide.c
===================================================================
--- src/southbridge/amd/amd8111/amd8111_ide.c	(revision 5263)
+++ src/southbridge/amd/amd8111/amd8111_ide.c	(working copy)
@@ -19,12 +19,12 @@
 	if (conf->ide1_enable) {
 		/* Enable secondary ide interface */
 		word |= (1<<0);
-		printk_debug("IDE1 ");
+		printk(BIOS_DEBUG, "IDE1 ");
 	}
 	if (conf->ide0_enable) {
 		/* Enable primary ide interface */
 		word |= (1<<1);
-		printk_debug("IDE0 ");
+		printk(BIOS_DEBUG, "IDE0 ");
 	}
 
 	word |= (1<<12);
Index: src/southbridge/amd/amd8131/amd8131_bridge.c
===================================================================
--- src/southbridge/amd/amd8131/amd8131_bridge.c	(revision 5263)
+++ src/southbridge/amd/amd8131/amd8131_bridge.c	(working copy)
@@ -83,7 +83,7 @@
 	}
 
 
-	printk_debug("%s AMD8131 PCI-X tuning\n", dev_path(dev));
+	printk(BIOS_DEBUG, "%s AMD8131 PCI-X tuning\n", dev_path(dev));
 	status = pci_read_config32(dev, cap + PCI_X_STATUS);
 	orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
 
@@ -170,7 +170,7 @@
 		}
 	}
 #if 0
-	printk_debug("%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n",
+	printk(BIOS_DEBUG, "%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n",
 		dev_path(dev), max_read, max_tran, sibs, sib_funcs, sib_funcs);
 #endif
 	if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
@@ -214,7 +214,7 @@
 	info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
 
 	/* Print the PCI-X bus speed */
-	printk_debug("PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus));
+	printk(BIOS_DEBUG, "PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus));
 
 
 	/* Examine the bus and find out how loaded it is */
@@ -260,7 +260,7 @@
 	 * implement relaxed ordering.  Errata #58
 	 */
 	for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
-		printk_spew("%s disabling relaxed ordering\n",
+		printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
 			bus_path(pbus));
 		pbus->disable_relaxed_ordering = 1;
 	}
Index: src/southbridge/ricoh/rl5c476/rl5c476.c
===================================================================
--- src/southbridge/ricoh/rl5c476/rl5c476.c	(revision 5263)
+++ src/southbridge/ricoh/rl5c476/rl5c476.c	(working copy)
@@ -38,9 +38,9 @@
 	unsigned char *base;
 
 	/* cardbus controller function 1 for CF Socket */
-	printk_debug("Ricoh RL5c476: Initializing.\n");
+	printk(BIOS_DEBUG, "Ricoh RL5c476: Initializing.\n");
 
-	printk_debug("CF Base = %0x\n",cf_base);
+	printk(BIOS_DEBUG, "CF Base = %0x\n",cf_base);
 
 	/* misc control register */
 	pci_write_config16(dev,0x82,0x00a0);
@@ -48,7 +48,7 @@
 	/* set up second slot as compact flash port if asked to do so */
 
 	if (!enable_cf_boot) {
-		printk_debug("CF boot not enabled.\n");
+		printk(BIOS_DEBUG, "CF boot not enabled.\n");
 		return;
 	}
 	
@@ -152,7 +152,7 @@
 	 */
 	unsigned char *cptr;
 	cptr = (unsigned char *)(cf_base + 0x200);
-	printk_debug("CF Config = %x\n",*cptr);
+	printk(BIOS_DEBUG, "CF Config = %x\n",*cptr);
 
 	/* Set CF to decode 16 IO bytes on any 16 byte boundary - 
 	 * rely on the io windows of the bridge set up above to 
@@ -184,12 +184,12 @@
 void rl5c476_set_resources(device_t dev)
 {
 	struct resource *resource;
-	printk_debug("%s In set resources \n",dev_path(dev));
+	printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
 	if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
 		resource = find_resource(dev,1);
 		if( !(resource->flags & IORESOURCE_STORED) ){
 			resource->flags |= IORESOURCE_STORED ;
-			printk_debug("%s 1 ==> %x\n", dev_path(dev), resource->base); 
+			printk(BIOS_DEBUG, "%s 1 ==> %x\n", dev_path(dev), resource->base); 
 			cf_base = resource->base;
 		}
 	}
Index: src/southbridge/broadcom/bcm21000/bcm21000_pcie.c
===================================================================
--- src/southbridge/broadcom/bcm21000/bcm21000_pcie.c	(revision 5263)
+++ src/southbridge/broadcom/bcm21000/bcm21000_pcie.c	(working copy)
@@ -33,7 +33,7 @@
 	uint32_t dword;
 	uint32_t msicap;
 
-	printk_debug("PCIE enable.... dev= %s\n",dev_path(dev));
+	printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev));
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
Index: src/southbridge/broadcom/bcm5785/bcm5785_sata.c
===================================================================
--- src/southbridge/broadcom/bcm5785/bcm5785_sata.c	(revision 5263)
+++ src/southbridge/broadcom/bcm5785/bcm5785_sata.c	(working copy)
@@ -49,17 +49,17 @@
 
 		//init PHY
 
-		printk_debug("init PHY...\n");
+		printk(BIOS_DEBUG, "init PHY...\n");
 		for(i=0; i<4; i++) {
 			mmio = base + 0x100 * i; 
 			byte = read8(mmio + 0x40);
-			printk_debug("port %d PHY status = %02x\r\n", i, byte);
+			printk(BIOS_DEBUG, "port %d PHY status = %02x\r\n", i, byte);
 			if(byte & 0x4) {// bit 2 is set
 				byte = read8(mmio+0x48);
 				write8(mmio + 0x48, byte | 1);
 				write8(mmio + 0x48, byte & (~1));
 	                        byte = read8(mmio + 0x40);
-	                        printk_debug("after reset port %d PHY status = %02x\r\n", i, byte);
+	                        printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\r\n", i, byte);
 			}
 		}
 		
Index: src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
===================================================================
--- src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	(revision 5263)
+++ src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	(working copy)
@@ -86,7 +86,7 @@
 					if(!(res->flags & IORESOURCE_IO)) continue;
 		        	        base = res->base;
                 			end = resource_end(res);
-					printk_debug("bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
+					printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
 					switch(base) {
 					case 0x60: //KBC
 					case 0x64:
Index: src/southbridge/nvidia/ck804/ck804_sata.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_sata.c	(revision 5263)
+++ src/southbridge/nvidia/ck804/ck804_sata.c	(working copy)
@@ -26,7 +26,7 @@
 
 	base = (uint32_t *) pci_read_config32(dev, 0x24);
 
-	printk_debug("base = %08lx\n", base);
+	printk(BIOS_DEBUG, "base = %08lx\n", base);
 
 	if (reset) {
 		*(base + 4) = 0xffffffff;
@@ -51,7 +51,7 @@
 		return;
 
 	dword = *(base + 0);
-	printk_debug("*(base+0)=%08x\r\n", dword);
+	printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword);
 	if (dword == 0x113) {
 		loop = 200000;	// 2
 		do {
@@ -60,11 +60,11 @@
 				break;
 			udelay(10);
 		} while (--loop > 0);
-		printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword);
+		printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword);
 	}
 
 	dword = *(base + 0x40);
-	printk_debug("*(base+0x40)=%08x\r\n", dword);
+	printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword);
 	if (dword == 0x113) {
 		loop = 200000;	//2
 		do {
@@ -73,7 +73,7 @@
 				break;
 			udelay(10);
 		} while (--loop > 0);
-		printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
+		printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
 	}
 }
 #endif
@@ -91,12 +91,12 @@
 	if (conf->sata1_enable) {
 		/* Enable secondary SATA interface. */
 		dword |= (1 << 0);
-		printk_debug("SATA S \t");
+		printk(BIOS_DEBUG, "SATA S \t");
 	}
 	if (conf->sata0_enable) {
 		/* Enable primary SATA interface. */
 		dword |= (1 << 1);
-		printk_debug("SATA P \n");
+		printk(BIOS_DEBUG, "SATA P \n");
 	}
 #if 0
 	/* Write back */
Index: src/southbridge/nvidia/ck804/ck804_ide.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_ide.c	(revision 5263)
+++ src/southbridge/nvidia/ck804/ck804_ide.c	(working copy)
@@ -25,12 +25,12 @@
 	if (conf->ide1_enable) {
 		/* Enable secondary IDE interface. */
 		word |= (1 << 0);
-		printk_debug("IDE1 \t");
+		printk(BIOS_DEBUG, "IDE1 \t");
 	}
 	if (conf->ide0_enable) {
 		/* Enable primary IDE interface. */
 		word |= (1 << 1);
-		printk_debug("IDE0\n");
+		printk(BIOS_DEBUG, "IDE0\n");
 	}
 
 	word |= (1 << 12);
Index: src/southbridge/nvidia/ck804/ck804_pci.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_pci.c	(revision 5263)
+++ src/southbridge/nvidia/ck804/ck804_pci.c	(working copy)
@@ -53,13 +53,13 @@
 
 	if (!pref || pref->base > mem->base) {
 		dword = mem->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
+		printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
 	} else {
 		dword = pref->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
+		printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
 	}
 
-	printk_debug("[0x50] <-- 0x%08x\n", dword);
+	printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
 	pci_write_config32(dev, 0x50, dword);	/* TOM */
 }
 
Index: src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_lpc.c	(revision 5263)
+++ src/southbridge/nvidia/ck804/ck804_lpc.c	(working copy)
@@ -95,7 +95,7 @@
 
 	pci_write_config32(dev, 0x44, 0xfed00001);
 	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
-	printk_debug("Enabling HPET @0x%lx\n", hpet_address);
+	printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address);
 }
 
 unsigned pm_base=0;
@@ -108,7 +108,7 @@
 	lpc_common_init(dev);
 
 	pm_base = pci_read_config32(dev, 0x60) & 0xff00;
-	printk_info("%s: pm_base = %x \n", __func__, pm_base);
+	printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
 
 #if CK804_CHIP_REV==1
 	if (dev->bus->secondary != 1)
@@ -129,7 +129,7 @@
 	if (!on)
 		byte |= 0x40;
 	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
-	printk_info("set power %s after power fail\n", on ? "on" : "off");
+	printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
 
 	/* Throttle the CPU speed down for testing. */
 	on = SLOW_CPU_OFF;
@@ -141,7 +141,7 @@
 		outl(((on << 1) + 0x10), (pm10_bar + 0x10));
 		dword = inl(pm10_bar + 0x10);
 		on = 8 - on;
-		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
+		printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 			     (on * 12) + (on >> 1), (on & 1) * 5);
 	}
 #if 0
@@ -250,7 +250,7 @@
 						continue;
 					base = res->base;
 					end = resource_end(res);
-					printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
+					printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
 					switch (base) {
 					case 0x3f8:	// COM1
 						reg |= (1 << 0);
Index: src/southbridge/nvidia/ck804/ck804_fadt.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_fadt.c	(revision 5263)
+++ src/southbridge/nvidia/ck804/ck804_fadt.c	(working copy)
@@ -13,7 +13,7 @@
 {
 	acpi_header_t *header = &(fadt->header);
 
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/southbridge/nvidia/mcp55/mcp55_sata.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_sata.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55_sata.c	(working copy)
@@ -43,16 +43,16 @@
 		if (conf->sata1_enable) {
 			/* Enable secondary SATA interface */
 			dword |= (1<<0);
-			printk_debug("SATA S \t");
+			printk(BIOS_DEBUG, "SATA S \t");
 		}
 		if (conf->sata0_enable) {
 			/* Enable primary SATA interface */
 			dword |= (1<<1);
-			printk_debug("SATA P \n");
+			printk(BIOS_DEBUG, "SATA P \n");
 		}
 	} else {
 		dword |= (1<<1) | (1<<0);
-		printk_debug("SATA P and S \n");
+		printk(BIOS_DEBUG, "SATA P and S \n");
 	}
 
 
Index: src/southbridge/nvidia/mcp55/mcp55_ide.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_ide.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55_ide.c	(working copy)
@@ -43,12 +43,12 @@
 	if (conf->ide1_enable) {
 		/* Enable secondary ide interface */
 		word |= (1<<0);
-		printk_debug("IDE1 \t");
+		printk(BIOS_DEBUG, "IDE1 \t");
 	}
 	if (conf->ide0_enable) {
 		/* Enable primary ide interface */
 		word |= (1<<1);
-		printk_debug("IDE0\n");
+		printk(BIOS_DEBUG, "IDE0\n");
 	}
 
 	word |= (1<<12);
Index: src/southbridge/nvidia/mcp55/mcp55_nic.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_nic.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55_nic.c	(working copy)
@@ -83,13 +83,13 @@
 		val = phy_read(base, phyaddr, 2);
 		if (val < 0 || val == 0xffff) continue;
 		id |= ((val & 0xffff)<<16);
-		printk_debug("MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
+		printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
 //		if((id == 0xe0180000) || (id==0x0032cc00))
 			break;
 	}
 
 	if(i>32) {
-		printk_debug("MCP55 MAC PHY not found\n");
+		printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n");
 	}
 }
 
Index: src/southbridge/nvidia/mcp55/mcp55_aza.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_aza.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55_aza.c	(working copy)
@@ -80,7 +80,7 @@
 	/* 6 */
 	if(!dword) {
 		set_bits(base + 0x08, 1, 0);
-		printk_debug("No codec!\n");
+		printk(BIOS_DEBUG, "No codec!\n");
 		return 0;
 	}
 	return dword;
@@ -186,15 +186,15 @@
 	dword = read32(base + 0x64);
 
 	/* 2 */
-	printk_debug("codec viddid: %08x\n", dword);
+	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
 	verb_size = find_verb(dword, &verb);
 
 	if(!verb_size) {
-		printk_debug("No verb!\n");
+		printk(BIOS_DEBUG, "No verb!\n");
 		return;
 	}
 
-	printk_debug("verb_size: %d\n", verb_size);
+	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
 	/* 3 */
 	for(i=0; i<verb_size; i++) {
 		do {
@@ -207,7 +207,7 @@
 			dword = read32(base + 0x68);
 		} while ((dword & 3) != 2);
 	}
-	printk_debug("verb loaded!\n");
+	printk(BIOS_DEBUG, "verb loaded!\n");
 }
 
 static void codecs_init(uint8_t *base, uint32_t codec_mask)
@@ -230,12 +230,12 @@
 		return;
 
 	base =(uint8_t *) res->base;
-	printk_debug("base = %08x\n", base);
+	printk(BIOS_DEBUG, "base = %08x\n", base);
 
 	codec_mask = codec_detect(base);
 
 	if(codec_mask) {
-		printk_debug("codec_mask = %02x\n", codec_mask);
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
 		codecs_init(base, codec_mask);
 	}
 }
Index: src/southbridge/nvidia/mcp55/mcp55_pci.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_pci.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55_pci.c	(working copy)
@@ -75,13 +75,13 @@
 
 	if (!pref || pref->base > mem->base) {
 		dword = mem->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
+		printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
 	} else {
 		dword = pref->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
+		printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
 	}
 
-	printk_debug("[0x50] <-- 0x%08x\n", dword);
+	printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
 	pci_write_config32(dev, 0x50, dword);	/* TOM */
 }
 
Index: src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_lpc.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55_lpc.c	(working copy)
@@ -80,7 +80,7 @@
 
 	pci_write_config32(dev,0x44, 0xfed00001);
 	hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
-	printk_debug("enabling HPET @0x%x\n", hpet_address);
+	printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address);
 }
 
 static void lpc_init(device_t dev)
@@ -108,7 +108,7 @@
 		byte |= 0x40;
 	}
 	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
-	printk_info("set power %s after power fail\n", on?"on":"off");
+	printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
 #endif
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
@@ -120,7 +120,7 @@
 		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 		dword = inl(pm10_bar + 0x10);
 		on = 8-on;
-		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
+		printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 			     (on*12)+(on>>1),(on&1)*5);
 	}
 
@@ -224,7 +224,7 @@
 					if(!(res->flags & IORESOURCE_IO)) continue;
 					base = res->base;
 					end = resource_end(res);
-					printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
+					printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 					switch(base) {
 					case 0x3f8: // COM1
 						reg |= (1<<0);	break;
Index: src/southbridge/nvidia/mcp55/mcp55_fadt.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_fadt.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55_fadt.c	(working copy)
@@ -49,7 +49,7 @@
 	memcpy(header->asl_compiler_id, "CORE", 4);
 	header->asl_compiler_revision = 42;
 
-	printk_info("ACPI: pm_base: %u...\n", pm_base);
+	printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base);
 
 	fadt->firmware_ctrl = facs;
 	fadt->dsdt = dsdt;
Index: src/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55.c	(revision 5263)
+++ src/southbridge/nvidia/mcp55/mcp55.c	(working copy)
@@ -218,7 +218,7 @@
 //		reg |= (1<<0);
 		reg &= ~(0x3f<<4);
 		if (reg != reg_old) {
-			printk_debug("mcp55.c pcie enabled\n");
+			printk(BIOS_DEBUG, "mcp55.c pcie enabled\n");
 			pci_write_config32(sm_dev, 0xe4, reg);
 		}
 #endif
Index: src/southbridge/intel/i82870/p64h2_ioapic.c
===================================================================
--- src/southbridge/intel/i82870/p64h2_ioapic.c	(revision 5263)
+++ src/southbridge/intel/i82870/p64h2_ioapic.c	(working copy)
@@ -62,7 +62,7 @@
     pIndexRegister  = (volatile uint32_t*) memoryBase;
     pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
 
-    printk_debug("IOAPIC %d at %02x:%02x.%01x  MBAR = %x DataAddr = %x\n",
+    printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %x DataAddr = %x\n",
                  apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), 
                  PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
 
Index: src/southbridge/intel/esb6300/esb6300_ide.c
===================================================================
--- src/southbridge/intel/esb6300/esb6300_ide.c	(revision 5263)
+++ src/southbridge/intel/esb6300/esb6300_ide.c	(working copy)
@@ -26,7 +26,7 @@
 	word |= (1 << 15);
 	pci_write_config16(dev, 0x42, word);
 #endif
-	printk_debug("IDE Enabled\n");
+	printk(BIOS_DEBUG, "IDE Enabled\n");
 }
 
 static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/esb6300/esb6300_ehci.c
===================================================================
--- src/southbridge/intel/esb6300/esb6300_ehci.c	(revision 5263)
+++ src/southbridge/intel/esb6300/esb6300_ehci.c	(working copy)
@@ -9,12 +9,12 @@
 {
 	uint32_t cmd;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, 
 		cmd | PCI_COMMAND_MASTER);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/esb6300/esb6300_lpc.c
===================================================================
--- src/southbridge/intel/esb6300/esb6300_lpc.c	(revision 5263)
+++ src/southbridge/intel/esb6300/esb6300_lpc.c	(working copy)
@@ -288,7 +288,7 @@
 		byte |= 1;
 	}
 	pci_write_config8(dev, 0xa4, byte);
-	printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+	printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
 
 	/* Set up the PIRQ */
 	esb6300_pirq_init(dev);
Index: src/southbridge/intel/esb6300/esb6300_uhci.c
===================================================================
--- src/southbridge/intel/esb6300/esb6300_uhci.c	(revision 5263)
+++ src/southbridge/intel/esb6300/esb6300_uhci.c	(working copy)
@@ -10,13 +10,13 @@
 	uint32_t cmd;
 
 #if 1
-	printk_debug("UHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, 
 		cmd | PCI_COMMAND_MASTER);
 
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 
 }
Index: src/southbridge/intel/esb6300/esb6300_sata.c
===================================================================
--- src/southbridge/intel/esb6300/esb6300_sata.c	(revision 5263)
+++ src/southbridge/intel/esb6300/esb6300_sata.c	(working copy)
@@ -13,7 +13,7 @@
 
 	/* Enable SATA devices */
 
-	printk_debug("SATA init\n");
+	printk(BIOS_DEBUG, "SATA init\n");
         /* SATA configuration */
         pci_write_config8(dev, 0x04, 0x07);
         pci_write_config8(dev, 0x09, 0x8f);
@@ -41,7 +41,7 @@
         pci_write_config16(dev, 0xa0, 0x0040);
         pci_write_config32(dev, 0xa4, 0x00220043);
                                                                                 
-	printk_debug("SATA Enabled\n");
+	printk(BIOS_DEBUG, "SATA Enabled\n");
 }
 
 static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/pxhd/pxhd_bridge.c
===================================================================
--- src/southbridge/intel/pxhd/pxhd_bridge.c	(revision 5263)
+++ src/southbridge/intel/pxhd/pxhd_bridge.c	(working copy)
@@ -22,7 +22,7 @@
 	}
 	bridge = dev_find_slot(dev->bus->secondary, dev->path.pci.devfn & ~1);
 	if (!bridge) {
-		printk_err("Cannot find bridge for ioapic: %s\n",
+		printk(BIOS_ERR, "Cannot find bridge for ioapic: %s\n",
 			   dev_path(dev));
 		return;
 	}
@@ -48,7 +48,7 @@
 	if(bus_100Mhz) {
 		uint16_t word;
 
-		printk_debug("setting pxhd bus to 100 Mhz\n");
+		printk(BIOS_DEBUG, "setting pxhd bus to 100 Mhz\n");
 		/* set to pcix 100 mhz */
 		word = pci_read_config16(dev, 0x40);
 		word &= ~(3 << 14);
Index: src/southbridge/intel/i82801ax/i82801ax_watchdog.c
===================================================================
--- src/southbridge/intel/i82801ax/i82801ax_watchdog.c	(revision 5263)
+++ src/southbridge/intel/i82801ax/i82801ax_watchdog.c	(working copy)
@@ -50,5 +50,5 @@
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
 
-	printk_debug("ICH Watchdog disabled\r\n");
+	printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n");
 }
Index: src/southbridge/intel/i82801ax/i82801ax_ide.c
===================================================================
--- src/southbridge/intel/i82801ax/i82801ax_ide.c	(revision 5263)
+++ src/southbridge/intel/i82801ax/i82801ax_ide.c	(working copy)
@@ -43,9 +43,9 @@
 	if (!config || config->ide0_enable) {
 		/* Enable primary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE0: Primary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE0: Primary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -54,9 +54,9 @@
 	if (!config || config->ide1_enable) {
 		/* Enable secondary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE1: Secondary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE1: Secondary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }
Index: src/southbridge/intel/i82801ax/i82801ax_lpc.c
===================================================================
--- src/southbridge/intel/i82801ax/i82801ax_lpc.c	(revision 5263)
+++ src/southbridge/intel/i82801ax/i82801ax_lpc.c	(working copy)
@@ -92,14 +92,14 @@
 	reg32 |= (1 << 1);	/* Delayed transaction enable */
 	reg32 |= (1 << 2);	/* DMA collection buffer enable */
 	pci_write_config32(dev, GEN_CNTL, reg32);
-	printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
 	*ioapic_index = 0;
 	*ioapic_data = (1 << 25);
 
 	*ioapic_index = 0;
 	reg32 = *ioapic_data;
-	printk_debug("Southbridge APIC ID = %x\n", reg32);
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
 	if (reg32 != (1 << 25))
 		die("APIC Error\n");
 
@@ -189,7 +189,7 @@
 	 * 1 == S5 Soft Off
 	 */
 	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-	printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
+	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
 
 	/* Set up NMI on errors. */
 	byte = inb(0x61);
Index: src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c
===================================================================
--- src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c	(revision 5263)
+++ src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c	(working copy)
@@ -30,11 +30,11 @@
 	/* TODO: Is any special init really needed? */
 	uint32_t cmd;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
Index: src/southbridge/intel/i82371eb/i82371eb_ide.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_ide.c	(revision 5263)
+++ src/southbridge/intel/i82371eb/i82371eb_ide.c	(working copy)
@@ -48,14 +48,14 @@
 	reg16 = pci_read_config16(dev, IDETIM_PRI);
 	reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE);
 	pci_write_config16(dev, IDETIM_PRI, reg16);
-	printk_debug("IDE: %s: %s\n", "Primary IDE interface",
+	printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface",
 		     conf->ide0_enable ? "on" : "off");
 
 	/* Enable/disable the secondary IDE interface. */
 	reg16 = pci_read_config16(dev, IDETIM_SEC);
 	reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE);
 	pci_write_config16(dev, IDETIM_SEC, reg16);
-	printk_debug("IDE: %s: %s\n", "Secondary IDE interface",
+	printk(BIOS_DEBUG, "IDE: %s: %s\n", "Secondary IDE interface",
 		     conf->ide1_enable ? "on" : "off");
 
 	/* Enable access to the legacy IDE ports (both primary and secondary),
@@ -67,7 +67,7 @@
 		reg16 = ONOFF(conf->ide_legacy_enable, reg16,
 			      (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
 		pci_write_config16(dev, PCI_COMMAND, reg16);
-		printk_debug("IDE: Access to legacy IDE ports: %s\n",
+		printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n",
 			     conf->ide_legacy_enable ? "on" : "off");
 	}
 }
@@ -96,10 +96,10 @@
 		reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1);
 		pci_write_config8(dev, UDMACTL, reg8);
 
-		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
 			     "Primary IDE interface", 0,
 			     conf->ide0_drive0_udma33_enable ? "on" : "off");
-		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
 			     "Primary IDE interface", 1,
 			     conf->ide0_drive1_udma33_enable ? "on" : "off");
 	}
@@ -111,10 +111,10 @@
 		reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1);
 		pci_write_config8(dev, UDMACTL, reg8);
 
-		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
 			     "Secondary IDE interface", 0,
 			     conf->ide1_drive0_udma33_enable ? "on" : "off");
-		printk_debug("IDE: %s, drive %d: UDMA/33: %s\n",
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
 			     "Secondary IDE interface", 1,
 			     conf->ide1_drive1_udma33_enable ? "on" : "off");
 	}
Index: src/southbridge/intel/i82801bx/i82801bx_watchdog.c
===================================================================
--- src/southbridge/intel/i82801bx/i82801bx_watchdog.c	(revision 5263)
+++ src/southbridge/intel/i82801bx/i82801bx_watchdog.c	(working copy)
@@ -50,5 +50,5 @@
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
 
-	printk_debug("ICH Watchdog disabled\r\n");
+	printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n");
 }
Index: src/southbridge/intel/i82801bx/i82801bx_ide.c
===================================================================
--- src/southbridge/intel/i82801bx/i82801bx_ide.c	(revision 5263)
+++ src/southbridge/intel/i82801bx/i82801bx_ide.c	(working copy)
@@ -43,9 +43,9 @@
 	if (!config || config->ide0_enable) {
 		/* Enable primary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE0: Primary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE0: Primary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -54,9 +54,9 @@
 	if (!config || config->ide1_enable) {
 		/* Enable secondary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE1: Secondary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE1: Secondary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }
Index: src/southbridge/intel/i82801bx/i82801bx_lpc.c
===================================================================
--- src/southbridge/intel/i82801bx/i82801bx_lpc.c	(revision 5263)
+++ src/southbridge/intel/i82801bx/i82801bx_lpc.c	(working copy)
@@ -92,14 +92,14 @@
 	reg32 |= (1 << 1);	/* Delayed transaction enable */
 	reg32 |= (1 << 2);	/* DMA collection buffer enable */
 	pci_write_config32(dev, GEN_CNTL, reg32);
-	printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
 	*ioapic_index = 0;
 	*ioapic_data = (1 << 25);
 
 	*ioapic_index = 0;
 	reg32 = *ioapic_data;
-	printk_debug("Southbridge APIC ID = %x\n", reg32);
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
 	if (reg32 != (1 << 25))
 		die("APIC Error\n");
 
@@ -189,7 +189,7 @@
 	 * 1 == S5 Soft Off
 	 */
 	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-	printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
+	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
 
 	/* Set up NMI on errors. */
 	byte = inb(0x61);
Index: src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c
===================================================================
--- src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c	(revision 5263)
+++ src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c	(working copy)
@@ -30,11 +30,11 @@
 	/* TODO: Is any special init really needed? */
 	uint32_t cmd;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
Index: src/southbridge/intel/i82801cx/i82801cx_usb.c
===================================================================
--- src/southbridge/intel/i82801cx/i82801cx_usb.c	(revision 5263)
+++ src/southbridge/intel/i82801cx/i82801cx_usb.c	(working copy)
@@ -10,14 +10,14 @@
 
 #if 0
 	uint32_t cmd;
-	printk_debug("USB: Setting up controller.. ");
+	printk(BIOS_DEBUG, "USB: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, 
 		cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 
 		PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
 
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 
 }
Index: src/southbridge/intel/i82801cx/i82801cx_ide.c
===================================================================
--- src/southbridge/intel/i82801cx/i82801cx_ide.c	(revision 5263)
+++ src/southbridge/intel/i82801cx/i82801cx_ide.c	(working copy)
@@ -18,7 +18,7 @@
 	if (enable_primary) {
 		/* Enable first ide interface */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE0 ");
+		printk(BIOS_DEBUG, "IDE0 ");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -27,7 +27,7 @@
     if (enable_secondary) {
 		/* Enable secondary ide interface */
         ideTimingConfig |= IDE_DECODE_ENABLE;
-        printk_debug("IDE1 ");
+        printk(BIOS_DEBUG, "IDE1 ");
 	}
     pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }
Index: src/southbridge/intel/i82801cx/i82801cx_lpc.c
===================================================================
--- src/southbridge/intel/i82801cx/i82801cx_lpc.c	(revision 5263)
+++ src/southbridge/intel/i82801cx/i82801cx_lpc.c	(working copy)
@@ -35,7 +35,7 @@
     dword |= (1 << 1); /* delay transaction enable */
     dword |= (1 << 2); /* DMA collection buf enable */
     pci_write_config32(dev, GEN_CNTL, dword);
-    printk_debug("ioapic southbridge enabled %x\n",dword);
+    printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword);
         
     // Must program the APIC's ID before using it
 
@@ -45,7 +45,7 @@
     // Hang if the ID didn't take (chip not present?)
     *ioapic_index = 0;
     dword = *ioapic_data;
-    printk_debug("Southbridge apic id = %x\n", (dword>>24) & 0xF);
+    printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF);
     if(dword != (2<<24))
 		die("");
 
@@ -105,7 +105,7 @@
 		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
 	}
 	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
-	printk_info("set power %s after power fail\n", 
+	printk(BIOS_INFO, "set power %s after power fail\n", 
 				 pwr_on ? "on" : "off");
 
     // See if the Safe Mode jumper is set
@@ -177,7 +177,7 @@
     else
     	byte |= 1;		// Return to S5
     pci_write_config8(dev, GEN_PMCON_3, byte);
-    printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+    printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
 
     /* Set up NMI on errors */
     byte = inb(0x61);
Index: src/southbridge/intel/i82801dx/i82801dx_smi.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_smi.c	(revision 5263)
+++ src/southbridge/intel/i82801dx/i82801dx_smi.c	(working copy)
@@ -63,16 +63,16 @@
 
 static void dump_pm1_status(u16 pm1_sts)
 {
-	printk_debug("PM1_STS: ");
-	if (pm1_sts & (1 << 15)) printk_debug("WAK ");
-	if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
-	if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
-	if (pm1_sts & (1 << 10)) printk_debug("RTC ");
-	if (pm1_sts & (1 <<  8)) printk_debug("PWRBTN ");
-	if (pm1_sts & (1 <<  5)) printk_debug("GBL ");
-	if (pm1_sts & (1 <<  4)) printk_debug("BM ");
-	if (pm1_sts & (1 <<  0)) printk_debug("TMROF ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_DEBUG, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_DEBUG, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_DEBUG, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_DEBUG, "TMROF ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 /**
@@ -92,28 +92,28 @@
 
 static void dump_smi_status(u32 smi_sts)
 {
-	printk_debug("SMI_STS: ");
-	if (smi_sts & (1 << 26)) printk_debug("SPI ");
-	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
-	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
-	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
-	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
-	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
-	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
-	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
-	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
-	if (smi_sts & (1 << 13)) printk_debug("TCO ");
-	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
-	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
-	if (smi_sts & (1 << 10)) printk_debug("GPI ");
-	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
-	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
-	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
-	if (smi_sts & (1 <<  5)) printk_debug("APM ");
-	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
-	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
-	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -135,25 +135,25 @@
 static void dump_gpe0_status(u32 gpe0_sts)
 {
 	int i;
-	printk_debug("GPE0_STS: ");
+	printk(BIOS_DEBUG, "GPE0_STS: ");
 	for (i=31; i<= 16; i--) {
-		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 	}
-	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
-	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
-	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
-	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
-	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
-	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
-	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
-	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
-	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
-	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
-	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
-	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
-	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
-	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
-	printk_debug("\n");
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -175,11 +175,11 @@
 static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
 {
 	int i;
-	printk_debug("ALT_GP_SMI_STS: ");
+	printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
 	for (i=15; i<= 0; i--) {
-		if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16));
+		if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -205,21 +205,21 @@
 
 static void dump_tco_status(u32 tco_sts)
 {
-	printk_debug("TCO_STS: ");
-	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
-	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
-	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
-	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
-	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
-	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
-	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
-	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
-	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
-	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
-	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
-	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
-	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -243,14 +243,14 @@
 	u32 smi_en;
 	u16 pm1_en;
 
-	printk_debug("Initializing SMM handler...");
+	printk(BIOS_DEBUG, "Initializing SMM handler...");
 
 	pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
-	printk_spew(" ... pmbase = 0x%04x\n", pmbase);
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
 
 	smi_en = inl(pmbase + SMI_EN);
 	if (smi_en & APMC_EN) {
-		printk_info("SMI# handler already enabled?\n");
+		printk(BIOS_INFO, "SMI# handler already enabled?\n");
 		return;
 	}
 
@@ -258,7 +258,7 @@
 	memcpy((void *)0x38000, &smm_relocation_start,
 			&smm_relocation_end - &smm_relocation_start);
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	dump_smi_status(reset_smi_status());
 	dump_pm1_status(reset_pm1_status());
 	dump_gpe0_status(reset_gpe0_status());
@@ -314,7 +314,7 @@
 	 */
 
 	/* raise an SMI interrupt */
-	printk_spew("  ... raise SMI#\n");
+	printk(BIOS_SPEW, "  ... raise SMI#\n");
 	outb(0x00, 0xb2);
 }
 
@@ -349,7 +349,7 @@
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
-	printk_debug("Locking SMM.\n");
+	printk(BIOS_DEBUG, "Locking SMM.\n");
 	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
 			D_LCK | G_SMRAME | C_BASE_SEG);
 }
Index: src/southbridge/intel/i82801dx/i82801dx_usb.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_usb.c	(revision 5263)
+++ src/southbridge/intel/i82801dx/i82801dx_usb.c	(working copy)
@@ -29,12 +29,12 @@
 static void usb_init(struct device *dev)
 {
 	u32 cmd;
-	printk_debug("USB: Setting up controller.. ");
+	printk(BIOS_DEBUG, "USB: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND,
 			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static struct device_operations usb_ops = {
Index: src/southbridge/intel/i82801dx/i82801dx_ide.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_ide.c	(revision 5263)
+++ src/southbridge/intel/i82801dx/i82801dx_ide.c	(working copy)
@@ -40,9 +40,9 @@
 	if (!config || config->ide0_enable) {
 		/* Enable primary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE0: Primary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE0: Primary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -51,9 +51,9 @@
 	if (!config || config->ide1_enable) {
 		/* Enable secondary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
-		printk_debug("IDE1: Secondary IDE interface is enabled\n");
+		printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
 	} else {
-		printk_info("IDE1: Secondary IDE interface is disabled\n");
+		printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }
Index: src/southbridge/intel/i82801dx/i82801dx_ac97.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_ac97.c	(revision 5263)
+++ src/southbridge/intel/i82801dx/i82801dx_ac97.c	(working copy)
@@ -101,7 +101,7 @@
 		timeout--;
 	} while ((reg8 & 1) && timeout);
 	if (! timeout) {
-		printk_debug("Timeout!\n");
+		printk(BIOS_DEBUG, "Timeout!\n");
 	}
 
 	return (!timeout);
@@ -123,7 +123,7 @@
 	u32 reg32;
 	int i;
 
-	printk_debug("Initializing AC'97 Audio.\n");
+	printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
 
 	/* top 16 bits are zero, so don't read them */
 	nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
@@ -142,7 +142,7 @@
 	reg32 = inl(nabmbar + GLOB_STA);
 	if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
 		/* Primary Codec not found */
-		printk_debug("No primary codec. Disabling AC'97 Audio.\n");
+		printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
 		return;
 	}
 
@@ -152,7 +152,7 @@
 	outw(0x8000, nambar + MASTER_VOL);
 	ac97_semaphore();
 	if (inw(nambar + MASTER_VOL) != 0x8000) {
-		printk_debug("Codec not programmable. Disabling AC'97 Audio.\n");
+		printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
 		return;
 	}
 
Index: src/southbridge/intel/i82801dx/i82801dx_usb2.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_usb2.c	(revision 5263)
+++ src/southbridge/intel/i82801dx/i82801dx_usb2.c	(working copy)
@@ -29,12 +29,12 @@
 static void usb2_init(struct device *dev)
 {
 	u32 cmd;
-	printk_debug("USB: Setting up controller.. ");
+	printk(BIOS_DEBUG, "USB: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND,
 			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static struct device_operations usb2_ops = {
Index: src/southbridge/intel/i82801dx/i82801dx_lpc.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_lpc.c	(revision 5263)
+++ src/southbridge/intel/i82801dx/i82801dx_lpc.c	(working copy)
@@ -53,14 +53,14 @@
 	reg32 |= (1 << 1);	/* Delayed transaction enable */
 	reg32 |= (1 << 2);	/* DMA collection buffer enable */
 	pci_write_config32(dev, GEN_CNTL, reg32);
-	printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
 	*ioapic_index = 0;
 	*ioapic_data = (1 << 25);
 
 	*ioapic_index = 0;
 	reg32 = *ioapic_data;
-	printk_debug("Southbridge APIC ID = %x\n", reg32);
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
 	if (reg32 != (1 << 25))
 		die("APIC Error\n");
 
@@ -107,7 +107,7 @@
 	 * 1 == S5 Soft Off
 	 */
 	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-	printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
+	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
 
 	/* Set up NMI on errors. */
 	byte = inb(0x61);
@@ -198,7 +198,7 @@
 	reg32 |= (code << 15);
 	pci_write_config32(dev, GEN_CNTL, reg32);
 
-	printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
+	printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
 }
 
 static void lpc_init(struct device *dev)
Index: src/southbridge/intel/i82801dx/i82801dx_smihandler.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_smihandler.c	(revision 5263)
+++ src/southbridge/intel/i82801dx/i82801dx_smihandler.c	(working copy)
@@ -83,18 +83,18 @@
 
 static void dump_pm1_status(u16 pm1_sts)
 {
-	printk_spew("PM1_STS: ");
-	if (pm1_sts & (1 << 15)) printk_spew("WAK ");
-	if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK ");
-	if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR ");
-	if (pm1_sts & (1 << 10)) printk_spew("RTC ");
-	if (pm1_sts & (1 <<  8)) printk_spew("PWRBTN ");
-	if (pm1_sts & (1 <<  5)) printk_spew("GBL ");
-	if (pm1_sts & (1 <<  4)) printk_spew("BM ");
-	if (pm1_sts & (1 <<  0)) printk_spew("TMROF ");
-	printk_spew("\n");
+	printk(BIOS_SPEW, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_SPEW, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_SPEW, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_SPEW, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_SPEW, "TMROF ");
+	printk(BIOS_SPEW, "\n");
 	int reg16 = inw(pmbase + PM1_EN);
-	printk_spew("PM1_EN: %x\n", reg16);
+	printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
 }
 
 /**
@@ -114,28 +114,28 @@
 
 static void dump_smi_status(u32 smi_sts)
 {
-	printk_debug("SMI_STS: ");
-	if (smi_sts & (1 << 26)) printk_debug("SPI ");
-	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
-	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
-	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
-	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
-	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
-	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
-	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
-	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
-	if (smi_sts & (1 << 13)) printk_debug("TCO ");
-	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
-	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
-	if (smi_sts & (1 << 10)) printk_debug("GPI ");
-	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
-	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
-	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
-	if (smi_sts & (1 <<  5)) printk_debug("APM ");
-	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
-	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
-	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -157,25 +157,25 @@
 static void dump_gpe0_status(u32 gpe0_sts)
 {
 	int i;
-	printk_debug("GPE0_STS: ");
+	printk(BIOS_DEBUG, "GPE0_STS: ");
 	for (i=31; i<= 16; i--) {
-		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 	}
-	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
-	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
-	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
-	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
-	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
-	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
-	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
-	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
-	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
-	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
-	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
-	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
-	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
-	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
-	printk_debug("\n");
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -200,21 +200,21 @@
 
 static void dump_tco_status(u32 tco_sts)
 {
-	printk_debug("TCO_STS: ");
-	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
-	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
-	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
-	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
-	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
-	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
-	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
-	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
-	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
-	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
-	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
-	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
-	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 /* We are using PCIe accesses for now
@@ -227,7 +227,7 @@
 {
 	switch (smif) {
 	case 0x32:
-		printk_debug("OS Init\n");
+		printk(BIOS_DEBUG, "OS Init\n");
 		/* gnvs->smif:
 		 *  On success, the IO Trap Handler returns 0
 		 *  On failure, the IO Trap Handler returns a value != 0
@@ -306,23 +306,23 @@
 
 	/* Figure out SLP_TYP */
 	reg32 = inl(pmbase + PM1_CNT);
-	printk_spew("SMI#: SLP = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
 	slp_typ = (reg32 >> 10) & 7;
 
 	/* Next, do the deed.
 	 */
 
 	switch (slp_typ) {
-	case 0: printk_debug("SMI#: Entering S0 (On)\n"); break;
-	case 1: printk_debug("SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+	case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+	case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
 	case 5:
-		printk_debug("SMI#: Entering S3 (Suspend-To-RAM)\n");
+		printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
 		/* Invalidate the cache before going to S3 */
 		wbinvd();
 		break;
-	case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+	case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
 	case 7:
-		printk_debug("SMI#: Entering S5 (Soft Power off)\n");
+		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 
 		outl(0, pmbase + GPE0_EN);
 
@@ -340,7 +340,7 @@
 		/* also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);
 		break;
-	default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break;
+	default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
 	}
 
 	/* Write back to the SLP register to cause the originally intended
@@ -375,51 +375,51 @@
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
-		printk_debug("C-state control\n");
+		printk(BIOS_DEBUG, "C-state control\n");
 		break;
 	case PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
-		printk_debug("P-state control\n");
+		printk(BIOS_DEBUG, "P-state control\n");
 		break;
 	case ACPI_DISABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
-		printk_debug("SMI#: ACPI disabled.\n");
+		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
 	case ACPI_ENABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
-		printk_debug("SMI#: ACPI enabled.\n");
+		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
 	case GNVS_UPDATE:
 		if (smm_initialized) {
-			printk_debug("SMI#: SMM structures already initialized!\n");
+			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
 		}
 		gnvs = *(global_nvs_t **)0x500;
 		tcg  = *(void **)0x504;
 		smi1 = *(void **)0x508;
 		smm_initialized = 1;
-		printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
+		printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
 		break;
 	case MBI_UPDATE: // FIXME
 		if (mbi_initialized) {
-			printk_debug("SMI#: mbi already registered!\n");
+			printk(BIOS_DEBUG, "SMI#: mbi already registered!\n");
 			return;
 		}
 		mbi = *(void **)0x500;
 		mbi_len = *(u32 *)0x504;
 		mbi_initialized = 1;
-		printk_debug("SMI#: Registered MBI at %p (%d bytes)\n", mbi, mbi_len);
+		printk(BIOS_DEBUG, "SMI#: Registered MBI at %p (%d bytes)\n", mbi, mbi_len);
 		break;
 
 	default:
-		printk_debug("SMI#: Unknown function APM_CNT=%02x\n", reg8);
+		printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
 	}
 }
 
@@ -463,7 +463,7 @@
 		mainboard_smi_gpi(reg16);
 	} else {
 		if (reg16)
-			printk_debug("GPI (mask %04x)\n",reg16);
+			printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
 	}
 }
 
@@ -477,7 +477,7 @@
 	if ((reg32 & MCSMI_EN) == 0)
 		return;
 
-	printk_debug("Microcontroller SMI.\n");
+	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
 
 
@@ -508,12 +508,12 @@
 			 * resolute answer would be to power down the
 			 * box.
 			 */
-			printk_debug("Switching back to RO\n");
+			printk(BIOS_DEBUG, "Switching back to RO\n");
 			pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
 		} /* No else for now? */
 	} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
 		/* Handle TCO timeout */
-		printk_debug("TCO Timeout.\n");
+		printk(BIOS_DEBUG, "TCO Timeout.\n");
 	} else if (!tco_sts) {
 		dump_tco_status(tco_sts);
 	}
@@ -529,7 +529,7 @@
 	if ((reg32 & PERIODIC_EN) == 0)
 		return;
 
-	printk_debug("Periodic SMI.\n");
+	printk(BIOS_DEBUG, "Periodic SMI.\n");
 }
 
 static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
@@ -563,7 +563,7 @@
 	/* IOTRAP(0) SMIC */
 	if (IOTRAP(0)) {
 		if (!(trap_cycle & (1 << 24))) { // It's a write
-			printk_debug("SMI1 command\n");
+			printk(BIOS_DEBUG, "SMI1 command\n");
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
@@ -573,16 +573,16 @@
 		// Fall through to debug
 	}
 
-	printk_debug("  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
-	for (i=0; i < 4; i++) if(IOTRAP(i)) printk_debug("  TRAP = %d\n", i);
-	printk_debug("  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
-	printk_debug("  MASK = 0x%08x\n", mask);
-	printk_debug("  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
+	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+	for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
+	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
+	printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
 
 	if (!(trap_cycle & (1 << 24))) {
 		/* Write Cycle */
 		data = RCBA32(0x1e18);
-		printk_debug("  iotrap written data = 0x%08x\n", data);
+		printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
 	}
 #endif
 #undef IOTRAP
@@ -655,7 +655,7 @@
 			if (southbridge_smi[i])
 				southbridge_smi[i](node, state_save);
 			else {
-				printk_debug("SMI_STS[%d] occured, but no "
+				printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
 						"handler available.\n", i);
 				dump = 1;
 			}
Index: src/southbridge/intel/i82801ex/i82801ex_uhci.c
===================================================================
--- src/southbridge/intel/i82801ex/i82801ex_uhci.c	(revision 5263)
+++ src/southbridge/intel/i82801ex/i82801ex_uhci.c	(working copy)
@@ -10,13 +10,13 @@
 	uint32_t cmd;
 
 #if 1
-	printk_debug("UHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, 
 		cmd | PCI_COMMAND_MASTER);
 
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 
 }
Index: src/southbridge/intel/i82801ex/i82801ex_sata.c
===================================================================
--- src/southbridge/intel/i82801ex/i82801ex_sata.c	(revision 5263)
+++ src/southbridge/intel/i82801ex/i82801ex_sata.c	(working copy)
@@ -7,7 +7,7 @@
 
 static void sata_init(struct device *dev)
 {
-  	printk_debug("SATA init\n");
+  	printk(BIOS_DEBUG, "SATA init\n");
 	/* SATA configuration */
 	pci_write_config8(dev, 0x04, 0x07);
 	pci_write_config8(dev, 0x09, 0x8f);
Index: src/southbridge/intel/i82801ex/i82801ex_watchdog.c
===================================================================
--- src/southbridge/intel/i82801ex/i82801ex_watchdog.c	(revision 5263)
+++ src/southbridge/intel/i82801ex/i82801ex_watchdog.c	(working copy)
@@ -24,6 +24,6 @@
         /* Clear TCO timeout status */
         outw(0x0008, base + 0x04);
         outw(0x0002, base + 0x06);
-        printk_debug("Watchdog ICH5 disabled\r\n");
+        printk(BIOS_DEBUG, "Watchdog ICH5 disabled\r\n");
 }
 
Index: src/southbridge/intel/i82801ex/i82801ex_ide.c
===================================================================
--- src/southbridge/intel/i82801ex/i82801ex_ide.c	(revision 5263)
+++ src/southbridge/intel/i82801ex/i82801ex_ide.c	(working copy)
@@ -13,7 +13,7 @@
 	pci_write_config8(dev, 0x48, 0x05);
 	pci_write_config16(dev, 0x4a, 0x0101);
 	pci_write_config16(dev, 0x54, 0x5055);
-	printk_debug("IDE Enabled\n");
+	printk(BIOS_DEBUG, "IDE Enabled\n");
 }
 
 static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/i82801ex/i82801ex_ehci.c
===================================================================
--- src/southbridge/intel/i82801ex/i82801ex_ehci.c	(revision 5263)
+++ src/southbridge/intel/i82801ex/i82801ex_ehci.c	(working copy)
@@ -9,12 +9,12 @@
 {
 	uint32_t cmd;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, 
 		cmd | PCI_COMMAND_MASTER);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/i82801ex/i82801ex_lpc.c
===================================================================
--- src/southbridge/intel/i82801ex/i82801ex_lpc.c	(revision 5263)
+++ src/southbridge/intel/i82801ex/i82801ex_lpc.c	(working copy)
@@ -233,7 +233,7 @@
 	dword |= (code<<15);
 	pci_write_config32(dev, GEN_CNTL, dword);
 
-	printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) );
+	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
 }
 
 static void lpc_init(struct device *dev)
@@ -267,7 +267,7 @@
 		byte |= 1;
 	}
 	pci_write_config8(dev, 0xa4, byte);
-	printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+	printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
 
 	/* Set up the PIRQ */
 	i82801ex_pirq_init(dev);
Index: src/southbridge/intel/i82801gx/i82801gx_smihandler.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_smihandler.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_smihandler.c	(working copy)
@@ -76,18 +76,18 @@
 
 static void dump_pm1_status(u16 pm1_sts)
 {
-	printk_spew("PM1_STS: ");
-	if (pm1_sts & (1 << 15)) printk_spew("WAK ");
-	if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK ");
-	if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR ");
-	if (pm1_sts & (1 << 10)) printk_spew("RTC ");
-	if (pm1_sts & (1 <<  8)) printk_spew("PWRBTN ");
-	if (pm1_sts & (1 <<  5)) printk_spew("GBL ");
-	if (pm1_sts & (1 <<  4)) printk_spew("BM ");
-	if (pm1_sts & (1 <<  0)) printk_spew("TMROF ");
-	printk_spew("\n");
+	printk(BIOS_SPEW, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_SPEW, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_SPEW, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_SPEW, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_SPEW, "TMROF ");
+	printk(BIOS_SPEW, "\n");
 	int reg16 = inw(pmbase + PM1_EN);
-	printk_spew("PM1_EN: %x\n", reg16);
+	printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
 }
 
 /**
@@ -107,28 +107,28 @@
 
 static void dump_smi_status(u32 smi_sts)
 {
-	printk_debug("SMI_STS: ");
-	if (smi_sts & (1 << 26)) printk_debug("SPI ");
-	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
-	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
-	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
-	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
-	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
-	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
-	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
-	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
-	if (smi_sts & (1 << 13)) printk_debug("TCO ");
-	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
-	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
-	if (smi_sts & (1 << 10)) printk_debug("GPI ");
-	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
-	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
-	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
-	if (smi_sts & (1 <<  5)) printk_debug("APM ");
-	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
-	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
-	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -150,25 +150,25 @@
 static void dump_gpe0_status(u32 gpe0_sts)
 {
 	int i;
-	printk_debug("GPE0_STS: ");
+	printk(BIOS_DEBUG, "GPE0_STS: ");
 	for (i=31; i<= 16; i--) {
-		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 	}
-	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
-	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
-	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
-	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
-	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
-	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
-	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
-	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
-	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
-	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
-	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
-	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
-	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
-	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
-	printk_debug("\n");
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -193,21 +193,21 @@
 
 static void dump_tco_status(u32 tco_sts)
 {
-	printk_debug("TCO_STS: ");
-	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
-	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
-	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
-	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
-	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
-	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
-	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
-	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
-	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
-	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
-	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
-	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
-	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 /* We are using PCIe accesses for now
@@ -220,7 +220,7 @@
 {
 	switch (smif) {
 	case 0x32:
-		printk_debug("OS Init\n");
+		printk(BIOS_DEBUG, "OS Init\n");
 		/* gnvs->smif:
 		 *  On success, the IO Trap Handler returns 0
 		 *  On failure, the IO Trap Handler returns a value != 0
@@ -299,23 +299,23 @@
 
 	/* Figure out SLP_TYP */
 	reg32 = inl(pmbase + PM1_CNT);
-	printk_spew("SMI#: SLP = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
 	slp_typ = (reg32 >> 10) & 7;
 
 	/* Next, do the deed.
 	 */
 
 	switch (slp_typ) {
-	case 0: printk_debug("SMI#: Entering S0 (On)\n"); break;
-	case 1: printk_debug("SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+	case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+	case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
 	case 5:
-		printk_debug("SMI#: Entering S3 (Suspend-To-RAM)\n");
+		printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
 		/* Invalidate the cache before going to S3 */
 		wbinvd();
 		break;
-	case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+	case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
 	case 7:
-		printk_debug("SMI#: Entering S5 (Soft Power off)\n");
+		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 
 		outl(0, pmbase + GPE0_EN);
 
@@ -333,7 +333,7 @@
 		/* also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);
 		break;
-	default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break;
+	default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
 	}
 
 	/* Write back to the SLP register to cause the originally intended
@@ -368,40 +368,40 @@
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
-		printk_debug("C-state control\n");
+		printk(BIOS_DEBUG, "C-state control\n");
 		break;
 	case PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
-		printk_debug("P-state control\n");
+		printk(BIOS_DEBUG, "P-state control\n");
 		break;
 	case ACPI_DISABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
-		printk_debug("SMI#: ACPI disabled.\n");
+		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
 	case ACPI_ENABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
-		printk_debug("SMI#: ACPI enabled.\n");
+		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
 	case GNVS_UPDATE:
 		if (smm_initialized) {
-			printk_debug("SMI#: SMM structures already initialized!\n");
+			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
 		}
 		gnvs = *(global_nvs_t **)0x500;
 		tcg  = *(void **)0x504;
 		smi1 = *(void **)0x508;
 		smm_initialized = 1;
-		printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
+		printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
 		break;
 	default:
-		printk_debug("SMI#: Unknown function APM_CNT=%02x\n", reg8);
+		printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
 	}
 }
 
@@ -445,7 +445,7 @@
 		mainboard_smi_gpi(reg16);
 	} else {
 		if (reg16)
-			printk_debug("GPI (mask %04x)\n",reg16);
+			printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
 	}
 }
 
@@ -459,7 +459,7 @@
 	if ((reg32 & MCSMI_EN) == 0)
 		return;
 
-	printk_debug("Microcontroller SMI.\n");
+	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
 
 
@@ -490,12 +490,12 @@
 			 * resolute answer would be to power down the
 			 * box.
 			 */
-			printk_debug("Switching back to RO\n");
+			printk(BIOS_DEBUG, "Switching back to RO\n");
 			pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
 		} /* No else for now? */
 	} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
 		/* Handle TCO timeout */
-		printk_debug("TCO Timeout.\n");
+		printk(BIOS_DEBUG, "TCO Timeout.\n");
 	} else if (!tco_sts) {
 		dump_tco_status(tco_sts);
 	}
@@ -511,7 +511,7 @@
 	if ((reg32 & PERIODIC_EN) == 0)
 		return;
 
-	printk_debug("Periodic SMI.\n");
+	printk(BIOS_DEBUG, "Periodic SMI.\n");
 }
 
 static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
@@ -544,7 +544,7 @@
 	/* IOTRAP(0) SMIC */
 	if (IOTRAP(0)) {
 		if (!(trap_cycle & (1 << 24))) { // It's a write
-			printk_debug("SMI1 command\n");
+			printk(BIOS_DEBUG, "SMI1 command\n");
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
@@ -554,16 +554,16 @@
 		// Fall through to debug
 	}
 
-	printk_debug("  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
-	for (i=0; i < 4; i++) if(IOTRAP(i)) printk_debug("  TRAP = %d\n", i);
-	printk_debug("  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
-	printk_debug("  MASK = 0x%08x\n", mask);
-	printk_debug("  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
+	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+	for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
+	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
+	printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
 
 	if (!(trap_cycle & (1 << 24))) {
 		/* Write Cycle */
 		data = RCBA32(0x1e18);
-		printk_debug("  iotrap written data = 0x%08x\n", data);
+		printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
 	}
 #undef IOTRAP
 }
@@ -635,7 +635,7 @@
 			if (southbridge_smi[i])
 				southbridge_smi[i](node, state_save);
 			else {
-				printk_debug("SMI_STS[%d] occured, but no "
+				printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
 						"handler available.\n", i);
 				dump = 1;
 			}
Index: src/southbridge/intel/i82801gx/i82801gx_smi.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_smi.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_smi.c	(working copy)
@@ -63,16 +63,16 @@
 
 static void dump_pm1_status(u16 pm1_sts)
 {
-	printk_debug("PM1_STS: ");
-	if (pm1_sts & (1 << 15)) printk_debug("WAK ");
-	if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
-	if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
-	if (pm1_sts & (1 << 10)) printk_debug("RTC ");
-	if (pm1_sts & (1 <<  8)) printk_debug("PWRBTN ");
-	if (pm1_sts & (1 <<  5)) printk_debug("GBL ");
-	if (pm1_sts & (1 <<  4)) printk_debug("BM ");
-	if (pm1_sts & (1 <<  0)) printk_debug("TMROF ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_DEBUG, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_DEBUG, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_DEBUG, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_DEBUG, "TMROF ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 /**
@@ -92,28 +92,28 @@
 
 static void dump_smi_status(u32 smi_sts)
 {
-	printk_debug("SMI_STS: ");
-	if (smi_sts & (1 << 26)) printk_debug("SPI ");
-	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
-	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
-	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
-	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
-	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
-	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
-	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
-	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
-	if (smi_sts & (1 << 13)) printk_debug("TCO ");
-	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
-	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
-	if (smi_sts & (1 << 10)) printk_debug("GPI ");
-	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
-	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
-	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
-	if (smi_sts & (1 <<  5)) printk_debug("APM ");
-	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
-	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
-	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -135,25 +135,25 @@
 static void dump_gpe0_status(u32 gpe0_sts)
 {
 	int i;
-	printk_debug("GPE0_STS: ");
+	printk(BIOS_DEBUG, "GPE0_STS: ");
 	for (i=31; i<= 16; i--) {
-		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 	}
-	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
-	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
-	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
-	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
-	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
-	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
-	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
-	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
-	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
-	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
-	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
-	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
-	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
-	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
-	printk_debug("\n");
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -175,11 +175,11 @@
 static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
 {
 	int i;
-	printk_debug("ALT_GP_SMI_STS: ");
+	printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
 	for (i=15; i<= 0; i--) {
-		if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16));
+		if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -205,21 +205,21 @@
 
 static void dump_tco_status(u32 tco_sts)
 {
-	printk_debug("TCO_STS: ");
-	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
-	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
-	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
-	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
-	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
-	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
-	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
-	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
-	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
-	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
-	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
-	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
-	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -243,14 +243,14 @@
 	u32 smi_en;
 	u16 pm1_en;
 
-	printk_debug("Initializing SMM handler...");
+	printk(BIOS_DEBUG, "Initializing SMM handler...");
 
 	pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
-	printk_spew(" ... pmbase = 0x%04x\n", pmbase);
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
 
 	smi_en = inl(pmbase + SMI_EN);
 	if (smi_en & APMC_EN) {
-		printk_info("SMI# handler already enabled?\n");
+		printk(BIOS_INFO, "SMI# handler already enabled?\n");
 		return;
 	}
 
@@ -258,7 +258,7 @@
 	memcpy((void *)0x38000, &smm_relocation_start,
 			&smm_relocation_end - &smm_relocation_start);
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	dump_smi_status(reset_smi_status());
 	dump_pm1_status(reset_pm1_status());
 	dump_gpe0_status(reset_gpe0_status());
@@ -314,7 +314,7 @@
 	 */
 
 	/* raise an SMI interrupt */
-	printk_spew("  ... raise SMI#\n");
+	printk(BIOS_SPEW, "  ... raise SMI#\n");
 	outb(0x00, 0xb2);
 }
 
@@ -349,7 +349,7 @@
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
-	printk_debug("Locking SMM.\n");
+	printk(BIOS_DEBUG, "Locking SMM.\n");
 	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
 			D_LCK | G_SMRAME | C_BASE_SEG);
 }
Index: src/southbridge/intel/i82801gx/i82801gx_sata.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_sata.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_sata.c	(working copy)
@@ -33,10 +33,10 @@
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	printk_debug("i82801gx_sata: initializing...\n");
+	printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
 
 	if (config == NULL) {
-		printk_err("i82801gx_sata: error: device not in Config.lb!\n");
+		printk(BIOS_ERR, "i82801gx_sata: error: device not in Config.lb!\n");
 		return;
 	}
 
@@ -46,7 +46,7 @@
 	pci_write_config16(dev, PCI_COMMAND, 0x0007);
 
 	if (config->ide_legacy_combined) {
-		printk_debug("SATA controller in combined mode.\n");
+		printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
 		/* No AHCI: clear AHCI base */
 		pci_write_config32(dev, 0x24, 0x00000000);
 		/* And without AHCI BAR no memory decoding */
@@ -80,7 +80,7 @@
 		/* SATA Initialization register */
 		pci_write_config32(dev, 0x94, 0x5a000180);
 	} else if(config->sata_ahci) {
-		printk_debug("SATA controller in AHCI mode.\n");
+		printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
 		/* Allow both Legacy and Native mode */
 		pci_write_config8(dev, 0x09, 0x8f);
 
@@ -112,7 +112,7 @@
 		/* SATA Initialization register */
 		pci_write_config32(dev, 0x94, 0x1a000180);
 	} else {
-		printk_debug("SATA controller in plain mode.\n");
+		printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
 		/* Set Sata Controller Mode. No Mapping(?) */
 		pci_write_config8(dev, 0x90, 0x00);
 
Index: src/southbridge/intel/i82801gx/i82801gx_usb.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_usb.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_usb.c	(working copy)
@@ -30,7 +30,7 @@
 	u8 reg8;
 
 	/* USB Specification says the device must be Bus Master */
-	printk_debug("UHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
@@ -43,7 +43,7 @@
 	reg8 |= (1 << 0);
 	pci_write_config8(dev, 0xca, reg8);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/i82801gx/i82801gx_smbus.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_smbus.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_smbus.c	(working copy)
@@ -35,11 +35,11 @@
 	u32 smb_base;
 
 	smb_base = pci_read_config32(dev, SMB_BASE);
-	printk_debug("Initializing SMBus device:\n");
-	printk_debug("  Old SMBUS Base Address: 0x%04x\n", smb_base);
+	printk(BIOS_DEBUG, "Initializing SMBus device:\n");
+	printk(BIOS_DEBUG, "  Old SMBUS Base Address: 0x%04x\n", smb_base);
 	pci_write_config32(dev, SMB_BASE, 0x00000401);
 	smb_base = pci_read_config32(dev, SMB_BASE);
-	printk_debug("  New SMBUS Base Address: 0x%04x\n", smb_base);
+	printk(BIOS_DEBUG, "  New SMBUS Base Address: 0x%04x\n", smb_base);
 }
 
 static int lsmbus_read_byte(device_t dev, u8 address)
Index: src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_usb_debug.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_usb_debug.c	(working copy)
@@ -30,7 +30,7 @@
 {
 	u32 dbgctl;
 
-	printk_debug("Enabling OWNER_CNT\n");
+	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
 	dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
 	dbgctl |= (1 << 30);
 	write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
Index: src/southbridge/intel/i82801gx/i82801gx_watchdog.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_watchdog.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_watchdog.c	(working copy)
@@ -49,5 +49,5 @@
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
 
-	printk_debug("ICH7 watchdog disabled\r\n");
+	printk(BIOS_DEBUG, "ICH7 watchdog disabled\r\n");
 }
Index: src/southbridge/intel/i82801gx/i82801gx_ide.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_ide.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_ide.c	(working copy)
@@ -35,9 +35,9 @@
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	printk_debug("i82801gx_ide: initializing... ");
+	printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
 	if (config == NULL) {
-		printk_err("\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
+		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
 		// Trying to set somewhat safe defaults instead of bailing out.
 		enable_primary = enable_secondary = 1;
 	} else {
@@ -61,7 +61,7 @@
 		ideTimingConfig |= (3 << 8); // RCT = 1 clock
 		ideTimingConfig |= (1 << 1); // IE0
 		ideTimingConfig |= (1 << 0); // TIME0
-		printk_debug("IDE0 ");
+		printk(BIOS_DEBUG, "IDE0 ");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -75,7 +75,7 @@
 		ideTimingConfig |= (3 << 8); // RCT = 1 clock
 		ideTimingConfig |= (1 << 1); // IE0
 		ideTimingConfig |= (1 << 0); // TIME0
-		printk_debug("IDE1 ");
+		printk(BIOS_DEBUG, "IDE1 ");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 
@@ -92,7 +92,7 @@
 	/* Interrupt Pin is set by D31IP.PIP */
 	pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/i82801gx/i82801gx_azalia.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_azalia.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_azalia.c	(working copy)
@@ -86,7 +86,7 @@
 	/* Codec Not found */
 	/* Put HDA back in reset (BAR + 0x8) [0] */
 	set_bits(base + 0x08, 1, 0);
-	printk_debug("Azalia: No codec!\n");
+	printk(BIOS_DEBUG, "Azalia: No codec!\n");
 	return 0;
 }
 
@@ -170,7 +170,7 @@
 	u32 verb_size;
 	int i;
 
-	printk_debug("Azalia: Initializing codec #%d\n", addr);
+	printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
 
 	/* 1 */
 	if (wait_for_ready(base) == -1)
@@ -185,14 +185,14 @@
 	reg32 = read32(base + 0x64);
 
 	/* 2 */
-	printk_debug("Azalia: codec viddid: %08x\n", reg32);
+	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
 	verb_size = find_verb(dev, reg32, &verb);
 
 	if (!verb_size) {
-		printk_debug("Azalia: No verb!\n");
+		printk(BIOS_DEBUG, "Azalia: No verb!\n");
 		return;
 	}
-	printk_debug("Azalia: verb_size: %d\n", verb_size);
+	printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
 
 	/* 3 */
 	for (i = 0; i < verb_size; i++) {
@@ -204,7 +204,7 @@
 		if (wait_for_valid(base) == -1)
 			return;
 	}
-	printk_debug("Azalia: verb loaded.\n");
+	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
 }
 
 static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
@@ -275,7 +275,7 @@
 	pci_write_config8(dev, 0x40, reg8);
 	mdelay(1);
 	reg8 = pci_read_config8(dev, 0x40);
-	printk_debug("Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
+	printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
 
 	//
 	reg8 = pci_read_config8(dev, 0x40); // Audio Control
@@ -304,11 +304,11 @@
 	// NOTE this will break as soon as the Azalia get's a bar above
 	// 4G. Is there anything we can do about it?
 	base = (u32)res->base;
-	printk_debug("Azalia: base = %08x\n", (u32)base);
+	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
-		printk_debug("Azalia: codec_mask = %02x\n", codec_mask);
+		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
 		codecs_init(dev, base, codec_mask);
 	}
 }
Index: src/southbridge/intel/i82801gx/i82801gx_ac97.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_ac97.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_ac97.c	(working copy)
@@ -101,7 +101,7 @@
 		timeout--;
 	} while ((reg8 & 1) && timeout);
 	if (! timeout) {
-		printk_debug("Timeout!\n");
+		printk(BIOS_DEBUG, "Timeout!\n");
 	}
 
 	return (!timeout);
@@ -123,7 +123,7 @@
 	u32 reg32;
 	int i;
 
-	printk_debug("Initializing AC'97 Audio.\n");
+	printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
 
 	/* top 16 bits are zero, so don't read them */
 	nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
@@ -142,7 +142,7 @@
 	reg32 = inl(nabmbar + GLOB_STA);
 	if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
 		/* Primary Codec not found */
-		printk_debug("No primary codec. Disabling AC'97 Audio.\n");
+		printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
 		return;
 	}
 
@@ -152,7 +152,7 @@
 	outw(0x8000, nambar + MASTER_VOL);
 	ac97_semaphore();
 	if (inw(nambar + MASTER_VOL) != 0x8000) {
-		printk_debug("Codec not programmable. Disabling AC'97 Audio.\n");
+		printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
 		return;
 	}
 
Index: src/southbridge/intel/i82801gx/i82801gx_pci.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_pci.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_pci.c	(working copy)
@@ -71,7 +71,7 @@
 	/* Set the subsystem vendor and device id for mainboard devices */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk_debug("%s subsystem <- %02x/%02x\n",
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
 			dev_path(dev),
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
@@ -87,10 +87,10 @@
 	 * this will cause the ROM and APICs not being visible
 	 * anymore.
 	 */
-	printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
+	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
 #else
-	printk_debug("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+	printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
 #endif
 }
 
@@ -105,7 +105,7 @@
 	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 	ctrl |= dev->link[0].bridge_ctrl;
 	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
-	printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+	printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
 	/* This is the reason we need our own pci_bus_enable_resources */
Index: src/southbridge/intel/i82801gx/i82801gx_lpc.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_lpc.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_lpc.c	(working copy)
@@ -52,16 +52,16 @@
 
 	*ioapic_index = 0;
 	reg32 = *ioapic_data;
-	printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
 	if (reg32 != (1 << 25))
 		die("APIC Error\n");
 
-	printk_spew("Dumping IOAPIC registers\n");
+	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
 	for (i=0; i<3; i++) {
 		*ioapic_index = i;
-		printk_spew("  reg 0x%04x:", i);
+		printk(BIOS_SPEW, "  reg 0x%04x:", i);
 		reg32 = *ioapic_data;
-		printk_spew(" 0x%08x\n", reg32);
+		printk(BIOS_SPEW, " 0x%08x\n", reg32);
 	}
 
 	*ioapic_index = 3; /* Select Boot Configuration register. */
@@ -213,7 +213,7 @@
 	reg8 &= ~(1 << 3);	/* minimum asssertion is 1 to 2 RTCCLK */
 
 	pci_write_config8(dev, GEN_PMCON_3, reg8);
-	printk_info("Set power %s after power failure.\n", state);
+	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 
 	/* Set up NMI on errors. */
 	reg8 = inb(0x61);
@@ -227,10 +227,10 @@
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
-		printk_info ("NMI sources enabled.\n");
+		printk(BIOS_INFO, "NMI sources enabled.\n");
 		reg8 &= ~(1 << 7);	/* Set NMI. */
 	} else {
-		printk_info ("NMI sources disabled.\n");
+		printk(BIOS_INFO, "NMI sources disabled.\n");
 		reg8 |= ( 1 << 7);	/* Can't mask NMI from PCI-E and NMI_NOW */
 	}
 	outb(reg8, 0x70);
@@ -296,7 +296,7 @@
 		reg8 &= ~RTC_BATTERY_DEAD;
 		pci_write_config8(dev, GEN_PMCON_3, reg8);
 	}
-	printk_debug("rtc_failed = 0x%x\n", rtc_failed);
+	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
 	rtc_init(rtc_failed);
 }
@@ -340,13 +340,13 @@
 #endif
 
 #if ENABLE_ACPI_MODE_IN_COREBOOT
-	printk_debug("Enabling ACPI via APMC:\n");
+	printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
 	outb(0xe1, 0xb2); // Enable ACPI mode
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #else
-	printk_debug("Disabling ACPI via APMC:\n");
+	printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
 	outb(0x1e, 0xb2); // Disable ACPI mode
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 	/* Don't allow evil boot loaders, kernels, or
 	 * userspace applications to deceive us:
@@ -355,29 +355,29 @@
 
 #if TEST_SMM_FLASH_LOCKDOWN
 	/* Now try this: */
-	printk_debug("Locking BIOS to RO... ");
+	printk(BIOS_DEBUG, "Locking BIOS to RO... ");
 	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
-	printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 			(reg8&1)?"rw":"ro");
 	reg8 &= ~(1 << 0);			/* clear BIOSWE */
 	pci_write_config8(dev, 0xdc, reg8);
 	reg8 |= (1 << 1);			/* set BLE */
 	pci_write_config8(dev, 0xdc, reg8);
-	printk_debug("ok.\n");
+	printk(BIOS_DEBUG, "ok.\n");
 	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
-	printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 			(reg8&1)?"rw":"ro");
 
-	printk_debug("Writing:\n");
+	printk(BIOS_DEBUG, "Writing:\n");
 	*(volatile u8 *)0xfff00000 = 0x00;
-	printk_debug("Testing:\n");
+	printk(BIOS_DEBUG, "Testing:\n");
 	reg8 |= (1 << 0);			/* set BIOSWE */
 	pci_write_config8(dev, 0xdc, reg8);
 
 	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
-	printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 			(reg8&1)?"rw":"ro");
-	printk_debug("Done.\n");
+	printk(BIOS_DEBUG, "Done.\n");
 #endif
 }
 #endif
@@ -406,7 +406,7 @@
 
 static void lpc_init(struct device *dev)
 {
-	printk_debug("i82801gx: lpc_init\n");
+	printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
 
 	/* Set the value for PCI command register. */
 	pci_write_config16(dev, PCI_COMMAND, 0x000f);
Index: src/southbridge/intel/i82801gx/i82801gx_pcie.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_pcie.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_pcie.c	(working copy)
@@ -28,7 +28,7 @@
 	u16 reg16;
 	u32 reg32;
 
-	printk_debug("Initializing ICH7 PCIe bridge.\n");
+	printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
 
 	/* Enable Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -77,13 +77,13 @@
 
 #ifdef EVEN_MORE_DEBUG
 	reg32 = pci_read_config32(dev, 0x20);
-	printk_spew("    MBL    = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
 	reg32 = pci_read_config32(dev, 0x24);
-	printk_spew("    PMBL   = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
 	reg32 = pci_read_config32(dev, 0x28);
-	printk_spew("    PMBU32 = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
 	reg32 = pci_read_config32(dev, 0x2c);
-	printk_spew("    PMLU32 = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
 #endif
 
 	/* Clear errors in status registers */
Index: src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c	(revision 5263)
+++ src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c	(working copy)
@@ -35,7 +35,7 @@
 	u32 reg32;
 	u8 reg8;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	reg32 |= PCI_COMMAND_MASTER;
 	reg32 |= PCI_COMMAND_SERR;
@@ -61,7 +61,7 @@
 	reg8 |= (1 << 4);
 	pci_write_config8(dev, 0x84, reg8);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/i3100/i3100_sata.c
===================================================================
--- src/southbridge/intel/i3100/i3100_sata.c	(revision 5263)
+++ src/southbridge/intel/i3100/i3100_sata.c	(working copy)
@@ -53,7 +53,7 @@
 	ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
 
 	/* Enable SATA devices */
-	printk_info("SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
+	printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
 
 	if(ahci) {
 	  /* AHCI mode */
@@ -97,7 +97,7 @@
 	  pci_write_config8(dev, SATA_PCS + 1, 0x0f);
 	  
 	}
-	printk_debug("SATA Enabled\n");
+	printk(BIOS_DEBUG, "SATA Enabled\n");
 }
 
 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Index: src/southbridge/intel/i3100/i3100_pciexp_portb.c
===================================================================
--- src/southbridge/intel/i3100/i3100_pciexp_portb.c	(revision 5263)
+++ src/southbridge/intel/i3100/i3100_pciexp_portb.c	(working copy)
@@ -46,12 +46,12 @@
 	int flag = 0;
 	do {
 		val = pci_read_config16(dev, PCIE_LSTS);
-		printk_debug("pcie portb link status: %02x\n", val);
+		printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val);
 		if ((val & (1<<10)) && (!flag)) { /* training error */
 			ctl = pci_read_config16(dev, PCIE_LCTL);
 			pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
 			val = pci_read_config16(dev, PCIE_LSTS);
-			printk_debug("pcie portb reset link status: %02x\n", val);
+			printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val);
 			flag=1;
 			hard_reset();
 		}
Index: src/southbridge/intel/i3100/i3100_lpc.c
===================================================================
--- src/southbridge/intel/i3100/i3100_lpc.c	(revision 5263)
+++ src/southbridge/intel/i3100/i3100_lpc.c	(working copy)
@@ -232,7 +232,7 @@
   /* minimum asssertion is 1 to 2 RTCCLK */
   reg8 &= ~(1 << 3);	
   pci_write_config8(dev, GEN_PMCON_3, reg8);
-  printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");  
+  printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");  
 
   /* Set up NMI on errors. */
   reg8 = inb(0x61);
@@ -251,11 +251,11 @@
   get_option(&nmi_option, "nmi");
   if (nmi_option) {
     /* Set NMI. */
-    printk_info ("NMI sources enabled.\n");
+    printk(BIOS_INFO, "NMI sources enabled.\n");
     reg8 &= ~(1 << 7);	
   } else {
     /* Can't mask NMI from PCI-E and NMI_NOW */
-    printk_info ("NMI sources disabled.\n");
+    printk(BIOS_INFO, "NMI sources disabled.\n");
     reg8 |= ( 1 << 7);
   }
   outb(reg8, 0x70);
Index: src/southbridge/ti/pci7420/pci7420_firewire.c
===================================================================
--- src/southbridge/ti/pci7420/pci7420_firewire.c	(revision 5263)
+++ src/southbridge/ti/pci7420/pci7420_firewire.c	(working copy)
@@ -32,7 +32,7 @@
 {
 	u8 reg8;
 
-	printk_debug("TI PCI7420/7620 FireWire init\n");
+	printk(BIOS_DEBUG, "TI PCI7420/7620 FireWire init\n");
 
 #ifdef ODD_IRQ_FIXUP
 	/* This is a workaround for buggy kernels. This should
Index: src/southbridge/ti/pci7420/pci7420_cardbus.c
===================================================================
--- src/southbridge/ti/pci7420/pci7420_cardbus.c	(revision 5263)
+++ src/southbridge/ti/pci7420/pci7420_cardbus.c	(working copy)
@@ -41,10 +41,10 @@
 	struct southbridge_ti_pci7420_config *config = dev->chip_info;
 	int smartcard_enabled = 0;
 
-	printk_debug("TI PCI7420/7620 init\n");
+	printk(BIOS_DEBUG, "TI PCI7420/7620 init\n");
 
 	if (!config) {
-		printk_debug("PCI7420: No configuration found.\n");
+		printk(BIOS_DEBUG, "PCI7420: No configuration found.\n");
 	} else {
 		smartcard_enabled = config->smartcard_enabled;
 	}
@@ -90,11 +90,11 @@
 
 void pci7420_cardbus_set_resources(device_t dev)
 {
-	printk_debug("%s In set resources \n",dev_path(dev));
+	printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
 
 	pci_dev_set_resources(dev);
 
-	printk_debug("%s done set resources \n",dev_path(dev));
+	printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev));
 }
 
 static struct device_operations ti_pci7420_ops = {
Index: src/southbridge/sis/sis966/sis966_usb2.c
===================================================================
--- src/southbridge/sis/sis966/sis966_usb2.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis966_usb2.c	(working copy)
@@ -95,7 +95,7 @@
                 return;
 
         base =(uint8_t *) res->base;
-        printk_debug("base = %08x\n", base);
+        printk(BIOS_DEBUG, "base = %08x\n", base);
         write32(base+0x20, 0x2);
 //-----------------------------------------------------------
 
Index: src/southbridge/sis/sis966/sis966_aza.c
===================================================================
--- src/southbridge/sis/sis966/sis966_aza.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis966_aza.c	(working copy)
@@ -101,23 +101,23 @@
 	int idx=0;
 
 	/* 1 */ // controller reset
-	printk_debug("controller reset\n");
+	printk(BIOS_DEBUG, "controller reset\n");
 
 	set_bits(base + 0x08, 1, 1);
 
       do{
 	  	dword = read32(base + 0x08)&0x1;
-		if(idx++>1000) { printk_debug("controller reset fail !!! \n"); break;}
+		if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!! \n"); break;}
 	   } while (dword !=1);
 
        dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
 
        if(dword==0) {
-	   	printk_debug("No codec!\n");
+	   	printk(BIOS_DEBUG, "No codec!\n");
 		return 0;
        }
 
-	 printk_debug("Codec ID = %lx\n", dword);
+	 printk(BIOS_DEBUG, "Codec ID = %lx\n", dword);
 
        dword=0x1;
 	return dword;
@@ -219,20 +219,20 @@
 	dword = read32(base + 0x64);
 
 	/* 2 */
-	printk_debug("codec viddid: %08x\n", dword);
+	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
 	verb_size = find_verb(dword, &verb);
 
 	if(!verb_size) {
-		printk_debug("No verb!\n");
+		printk(BIOS_DEBUG, "No verb!\n");
 		return;
 	}
 
-	printk_debug("verb_size: %d\n", verb_size);
+	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
 	/* 3 */
 	for(i=0; i<verb_size; i++) {
 		send_verb(base,verb[i]);
 	}
-	printk_debug("verb loaded!\n");
+	printk(BIOS_DEBUG, "verb loaded!\n");
 }
 
 static void codecs_init(uint8_t *base, uint32_t codec_mask)
@@ -293,12 +293,12 @@
 		return;
 
 	base =(uint8_t *) res->base;
-	printk_debug("base = %08x\n", base);
+	printk(BIOS_DEBUG, "base = %08x\n", base);
 
 	codec_mask = codec_detect(base);
 
 	if(codec_mask) {
-		printk_debug("codec_mask = %02x\n", codec_mask);
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
 		codecs_init(base, codec_mask);
 	}
 
Index: src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- src/southbridge/sis/sis966/sis966_lpc.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis966_lpc.c	(working copy)
@@ -92,7 +92,7 @@
 	 int on;
 	 int nmi_option;
 
-        printk_debug("LPC_INIT -------->\n");
+        printk(BIOS_DEBUG, "LPC_INIT -------->\n");
         pc_keyboard_init(0);
 
         lpc_usb_legacy_init(dev);
@@ -109,7 +109,7 @@
 		byte |= 0x40;
 	}
 	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
-	printk_info("set power %s after power fail\n", on?"on":"off");
+	printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
 
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
@@ -121,7 +121,7 @@
 		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 		dword = inl(pm10_bar + 0x10);
 		on = 8-on;
-		printk_debug("Throttling CPU %2d.%1.1d percent.\n",
+		printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 				(on*12)+(on>>1),(on&1)*5);
 	}
 
@@ -151,7 +151,7 @@
         /* Initialize isa dma */
         isa_dma_init();
 
-        printk_debug("LPC_INIT <--------\n");
+        printk(BIOS_DEBUG, "LPC_INIT <--------\n");
 }
 
 static void sis966_lpc_read_resources(device_t dev)
@@ -214,7 +214,7 @@
 					if(!(res->flags & IORESOURCE_IO)) continue;
 					base = res->base;
 					end = resource_end(res);
-					printk_debug("sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
+					printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 					switch(base) {
 					case 0x3f8: // COM1
 						reg |= (1<<0);	break;
Index: src/southbridge/sis/sis966/sis966_early_smbus.c
===================================================================
--- src/southbridge/sis/sis966/sis966_early_smbus.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis966_early_smbus.c	(working copy)
@@ -481,23 +481,23 @@
 
 // ========================== NB =============================
 
-        printk_debug("Init NorthBridge sis761 -------->\n");
+        printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
         msr = rdmsr(0xC001001A);
-	 printk_debug("Memory Top Bound %lx\n",msr.lo );
+	 printk(BIOS_DEBUG, "Memory Top Bound %lx\n",msr.lo );
 
         temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
         temp16=0x0001<<(temp16-1);
         temp16<<=8;
 
-        printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
+        printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
         pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
         pci_write_config8(dev, 0x7F, 0x08);									// ACPI Base
         outb(inb(0x856) | 0x40, 0x856);										// Auto-Reset Function
 
 // ========================== ACPI =============================
 	i=0;
-	printk_debug("Init ACPI -------->\n");
+	printk(BIOS_DEBUG, "Init ACPI -------->\n");
 	do
 	{				temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
 					temp8 &= SiS_ACPI_2_init[i][1];
@@ -507,7 +507,7 @@
 	}while(SiS_ACPI_2_init[i][0] != 0);
 
 // ========================== Misc =============================
-       printk_debug("Init Misc -------->\n");
+       printk(BIOS_DEBUG, "Init Misc -------->\n");
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 
 	/* R77h Internal PCI Device Enable 1 (Power On Value = 0h)
@@ -533,7 +533,7 @@
 	pci_write_config8(dev, 0x7E, 0x00);  // azalia controller enable
 	temp8=inb(0x878)|0x4;   //bit2=1 enable Azalia  =0 enable AC97
 	outb(temp8, 0x878);  // ACPI select AC97 or HDA controller
-	printk_debug("Audio select %x\n",inb(0x878));
+	printk(BIOS_DEBUG, "Audio select %x\n",inb(0x878));
 
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0);
 
@@ -550,7 +550,7 @@
 {
 	device_t dev;
 	uint8_t temp8;
-	printk_debug("enable_smbus -------->\n");
+	printk(BIOS_DEBUG, "enable_smbus -------->\n");
 
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 
@@ -561,7 +561,7 @@
 	temp8=pci_read_config8(dev, 0x76);					// Enable SMBUS
 	pci_write_config8(dev, 0x76, temp8 | 0x03);
 
-	printk_debug("enable_smbus <--------\n");
+	printk(BIOS_DEBUG, "enable_smbus <--------\n");
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)
Index: src/southbridge/sis/sis966/sis966_sata.c
===================================================================
--- src/southbridge/sis/sis966/sis966_sata.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis966_sata.c	(working copy)
@@ -141,7 +141,7 @@
    temp32=0;
    temp32= pci_read_config32(dev, 0xC0);
    for ( j=0;j<0xFFFF;j++);
-   printk_debug("status= %x\n",temp32);
+   printk(BIOS_DEBUG, "status= %x\n",temp32);
    if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
 }
 
Index: src/southbridge/sis/sis966/sis966_ide.c
===================================================================
--- src/southbridge/sis/sis966/sis966_ide.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis966_ide.c	(working copy)
@@ -123,12 +123,12 @@
 	if (conf->ide1_enable) {
 		/* Enable secondary ide interface */
 		word |= (1<<0);
-		printk_debug("IDE1 \t");
+		printk(BIOS_DEBUG, "IDE1 \t");
 	}
 	if (conf->ide0_enable) {
 		/* Enable primary ide interface */
 		word |= (1<<1);
-		printk_debug("IDE0\n");
+		printk(BIOS_DEBUG, "IDE0\n");
 	}
 
 	word |= (1<<12);
Index: src/southbridge/sis/sis966/sis761.c
===================================================================
--- src/southbridge/sis/sis966/sis761.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis761.c	(working copy)
@@ -72,27 +72,27 @@
 static void sis761_read_resources(device_t dev)
 {
 	/* Read the generic PCI resources */
-	printk_debug("sis761_read_resources ------->\n");
+	printk(BIOS_DEBUG, "sis761_read_resources ------->\n");
 	pci_dev_read_resources(dev);
 
 	/* If we are not the first processor don't allocate the gart apeture */
 	if (dev->path.pci.devfn != PCI_DEVFN(0x0, 0)) {
-		printk_debug("sis761_not_the_first_processor !!!\n");
+		printk(BIOS_DEBUG, "sis761_not_the_first_processor !!!\n");
 		return;
 	}
 
-	printk_debug("sis761_read_resources <-------\n");
+	printk(BIOS_DEBUG, "sis761_read_resources <-------\n");
 	return;
 
 }
 
 static void sis761_set_resources(device_t dev)
 {
-	printk_debug("sis761_set_resources ------->\n");
+	printk(BIOS_DEBUG, "sis761_set_resources ------->\n");
 
 	/* Set the generic PCI resources */
 	pci_dev_set_resources(dev);
-	printk_debug("sis761_set_resources <-------\n");
+	printk(BIOS_DEBUG, "sis761_set_resources <-------\n");
 }
 
 static void sis761_init(struct device *dev)
@@ -102,14 +102,14 @@
 
 
 	needs_reset = 0;
-	printk_debug("sis761_init: ---------->\n");
+	printk(BIOS_DEBUG, "sis761_init: ---------->\n");
 
 	msr = rdmsr(0xC001001A);
 	pci_write_config16(dev, 0x8E, msr.lo >> 16);				// Topbound
 	pci_write_config8(dev, 0x7F, 0x08);			// ACPI Base
 	outb(inb(0x856) | 0x40, 0x856);	 // Auto-Reset Function
 
-	printk_debug("sis761_init: <----------\n");
+	printk(BIOS_DEBUG, "sis761_init: <----------\n");
 }
 
 
Index: src/southbridge/sis/sis966/sis966_nic.c
===================================================================
--- src/southbridge/sis/sis966/sis966_nic.c	(revision 5263)
+++ src/southbridge/sis/sis966/sis966_nic.c	(working copy)
@@ -75,12 +75,12 @@
     outl(0x80001048,0xcf8);
     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
 
-    printk_debug("MAC addr in APC = ");
+    printk(BIOS_DEBUG, "MAC addr in APC = ");
     for(i = 0x9 ; i <=0xe ; i++)
     {
-        printk_debug("%2.2x",readApcByte(i));
+        printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
     }
-    printk_debug("\n");
+    printk(BIOS_DEBUG, "\n");
 
     /* Set APC Reload */
     writeApcByte(0x7,readApcByte(0x7)&0xf7);
@@ -192,7 +192,7 @@
 		   mdelay(20);
     	       ulValue = read32(base+0x44);
            } while((ulValue & SMI_REQUEST) != 0);
-            //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
+            //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
            usData=(ulValue>>16);
 
 
@@ -227,7 +227,7 @@
 
 	if(!bFoundPhy)
 	{
-	    printk_debug("PHY not found !!!! \n");
+	    printk(BIOS_DEBUG, "PHY not found !!!! \n");
 	}
 
        *PhyAddr=PhyAddress;
@@ -270,15 +270,15 @@
 
 	if(!res)
 	{
-		printk_debug("NIC Cannot find resource..\r\n");
+		printk(BIOS_DEBUG, "NIC Cannot find resource..\r\n");
 		return;
 	}
 	base = res->base;
-        printk_debug("NIC base address %lx\n",base);
+        printk(BIOS_DEBUG, "NIC base address %lx\n",base);
 
 	if(!(val=phy_detect(base,&PhyAddr)))
 	{
-	       printk_debug("PHY detect fail !!!!\r\n");
+	       printk(BIOS_DEBUG, "PHY detect fail !!!!\r\n");
 		return;
 	}
 
@@ -291,7 +291,7 @@
 
           //	if that is valid we will use that
 
-			printk_debug("EEPROM contents %x \n",ReadEEprom( dev,  base,  0LL));
+			printk(BIOS_DEBUG, "EEPROM contents %x \n",ReadEEprom( dev,  base,  0LL));
 			for(i=0;i<3;i++) {
 				//status = smbus_read_byte(dev_eeprom, i);
 				ulValue=ReadEEprom( dev,  base,  i+3L);
@@ -302,7 +302,7 @@
 			}
         }else{
                  // read MAC address from firmware
-		 printk_debug("EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
+		 printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
 		 MacAddr[0]=read16(0xffffffc0); // mac address store at here
 		 MacAddr[1]=read16(0xffffffc2);
 		 MacAddr[2]=read16(0xffffffc4);
Index: src/devices/device.c
===================================================================
--- src/devices/device.c	(revision 5263)
+++ src/devices/device.c	(working copy)
@@ -129,7 +129,7 @@
 {
 	struct device *curdev;
 
-	printk_spew("%s %s bus %x link: %d\n", dev_path(bus->dev), __func__,
+	printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev), __func__,
 		    bus->secondary, bus->link);
 
 	/* Walk through all devices and find which resources they need. */
@@ -139,7 +139,7 @@
 			continue;
 		}
 		if (!curdev->ops || !curdev->ops->read_resources) {
-			printk_err("%s missing read_resources\n",
+			printk(BIOS_ERR, "%s missing read_resources\n",
 				   dev_path(curdev));
 			continue;
 		}
@@ -149,7 +149,7 @@
 		for (i = 0; i < curdev->links; i++)
 			read_resources(&curdev->link[i]);
 	}
-	printk_spew("%s read_resources bus %d link: %d done\n",
+	printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n",
 		    dev_path(bus->dev), bus->secondary, bus->link);
 }
 
@@ -245,7 +245,7 @@
 	resource_t base;
 	base = round(bridge->base, bridge->align);
 
-	printk_spew( "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx\n",
+	printk(BIOS_SPEW,  "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx\n",
 	       dev_path(bus->dev), __func__,
 	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
 	       "prefmem" : "mem",
@@ -309,8 +309,8 @@
 		/* Warn if it looks like APICs aren't declared. */
 		if ((resource->limit == 0xffffffff) &&
 		    (resource->flags & IORESOURCE_ASSIGNED)) {
-			printk_err("Resource limit looks wrong! (no APIC?)\n");
-			printk_err("%s %02lx limit %08Lx\n", dev_path(dev),
+			printk(BIOS_ERR, "Resource limit looks wrong! (no APIC?)\n");
+			printk(BIOS_ERR, "%s %02lx limit %08Lx\n", dev_path(dev),
 			           resource->index, resource->limit);
 		}
 
@@ -336,7 +336,7 @@
 		resource->base = base;
 		base += resource->size;
 
-		printk_spew("%s %02lx *  [0x%llx - 0x%llx] %s\n",
+		printk(BIOS_SPEW, "%s %02lx *  [0x%llx - 0x%llx] %s\n",
 			    dev_path(dev), resource->index,
 			    resource->base,
 			    resource->base + resource->size - 1,
@@ -353,7 +353,7 @@
 	bridge->size = round(base, bridge->gran) -
 		       round(bridge->base, bridge->align);
 
-	printk_spew("%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n",
+	printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n",
 		    dev_path(bus->dev), __func__,
 		    (bridge->flags & IORESOURCE_IO) ? "io" :
 		     (bridge->flags & IORESOURCE_PREFETCH) ?  "prefmem" : "mem",
@@ -402,7 +402,7 @@
 	resource_t base;
 	base = bridge->base;
 
-	printk_spew("%s %s_%s: base:%llx size:%llx align:%d gran:%d limit:%llx\n",
+	printk(BIOS_SPEW, "%s %s_%s: base:%llx size:%llx align:%d gran:%d limit:%llx\n",
 	       dev_path(bus->dev), __func__,
 	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
 	       "prefmem" : "mem",
@@ -456,14 +456,14 @@
 			resource->flags &= ~IORESOURCE_STORED;
 			base += resource->size;
 		} else {
-			printk_err("!! Resource didn't fit !!\n");
-			printk_err("   aligned base %llx size %llx limit %llx\n",
+			printk(BIOS_ERR, "!! Resource didn't fit !!\n");
+			printk(BIOS_ERR, "   aligned base %llx size %llx limit %llx\n",
 			       round(base, resource->align), resource->size,
 			       resource->limit);
-			printk_err("   %llx needs to be <= %llx (limit)\n",
+			printk(BIOS_ERR, "   %llx needs to be <= %llx (limit)\n",
 			       (round(base, resource->align) +
 				resource->size) - 1, resource->limit);
-			printk_err("   %s%s %02lx *  [0x%llx - 0x%llx] %s\n",
+			printk(BIOS_ERR, "   %s%s %02lx *  [0x%llx - 0x%llx] %s\n",
 			       (resource->
 				flags & IORESOURCE_ASSIGNED) ? "Assigned: " :
 			       "", dev_path(dev), resource->index,
@@ -476,7 +476,7 @@
 			       ? "prefmem" : "mem");
 		}
 
-		printk_spew("%s%s %02lx *  [0x%llx - 0x%llx] %s\n",
+		printk(BIOS_SPEW, "%s%s %02lx *  [0x%llx - 0x%llx] %s\n",
 		       (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: "
 		       : "",
 		       dev_path(dev), resource->index, resource->base,
@@ -494,7 +494,7 @@
 
 	bridge->flags |= IORESOURCE_ASSIGNED;
 
-	printk_spew("%s %s_%s: next_base: %llx size: %llx align: %d gran: %d done\n",
+	printk(BIOS_SPEW, "%s %s_%s: next_base: %llx size: %llx align: %d gran: %d done\n",
 	       dev_path(bus->dev), __func__,
 	       (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
 	       "prefmem" : "mem",
@@ -553,7 +553,7 @@
 	struct resource *lim;
 	int i;
 
-	printk_spew("%s: %s\n", __func__, dev_path(dev));
+	printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev));
 
 	/* Constrain limits based on the fixed resources of this device. */
 	for (i = 0; i < dev->resources; i++) {
@@ -562,7 +562,7 @@
 			continue;
 		if (!res->size) {
 			/* It makes no sense to have 0-sized, fixed resources.*/
-			printk_err("skipping %s@%lx fixed resource, size=0!\n",
+			printk(BIOS_ERR, "skipping %s@%lx fixed resource, size=0!\n",
 				   dev_path(dev), res->index);
 			continue;
 		}
@@ -606,7 +606,7 @@
 	struct resource *res;
 	int i;
 
-	printk_spew("%s: %s\n", __func__, dev_path(dev));
+	printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev));
 	/* Initialize constraints to maximum size. */
 
 	limits.pref.base = 0;
@@ -621,7 +621,7 @@
 		res = &dev->resource[i];
 		if ((res->flags & IORESOURCE_FIXED))
 			continue;
-		printk_spew("%s:@%s %02lx limit %08Lx\n", __func__,
+		printk(BIOS_SPEW, "%s:@%s %02lx limit %08Lx\n", __func__,
 			     dev_path(dev), res->index, res->limit);
 		if ((res->flags & MEM_MASK) == PREF_TYPE &&
 		    (res->limit < limits.pref.limit))
@@ -655,9 +655,9 @@
 		else
 			continue;
 
-		printk_spew("%s2: %s@%02lx limit %08Lx\n", __func__,
+		printk(BIOS_SPEW, "%s2: %s@%02lx limit %08Lx\n", __func__,
 			     dev_path(dev), res->index, res->limit);
-		printk_spew("\tlim->base %08Lx lim->limit %08Lx\n",
+		printk(BIOS_SPEW, "\tlim->base %08Lx lim->limit %08Lx\n",
 			     lim->base, lim->limit);
 
 		/* Is the resource outside the limits? */
@@ -726,7 +726,7 @@
 
 	if (vga) {
 		/* VGA is first add on card or the only onboard VGA. */
-		printk_debug("Setting up VGA for %s\n", dev_path(vga));
+		printk(BIOS_DEBUG, "Setting up VGA for %s\n", dev_path(vga));
 		/* All legacy VGA cards have MEM & I/O space registers. */
 		vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 		vga_pri = vga;
@@ -734,7 +734,7 @@
 	}
 	/* Now walk up the bridges setting the VGA enable. */
 	while (bus) {
-		printk_debug("Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
+		printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
 			     dev_path(bus->dev));
 		bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
 		bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
@@ -760,7 +760,7 @@
 {
 	struct device *curdev;
 
-	printk_spew("%s assign_resources, bus %d link: %d\n",
+	printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
 		    dev_path(bus->dev), bus->secondary, bus->link);
 
 	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
@@ -768,13 +768,13 @@
 			continue;
 		}
 		if (!curdev->ops || !curdev->ops->set_resources) {
-			printk_err("%s missing set_resources\n",
+			printk(BIOS_ERR, "%s missing set_resources\n",
 				   dev_path(curdev));
 			continue;
 		}
 		curdev->ops->set_resources(curdev);
 	}
-	printk_spew("%s assign_resources, bus %d link: %d\n",
+	printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
 		    dev_path(bus->dev), bus->secondary, bus->link);
 }
 
@@ -802,7 +802,7 @@
 		return;
 	}
 	if (!dev->ops || !dev->ops->enable_resources) {
-		printk_err("%s missing enable_resources\n", dev_path(dev));
+		printk(BIOS_ERR, "%s missing enable_resources\n", dev_path(dev));
 		return;
 	}
 	dev->ops->enable_resources(dev);
@@ -891,22 +891,22 @@
 void dev_enumerate(void)
 {
 	struct device *root;
-	printk_info("Enumerating buses...\n");
+	printk(BIOS_INFO, "Enumerating buses...\n");
 	root = &dev_root;
 
 	show_all_devs(BIOS_SPEW, "Before Device Enumeration.");
-	printk_spew("Compare with tree...\n");
+	printk(BIOS_SPEW, "Compare with tree...\n");
 	show_devs_tree(root, BIOS_SPEW, 0, 0);
 
 	if (root->chip_ops && root->chip_ops->enable_dev) {
 		root->chip_ops->enable_dev(root);
 	}
 	if (!root->ops || !root->ops->scan_bus) {
-		printk_err("dev_root missing scan_bus operation");
+		printk(BIOS_ERR, "dev_root missing scan_bus operation");
 		return;
 	}
 	scan_bus(root, 0);
-	printk_info("done\n");
+	printk(BIOS_INFO, "done\n");
 }
 
 /**
@@ -933,7 +933,7 @@
 	set_vga_bridge_bits();
 #endif
 
-	printk_info("Allocating resources...\n");
+	printk(BIOS_INFO, "Allocating resources...\n");
 
 	root = &dev_root;
 
@@ -944,9 +944,9 @@
 
 	/* Read the resources for the entire tree. */
 
-	printk_info("Reading resources...\n");
+	printk(BIOS_INFO, "Reading resources...\n");
 	read_resources(&root->link[0]);
-	printk_info("Done reading resources.\n");
+	printk(BIOS_INFO, "Done reading resources.\n");
 
 	print_resource_tree(root, BIOS_SPEW, "After reading.");
 
@@ -997,7 +997,7 @@
 	}
 
 	/* Store the computed resource allocations into device registers ... */
-	printk_info("Setting resources...\n");
+	printk(BIOS_INFO, "Setting resources...\n");
 	for (child = root->link[0].children; child; child = child->sibling) {
 		if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
 			continue;
@@ -1023,10 +1023,10 @@
 		}
 	}
 	assign_resources(&root->link[0]);
-	printk_info("Done setting resources.\n");
+	printk(BIOS_INFO, "Done setting resources.\n");
 	print_resource_tree(root, BIOS_SPEW, "After assigning values.");
 
-	printk_info("Done allocating resources.\n");
+	printk(BIOS_INFO, "Done allocating resources.\n");
 }
 
 /**
@@ -1037,12 +1037,12 @@
  */
 void dev_enable(void)
 {
-	printk_info("Enabling resources...\n");
+	printk(BIOS_INFO, "Enabling resources...\n");
 
 	/* now enable everything. */
 	enable_resources(&dev_root);
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 }
 
 /**
@@ -1056,20 +1056,20 @@
 {
 	struct device *dev;
 
-	printk_info("Initializing devices...\n");
+	printk(BIOS_INFO, "Initializing devices...\n");
 	for (dev = all_devices; dev; dev = dev->next) {
 		if (dev->enabled && !dev->initialized &&
 		    dev->ops && dev->ops->init) {
 			if (dev->path.type == DEVICE_PATH_I2C) {
-				printk_debug("smbus: %s[%d]->",
+				printk(BIOS_DEBUG, "smbus: %s[%d]->",
 					     dev_path(dev->bus->dev),
 					     dev->bus->link);
 			}
-			printk_debug("%s init\n", dev_path(dev));
+			printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
 			dev->initialized = 1;
 			dev->ops->init(dev);
 		}
 	}
-	printk_info("Devices initialized\n");
+	printk(BIOS_INFO, "Devices initialized\n");
 	show_all_devs(BIOS_SPEW, "After init.");
 }
Index: src/devices/root_device.c
===================================================================
--- src/devices/root_device.c	(revision 5263)
+++ src/devices/root_device.c	(working copy)
@@ -34,7 +34,7 @@
  */
 void root_dev_read_resources(device_t root)
 {
-	printk_err("%s should never be called.\n", __func__);
+	printk(BIOS_ERR, "%s should never be called.\n", __func__);
 }
 
 /**
@@ -46,7 +46,7 @@
  */
 void root_dev_set_resources(device_t root)
 {
-	printk_err("%s should never be called.\n", __func__);
+	printk(BIOS_ERR, "%s should never be called.\n", __func__);
 }
 
 /**
@@ -77,7 +77,7 @@
 	device_t child;
 	unsigned link;
 
-	printk_spew("%s for %s\n", __func__, dev_path(bus));
+	printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));
 
 	for(link = 0; link < bus->links; link++) {
 		/* for smbus bus enumerate */
@@ -93,10 +93,10 @@
 				child->ops->enable(child);
 			}
  			if (child->path.type == DEVICE_PATH_I2C) {
- 				printk_debug("smbus: %s[%d]->",  
+ 				printk(BIOS_DEBUG, "smbus: %s[%d]->",  
 					dev_path(child->bus->dev), child->bus->link );
 			}
-			printk_debug("%s %s\n",
+			printk(BIOS_DEBUG, "%s %s\n",
 				dev_path(child),
 				child->enabled?"enabled": "disabled");
 		}
@@ -105,12 +105,12 @@
 		for(child = bus->link[link].children; child; child = child->sibling) {
 			if (!child->ops || !child->ops->scan_bus)
 				continue;
-			printk_spew("%s scanning...\n", dev_path(child));
+			printk(BIOS_SPEW, "%s scanning...\n", dev_path(child));
 			max = scan_bus(child, max);
 		}
 	}
 
-	printk_spew("%s for %s done\n", __func__, dev_path(bus));
+	printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus));
 
 	return max;
 }
@@ -163,7 +163,7 @@
 
 void root_dev_reset(struct bus *bus)
 {
-	printk_info("Reseting board...\n");
+	printk(BIOS_INFO, "Reseting board...\n");
 	hard_reset();
 }
 
Index: src/devices/cardbus_device.c
===================================================================
--- src/devices/cardbus_device.c	(revision 5263)
+++ src/devices/cardbus_device.c	(working copy)
@@ -166,7 +166,7 @@
 			PCI_BRIDGE_CTL_MASTER_ABORT |
 			PCI_BRIDGE_CTL_BUS_RESET));
 	ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); /* error check */
-	printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+	printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
 	pci_dev_enable_resources(dev);
@@ -188,7 +188,7 @@
 	uint32_t buses;
 	uint16_t cr;
 
-	printk_spew("%s for %s\n", __func__, dev_path(dev));
+	printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
 
 	bus = &dev->link[0];
 	bus->dev = dev;
@@ -236,7 +236,7 @@
 	pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses);
 	pci_write_config16(dev, PCI_COMMAND, cr);
 	
-	printk_spew("%s returns max %d\n", __func__, max);
+	printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
 	return max;
 }
 
Index: src/devices/hypertransport.c
===================================================================
--- src/devices/hypertransport.c	(revision 5263)
+++ src/devices/hypertransport.c	(working copy)
@@ -192,11 +192,11 @@
 		unsigned new_freq;
 		pci_write_config8(cur->dev, cur->pos + cur->freq_off, freq);
 		reset_needed = 1;
-		printk_spew("HyperT FreqP old %x new %x\n",old_freq,freq);
+		printk(BIOS_SPEW, "HyperT FreqP old %x new %x\n",old_freq,freq);
 		new_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
 		new_freq &= 0x0f;
 		if (new_freq != freq) {
-			printk_err("%s Hypertransport frequency would not set wanted: %x got: %x\n",
+			printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
 				dev_path(dev), freq, new_freq);
 		}
 	}
@@ -206,10 +206,10 @@
 		pci_write_config8(cur->dev, cur->pos + cur->config_off + 1,
 			present_width);
 		reset_needed = 1;
-		printk_spew("HyperT widthP old %x new %x\n",old_width, present_width);
+		printk(BIOS_SPEW, "HyperT widthP old %x new %x\n",old_width, present_width);
 		new_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
 		if (new_width != present_width) {
-			printk_err("%s Hypertransport width would not set wanted: %x got: %x\n",
+			printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
 				dev_path(dev), present_width, new_width);
 		}
 	}
@@ -221,11 +221,11 @@
 		unsigned new_freq;
 		pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
 		reset_needed = 1;
-		printk_spew("HyperT freqU old %x new %x\n", old_freq, freq);
+		printk(BIOS_SPEW, "HyperT freqU old %x new %x\n", old_freq, freq);
 		new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
 		new_freq &= 0x0f;
 		if (new_freq != freq) {
-			printk_err("%s Hypertransport frequency would not set wanted: %x got: %x\n",
+			printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
 				dev_path(prev->dev), freq, new_freq);
 		}
 	}
@@ -234,10 +234,10 @@
 		unsigned new_width;
 		pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
 		reset_needed = 1;
-		printk_spew("HyperT widthU old %x new %x\n", old_width, upstream_width);
+		printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width, upstream_width);
 		new_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
 		if (new_width != upstream_width) {
-			printk_err("%s Hypertransport width would not set wanted: %x got: %x\n",
+			printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
 				dev_path(prev->dev), upstream_width, new_width);
 		}
 	}
@@ -273,7 +273,7 @@
 		if (pos) {
 			unsigned flags;
 			flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
-			printk_spew("flags: 0x%04x\n", flags);
+			printk(BIOS_SPEW, "flags: 0x%04x\n", flags);
 			if ((flags >> 13) == 0) {
 				/* Entry is a Slave secondary, success... */
 				break;
@@ -317,7 +317,7 @@
 			pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
 			ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
 			if (ctrl & ((1 << 4) | (1 << 8))) {
-				printk_alert("Detected error on Hypertransport Link\n");
+				printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
 				return;
 			}
 		}
@@ -371,7 +371,7 @@
 		flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
 		flags &= ~0x1f;
 		pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
-		printk_spew("Collapsing %s [%04x/%04x]\n", 
+		printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", 
 			dev_path(&dummy), dummy.vendor, dummy.device);
 	}
 }
@@ -441,7 +441,7 @@
 				pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
 				ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
 				if (ctrl & ((1 << 4) | (1 << 8))) {
-					printk_alert("Detected error on Hypertransport Link\n");
+					printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
 					goto end_of_chain;
 				}
 			}
@@ -462,7 +462,7 @@
 		/* Find the hypertransport link capability */
 		pos = ht_lookup_slave_capability(dev);
 		if (pos == 0) {
-			printk_err("%s Hypertransport link capability not found", 
+			printk(BIOS_ERR, "%s Hypertransport link capability not found", 
 				dev_path(dev));
 			break;
 		}
@@ -507,7 +507,7 @@
 			last_func = func;
 		}
 		/* Compute the number of unitids consumed */
-		printk_spew("%s count: %04x static_count: %04x\n", 
+		printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", 
 			dev_path(dev), count, static_count);
 		if (count < static_count) {
 			count = static_count;
@@ -532,7 +532,7 @@
 		/* Setup the hypetransport link */
 		bus->reset_needed |= ht_setup_link(&prev, dev, pos);
 
-		printk_debug("%s [%04x/%04x] %s next_unitid: %04x\n",
+		printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
 			dev_path(dev),
 			dev->vendor, dev->device, 
 			(dev->enabled? "enabled": "disabled"), next_unitid);
@@ -541,10 +541,10 @@
  end_of_chain:
 #if OPT_HT_LINK == 1
 	if(bus->reset_needed) {
-		printk_info("HyperT reset needed\n");
+		printk(BIOS_INFO, "HyperT reset needed\n");
 	}
 	else {
-		printk_debug("HyperT reset not needed\n");
+		printk(BIOS_DEBUG, "HyperT reset not needed\n");
 	}
 #endif
 
@@ -563,7 +563,7 @@
 
 		ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one
 		
-		printk_debug(" unitid: %04x --> %04x\n",
+		printk(BIOS_DEBUG, " unitid: %04x --> %04x\n",
 				real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
 
         }
@@ -583,9 +583,9 @@
 	if(old_devices) {
 		device_t left;
 		for(left = old_devices; left; left = left->sibling) {
-			printk_debug("%s\n", dev_path(left));
+			printk(BIOS_DEBUG, "%s\n", dev_path(left));
 		}
-		printk_err("HT: Left over static devices.  Check your Config.lb\n");
+		printk(BIOS_ERR, "HT: Left over static devices.  Check your Config.lb\n");
 		if(last_func  && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it
 			last_func->sibling = old_devices; 
 	}
Index: src/devices/pciexp_device.c
===================================================================
--- src/devices/pciexp_device.c	(revision 5263)
+++ src/devices/pciexp_device.c	(working copy)
@@ -35,7 +35,7 @@
 		return;
 	}
 #ifdef CONFIG_PCIE_TUNING
-	printk_debug("PCIe: tuning %s\n", dev_path(dev));
+	printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
 
 	// TODO make this depending on ASPM
 	/* Enable ASPM Role Based Error Reporting */
Index: src/devices/smbus_ops.c
===================================================================
--- src/devices/smbus_ops.c	(revision 5263)
+++ src/devices/smbus_ops.c	(working copy)
@@ -32,7 +32,7 @@
 		pbus = pbus->dev->bus;
 	}
 	if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_smbus_bus) {
-		printk_alert("%s Cannot find smbus bus operations", dev_path(dev));
+		printk(BIOS_ALERT, "%s Cannot find smbus bus operations", dev_path(dev));
 		die("");
 	}
 	return pbus;
@@ -53,15 +53,15 @@
 		pbus_a[pbus_num++] = pbus;
                 pbus = pbus->dev->bus;
         }
-//	printk_info("smbus_set_link: ");
+//	printk(BIOS_INFO, "smbus_set_link: ");
 	for (i=pbus_num-1; i>=0; i--) {
-//		printk_info(" %s[%d] -> ", dev_path(pbus_a[i]->dev), pbus_a[i]->link);
+//		printk(BIOS_INFO, " %s[%d] -> ", dev_path(pbus_a[i]->dev), pbus_a[i]->link);
         	if (ops_smbus_bus(get_pbus_smbus(pbus_a[i]->dev))) {
                 	if (pbus_a[i]->dev->ops && pbus_a[i]->dev->ops->set_link)
                         	pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, pbus_a[i]->link);
 		}
 	}
-//	printk_info(" %s\n", dev_path(dev));
+//	printk(BIOS_INFO, " %s\n", dev_path(dev));
 
         return pbus_num;
 }
Index: src/devices/pnp_device.c
===================================================================
--- src/devices/pnp_device.c	(revision 5263)
+++ src/devices/pnp_device.c	(working copy)
@@ -103,7 +103,7 @@
 static void pnp_set_resource(device_t dev, struct resource *resource)
 {
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n",
+		printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n",
 			dev_path(dev), resource->index,
 			resource_type(resource),
 			resource->size);
@@ -121,7 +121,7 @@
 		pnp_set_irq(dev, resource->index, resource->base);
 	}
 	else {
-		printk_err("ERROR: %s %02lx unknown resource type\n",
+		printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n",
 			dev_path(dev), resource->index);
 		return;
 	}
Index: src/devices/pcix_device.c
===================================================================
--- src/devices/pcix_device.c	(revision 5263)
+++ src/devices/pcix_device.c	(working copy)
@@ -38,7 +38,7 @@
 	if (!cap) {
 		return;
 	}
-	printk_debug("%s PCI-X tuning\n", dev_path(dev));
+	printk(BIOS_DEBUG, "%s PCI-X tuning\n", dev_path(dev));
 	status = pci_read_config32(dev, cap + PCI_X_STATUS);
 	orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
 
@@ -135,7 +135,7 @@
 	}
 
 	/* Print the PCI-X bus speed */
-	printk_debug("PCI: %02x: %s\n", dev->link[0].secondary, pcix_speed(sstatus));
+	printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link[0].secondary, pcix_speed(sstatus));
 
 	return max;
 }
Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c	(revision 5263)
+++ src/devices/pci_rom.c	(working copy)
@@ -38,7 +38,7 @@
 	rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
 
 	if (rom_header) {
-		printk_debug("In cbfs, rom address for %s = %p\n",
+		printk(BIOS_DEBUG, "In cbfs, rom address for %s = %p\n",
 			     dev_path(dev), rom_header);
 	} else {
 		unsigned long rom_address;
@@ -59,35 +59,35 @@
 					   rom_address|PCI_ROM_ADDRESS_ENABLE);
 		}
 
-		printk_debug("On card, rom address for %s = %lx\n",
+		printk(BIOS_DEBUG, "On card, rom address for %s = %lx\n",
 				dev_path(dev), rom_address);
 		rom_header = (struct rom_header *)rom_address;
 	}
 
-	printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
+	printk(BIOS_SPEW, "PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
 		    le32_to_cpu(rom_header->signature),
 		    rom_header->size * 512, le32_to_cpu(rom_header->data));
 	if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
-		printk_err("Incorrect Expansion ROM Header Signature %04x\n",
+		printk(BIOS_ERR, "Incorrect Expansion ROM Header Signature %04x\n",
 			   le32_to_cpu(rom_header->signature));
 		return NULL;
 	}
 
 	rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
 
-	printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
+	printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n",
 		    rom_data->vendor, rom_data->device);
 	if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
-		printk_err("ID mismatch: Vendor ID %04x, Device ID %04x\n",
+		printk(BIOS_ERR, "ID mismatch: Vendor ID %04x, Device ID %04x\n",
 			   rom_data->vendor, rom_data->device);
 		return NULL;
 	}
 
-	printk_spew("PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",
+	printk(BIOS_SPEW, "PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",
 		    rom_data->class_hi, rom_data->class_lo,
 		    rom_data->type);
 	if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
-		printk_debug("Class Code mismatch ROM %08x, dev %08x\n", 
+		printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n", 
 			     (rom_data->class_hi << 8) | rom_data->class_lo,
 			     dev->class);
 		//return NULL;
@@ -124,14 +124,14 @@
 		if (dev != vga_pri) return NULL; // only one VGA supported
 #endif
 		if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) {
-			printk_debug("copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n",
+			printk(BIOS_DEBUG, "copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n",
 			    rom_header, PCI_VGA_RAM_IMAGE_START, rom_size);
 			memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size);
 		}
 		return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START);
 	}
 
-	printk_debug("copying non-VGA ROM Image from %p to %p, 0x%x bytes\n",
+	printk(BIOS_DEBUG, "copying non-VGA ROM Image from %p to %p, 0x%x bytes\n",
 		    rom_header, pci_ram_image_start, rom_size);
 
 	memcpy(pci_ram_image_start, rom_header, rom_size);
Index: src/devices/pci_device.c
===================================================================
--- src/devices/pci_device.c	(revision 5263)
+++ src/devices/pci_device.c	(working copy)
@@ -136,7 +136,7 @@
 		int this_cap;
 		pos &= ~3;
 		this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
-		printk_spew("Capability: type 0x%02x @ 0x%02x\n", this_cap,
+		printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", this_cap,
 			    pos);
 		if (this_cap == 0xff) {
 			break;
@@ -226,8 +226,7 @@
 	 */
 	if (moving == 0) {
 		if (value != 0) {
-			printk_debug
-			    ("%s register %02lx(%08lx), read-only ignoring it\n",
+			printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
 			     dev_path(dev), index, value);
 		}
 		resource->flags = 0;
@@ -257,8 +256,8 @@
 			resource->flags |= IORESOURCE_PCI64;
 		} else {
 			/* Invalid value. */
-			printk_err("Broken BAR with value %lx\n", attr);
-			printk_err(" on dev %s at index %02lx\n",
+			printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
+			printk(BIOS_ERR, " on dev %s at index %02lx\n",
 			       dev_path(dev), index);
 			resource->flags = 0;
 		}
@@ -313,8 +312,7 @@
 		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
 	} else {
 		if (value != 0) {
-			printk_debug
-			    ("%s register %02lx(%08lx), read-only ignoring it\n",
+			printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
 			     dev_path(dev), index, value);
 		}
 		resource->flags = 0;
@@ -454,7 +452,7 @@
 
 	/* Make certain the resource has actually been assigned a value. */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
+		printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
 			   dev_path(dev), resource->index,
 			   resource_type(resource), resource->size);
 		return;
@@ -543,7 +541,7 @@
 	} else {
 		/* Don't let me think I stored the resource. */
 		resource->flags &= ~IORESOURCE_STORED;
-		printk_err("ERROR: invalid resource->index %lx\n",
+		printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
 			   resource->index);
 	}
 	report_resource_stored(dev, resource, "");
@@ -594,7 +592,7 @@
 	/* Set the subsystem vendor and device id for mainboard devices. */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk_debug("%s subsystem <- %02x/%02x\n",
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
 			     dev_path(dev),
 			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
 			     CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
@@ -607,7 +605,7 @@
 	/* v3 has
 	 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR);	// Error check.
 	 */
-	printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
+	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
 }
 
@@ -623,7 +621,7 @@
 	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 	ctrl |= dev->link[0].bridge_ctrl;
 	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR);	/* Error check. */
-	printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+	printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
 	pci_dev_enable_resources(dev);
@@ -731,7 +729,7 @@
 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 	if (pos) {
-		printk_debug("%s subordinate bus PCI-X\n", dev_path(dev));
+		printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
 		return &default_pcix_ops_bus;
 	}
 #endif
@@ -745,7 +743,7 @@
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 		if ((flags >> 13) == 1) {
 			/* Host or Secondary Interface */
-			printk_debug("%s subordinate bus Hypertransport\n",
+			printk(BIOS_DEBUG, "%s subordinate bus Hypertransport\n",
 				     dev_path(dev));
 			return &default_ht_ops_bus;
 		}
@@ -760,11 +758,11 @@
 		case PCI_EXP_TYPE_ROOT_PORT:
 		case PCI_EXP_TYPE_UPSTREAM:
 		case PCI_EXP_TYPE_DOWNSTREAM:
-			printk_debug("%s subordinate bus PCI Express\n",
+			printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
 				     dev_path(dev));
 			return &default_pciexp_ops_bus;
 		case PCI_EXP_TYPE_PCI_BRIDGE:
-			printk_debug("%s subordinate PCI\n", dev_path(dev));
+			printk(BIOS_DEBUG, "%s subordinate PCI\n", dev_path(dev));
 			return &default_pci_ops_bus;
 		default:
 			break;
@@ -795,7 +793,7 @@
 		if ((driver->vendor == dev->vendor) &&
 		    (driver->device == dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
-			printk_spew("%s [%04x/%04x] %sops\n",
+			printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
 				    dev_path(dev),
 				    driver->vendor, driver->device,
 				    (driver->ops->scan_bus ? "bus " : ""));
@@ -823,7 +821,7 @@
 	default:
 	      bad:
 		if (dev->enabled) {
-			printk_err("%s [%04x/%04x/%06x] has unknown header "
+			printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown header "
 				   "type %02x, ignoring.\n",
 				   dev_path(dev),
 				   dev->vendor, dev->device,
@@ -852,7 +850,7 @@
 	dev = 0;
 	for (; *list; list = &(*list)->sibling) {
 		if ((*list)->path.type != DEVICE_PATH_PCI) {
-			printk_err("child %s not a pci device\n",
+			printk(BIOS_ERR, "child %s not a pci device\n",
 				   dev_path(*list));
 			continue;
 		}
@@ -916,7 +914,7 @@
 		 */
 		if ((id == 0xffffffff) || (id == 0x00000000) ||
 		    (id == 0x0000ffff) || (id == 0xffff0000)) {
-			printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
+			printk(BIOS_SPEW, "%s, bad id 0x%x\n", dev_path(&dummy), id);
 			return NULL;
 		}
 		dev = alloc_dev(bus, &dummy.path);
@@ -947,7 +945,7 @@
 		if ((id == 0xffffffff) || (id == 0x00000000) ||
 		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			if (dev->enabled) {
-				printk_info("PCI: Static device %s not found, disabling it.\n",
+				printk(BIOS_INFO, "PCI: Static device %s not found, disabling it.\n",
 					    dev_path(dev));
 				dev->enabled = 0;
 			}
@@ -982,7 +980,7 @@
 	}
 
 	/* Display the device. */
-	printk_debug("%s [%04x/%04x] %s%s\n",
+	printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n",
 		     dev_path(dev),
 		     dev->vendor, dev->device,
 		     dev->enabled ? "enabled" : "disabled",
@@ -1016,10 +1014,10 @@
 	struct device *child;
 
 #if CONFIG_PCI_BUS_SEGN_BITS
-	printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
+	printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
 		     bus->secondary >> 8, bus->secondary & 0xff);
 #else
-	printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
+	printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
 #endif
 
 	old_devices = bus->children;
@@ -1055,11 +1053,11 @@
 	 */
 	if (old_devices) {
 		device_t left;
-		printk_warning("PCI: Left over static devices:\n");
+		printk(BIOS_WARNING, "PCI: Left over static devices:\n");
 		for (left = old_devices; left; left = left->sibling) {
-			printk_warning("%s\n", dev_path(left));
+			printk(BIOS_WARNING, "%s\n", dev_path(left));
 		}
-		printk_warning("PCI: Check your mainboard Config.lb.\n");
+		printk(BIOS_WARNING, "PCI: Check your mainboard Config.lb.\n");
 	}
 
 	/* For all children that implement scan_bus() (i.e. bridges)
@@ -1073,7 +1071,7 @@
 	 * side of any bridges that may be on this bus plus any devices.
 	 * Return how far we've got finding sub-buses.
 	 */
-	printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
+	printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
 	post_code(0x55);
 	return max;
 }
@@ -1100,7 +1098,7 @@
 	u32 buses;
 	u16 cr;
 
-	printk_spew("%s for %s\n", __func__, dev_path(dev));
+	printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
 
 	bus = &dev->link[0];
 	bus->dev = dev;
@@ -1146,7 +1144,7 @@
 	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 	pci_write_config16(dev, PCI_COMMAND, cr);
 
-	printk_spew("%s returns max %d\n", __func__, max);
+	printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
 	return max;
 }
 
@@ -1224,7 +1222,7 @@
 
 		irq = pIntAtoD[line - 1];
 
-		printk_debug("Assigning IRQ %d to %d:%x.%d\n",
+		printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
 			irq, bus, slot, funct);
 
 		pci_write_config8(pdev, PCI_INTERRUPT_LINE, 
@@ -1232,7 +1230,7 @@
 
 #ifdef PARANOID_IRQ_ASSIGNMENTS
 		irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
-		printk_debug("  Readback = %d\n", irq);
+		printk(BIOS_DEBUG, "  Readback = %d\n", irq);
 #endif
 
 		// Change to level triggered
Index: src/devices/device_util.c
===================================================================
--- src/devices/device_util.c	(revision 5263)
+++ src/devices/device_util.c	(working copy)
@@ -203,7 +203,7 @@
 			sprintf(buffer, "CPU_BUS: %02x", dev->path.cpu_bus.id);
 			break;
 		default:
-			printk_err("Unknown device path type: %d\n", dev->path.type);
+			printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type);
 			break;
 		}
 	}
@@ -253,7 +253,7 @@
 			equal = (path1->cpu_bus.id == path2->cpu_bus.id);
 			break;
 		default:
-			printk_err("Uknown device type: %d\n", path1->type);
+			printk(BIOS_ERR, "Uknown device type: %d\n", path1->type);
 			break;
 		}
 	}
@@ -355,7 +355,7 @@
 	/* See if there is a resource with the appropriate index */
 	resource = probe_resource(dev, index);
 	if (!resource) {
-		printk_emerg("%s missing resource: %02x\n",
+		printk(BIOS_EMERG, "%s missing resource: %02x\n",
 			dev_path(dev), index);
 		die("");
 	}
@@ -468,7 +468,7 @@
 			sprintf(buf, "bus %02x ", dev->link[0].secondary);
 #endif
 		}
-		printk_debug(
+		printk(BIOS_DEBUG, 
 			"%s %02lx <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n",
 			dev_path(dev),
 			resource->index,
Index: src/devices/pci_ops.c
===================================================================
--- src/devices/pci_ops.c	(revision 5263)
+++ src/devices/pci_ops.c	(working copy)
@@ -39,7 +39,7 @@
 
 	while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
 		if (pbus == pbus->dev->bus) {
-			printk_alert("%s in endless loop looking for a parent "
+			printk(BIOS_ALERT, "%s in endless loop looking for a parent "
 				"bus with ops_pci_bus for %s, breaking out.\n",
 				 __func__, dev_path(dev));
 			break;
@@ -48,7 +48,7 @@
 	}
 	if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) {
 		/* This can happen before the device tree is set up completely. */
-		//printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev));
+		//printk(BIOS_EMERG, "%s: Cannot find pci bus operations.\n", dev_path(dev));
 		pbus = NULL;
 	}
 	return pbus;
Index: src/include/assert.h
===================================================================
--- src/include/assert.h	(revision 5263)
+++ src/include/assert.h	(working copy)
@@ -48,13 +48,13 @@
 /* GCC and CAR versions */
 #define ASSERT(x) {						\
 	if (!(x)) {						\
-		printk_emerg("ASSERTION FAILED: file '%s', "	\
+		printk(BIOS_EMERG, "ASSERTION FAILED: file '%s', "	\
 			" line %d\n", __FILE__, __LINE__);	\
 		/* die(""); */					\
 	}							\
 }
 #define BUG() {							\
-	printk_emerg("BUG ENCOUNTERED: SYSTEM HALTED at file '%s', "	\
+	printk(BIOS_EMERG, "BUG ENCOUNTERED: SYSTEM HALTED at file '%s', "	\
 		" line %d\n", __FILE__, __LINE__);		\
 	/* die(""); */						\
 }
Index: src/include/cpu/x86/bist.h
===================================================================
--- src/include/cpu/x86/bist.h	(revision 5263)
+++ src/include/cpu/x86/bist.h	(working copy)
@@ -5,7 +5,7 @@
 {
 	if (bist != 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-                printk_emerg("BIST failed: %08x", bist);
+                printk(BIOS_EMERG, "BIST failed: %08x", bist);
 #else
 		print_emerg("BIST failed: ");
 		print_emerg_hex32(bist);
Index: src/superio/via/vt1211/vt1211.c
===================================================================
--- src/superio/via/vt1211/vt1211.c	(revision 5263)
+++ src/superio/via/vt1211/vt1211.c	(working copy)
@@ -113,13 +113,13 @@
 		init_hwm(res0->base);
 		break;
 	default:
-		printk_info("vt1211 asked to initialise unknown device!\n");
+		printk(BIOS_INFO, "vt1211 asked to initialise unknown device!\n");
 	}
 }
 
 void vt1211_pnp_enable_resources(device_t dev)
 {
-	printk_debug("%s - enabling\n",dev_path(dev));
+	printk(BIOS_DEBUG, "%s - enabling\n",dev_path(dev));
 	pnp_enter_ext_func_mode(dev);
 	pnp_enable_resources(dev);
 	pnp_exit_ext_func_mode(dev);
@@ -148,7 +148,7 @@
 	for(i = 0; i < dev->resources; i++) {
 		resource = &dev->resource[i];
 		if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-			printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n",
+			printk(BIOS_ERR, "ERROR: %s %02x %s size: 0x%010Lx not assigned\n",
 				dev_path(dev), dev->resource->index,
 				resource_type(resource),
 				resource->size);
@@ -166,7 +166,7 @@
 			pnp_set_irq(dev, resource->index, resource->base);
 		}
 		else {
-			printk_err("ERROR: %s %02x unknown resource type\n",
+			printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
 				dev_path(dev), resource->index);
 			return;
 		}
@@ -206,7 +206,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_debug("vt1211 enabling PNP devices.\n");
+	printk(BIOS_DEBUG, "vt1211 enabling PNP devices.\n");
 	pnp_enable_devices(dev,
 			&ops,
 			ARRAY_SIZE(pnp_dev_info),
Index: src/superio/renesas/m3885x/superio.c
===================================================================
--- src/superio/renesas/m3885x/superio.c	(revision 5263)
+++ src/superio/renesas/m3885x/superio.c	(working copy)
@@ -39,7 +39,7 @@
 	if (!dev->enabled)
 		return;
 
-	printk_debug("Renesas M3885x: Initializing keyboard.\n");
+	printk(BIOS_DEBUG, "Renesas M3885x: Initializing keyboard.\n");
 	set_kbc_ps2_mode();
 	pc_keyboard_init(&conf->keyboard);
 	m3885_configure_multikey();
Index: src/superio/winbond/w83627ehg/superio.c
===================================================================
--- src/superio/winbond/w83627ehg/superio.c	(revision 5263)
+++ src/superio/winbond/w83627ehg/superio.c	(working copy)
@@ -100,7 +100,7 @@
 		value = pnp_read_index(base, reg);
 		value &= 0xff & (~(hwm_reg_values[i + 1]));
 		value |= 0xff & hwm_reg_values[i + 2];
-		/* printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); */
+		/* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); */
 		pnp_write_index(base, reg, value);
 	}
 }
@@ -152,7 +152,7 @@
 
 	switch (dev->path.pnp.device) {
 	case W83627EHG_HWM:
-		printk_debug("w83627ehg hwm smbus enabled\n");
+		printk(BIOS_DEBUG, "w83627ehg hwm smbus enabled\n");
 		enable_hwm_smbus(dev);
 		break;
 	}
Index: src/superio/winbond/w83627hf/superio.c
===================================================================
--- src/superio/winbond/w83627hf/superio.c	(revision 5263)
+++ src/superio/winbond/w83627hf/superio.c	(working copy)
@@ -120,7 +120,7 @@
 		value &= 0xff & hwm_reg_values[i+1];
 		value |= 0xff & hwm_reg_values[i+2];
 #if 0
-		printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
+		printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
 #endif
 		pnp_write_index(base, reg, value);
 	}
@@ -172,7 +172,7 @@
 	pnp_enable_resources(dev);
 	switch(dev->path.pnp.device) {
 	case W83627HF_HWM:
-		printk_debug("w83627hf hwm smbus enabled\n");
+		printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n");
 		enable_hwm_smbus(dev);
 		break;
 	}
Index: src/superio/ite/it8716f/superio.c
===================================================================
--- src/superio/ite/it8716f/superio.c	(revision 5263)
+++ src/superio/ite/it8716f/superio.c	(working copy)
@@ -72,13 +72,13 @@
 
 	/* Read out current value of FAN_CTL control register (0x14). */
 	value = pnp_read_index(base, 0x14);
-	printk_debug("FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
+	printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
 		     base + 0x14, value);
 
 	/* Set FAN_CTL control register (0x14) polarity to high, and
 	   activate fans 1, 2 and 3. */
 	pnp_write_index(base, 0x14, value | 0x87);
-	printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
+	printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
 		     base + 0x14, value | 0x87);
 }
 #endif
Index: src/superio/smsc/lpc47n217/superio.c
===================================================================
--- src/superio/smsc/lpc47n217/superio.c	(revision 5263)
+++ src/superio/smsc/lpc47n217/superio.c	(working copy)
@@ -180,7 +180,7 @@
 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
 {
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02x not allocated\n",
+		printk(BIOS_ERR, "ERROR: %s %02x not allocated\n",
 			dev_path(dev), resource->index);
 		return;
 	}
@@ -200,7 +200,7 @@
 		lpc47n217_pnp_set_irq(dev, resource->base);
 	}
 	else {
-		printk_err("ERROR: %s %02x unknown resource type\n",
+		printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
 			dev_path(dev), resource->index);
 		return;
 	}
Index: src/superio/smsc/lpc47n227/superio.c
===================================================================
--- src/superio/smsc/lpc47n227/superio.c	(revision 5263)
+++ src/superio/smsc/lpc47n227/superio.c	(working copy)
@@ -163,7 +163,7 @@
 		break;
 
 	case LPC47N227_KBDC:
-		printk_debug("LPC47N227: Initializing keyboard.\n");
+		printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n");
 		pc_keyboard_init(&conf->keyboard);
 		break;
 	}
@@ -176,7 +176,7 @@
 static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource)
 {
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02lx not allocated\n",
+		printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n",
 			   dev_path(dev), resource->index);
 		return;
 	}
@@ -192,7 +192,7 @@
 	} else if (resource->flags & IORESOURCE_IRQ) {
 		lpc47n227_pnp_set_irq(dev, resource->base);
 	} else {
-		printk_err("ERROR: %s %02lx unknown resource type\n",
+		printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n",
 			   dev_path(dev), resource->index);
 		return;
 	}
Index: src/superio/smsc/smscsuperio/superio.c
===================================================================
--- src/superio/smsc/smscsuperio/superio.c	(revision 5263)
+++ src/superio/smsc/smscsuperio/superio.c	(working copy)
@@ -304,7 +304,7 @@
 
 		/* TODO: Error handling? */
 
-		printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
+		printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
 			    superio_id, superio_rev);
 		first_time = 0;
 
Index: src/superio/smsc/lpc47b397/superio.c
===================================================================
--- src/superio/smsc/lpc47b397/superio.c	(revision 5263)
+++ src/superio/smsc/lpc47b397/superio.c	(working copy)
@@ -106,7 +106,7 @@
 
 	switch(dev->path.pnp.device) {
 	case LPC47B397_HWM:
-		printk_debug("lpc47b397 SensorBus Register Access enabled\r\n");
+		printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\r\n");
 		pnp_set_logical_device(dev);
 		enable_hwm_smbus(dev);
 		break;
Index: src/cpu/via/model_c7/model_c7_init.c
===================================================================
--- src/cpu/via/model_c7/model_c7_init.c	(revision 5263)
+++ src/cpu/via/model_c7/model_c7_init.c	(working copy)
@@ -68,7 +68,7 @@
 static void set_c7_speed(int model) {
 	int cnt, current, new, i;
 	msr_t msr;
-	printk_debug("Enabling improved C7 clock and voltage.\n");
+	printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n");
 
 	// Enable Speedstep
 	msr = rdmsr(MSR_IA32_MISC_ENABLE);
@@ -77,16 +77,16 @@
 
 	msr = rdmsr(MSR_IA32_PERF_STATUS);
 
-	printk_info("Voltage: %dmV (min %dmV; max %dmV)\n",
+	printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
 		    ((int)(msr.lo & 0xff) * 16 + 700),
 		    ((int)((msr.hi >> 16) & 0xff) * 16 + 700),
 		    ((int)(msr.hi & 0xff) * 16 + 700));
 
-	printk_info("CPU multiplier: %dx (min %dx; max %dx)\n",
+	printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
 		    (int)((msr.lo >> 8) & 0xff),
 		    (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
 
-	printk_debug(" msr.lo = %x\n", msr.lo);
+	printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
 
 	/* Wait while CPU is busy */
 	cnt = 0;
@@ -95,7 +95,7 @@
 		msr = rdmsr(MSR_IA32_PERF_STATUS);
 		cnt++;
 		if (cnt > 128) {
-			printk_warning("Could not update multiplier and voltage.\n");
+			printk(BIOS_WARNING, "Could not update multiplier and voltage.\n");
 			return;
 		}
 	}
@@ -129,7 +129,7 @@
 
 	msr.lo = new;
 	msr.hi = 0;
-	printk_debug(" new msr.lo = %x\n", msr.lo);
+	printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo);
 
 	wrmsr(MSR_IA32_PERF_CTL, msr);
 
@@ -140,13 +140,13 @@
 		msr = rdmsr(MSR_IA32_PERF_STATUS);
 		cnt++;
 		if (cnt > 128) {
-			printk_warning("Error while updating multiplier and voltage\n");
+			printk(BIOS_WARNING, "Error while updating multiplier and voltage\n");
 			break;
 		}
 	} while (msr.lo & ((1 << 16) | (1 << 17)));
 
-	printk_info("Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
-	printk_info("Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
+	printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
+	printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
 }
 
 static void model_c7_init(device_t dev)
@@ -157,39 +157,39 @@
 
 	get_fms(&c, dev->device);
 
-	printk_info("Detected VIA ");
+	printk(BIOS_INFO, "Detected VIA ");
 
 	switch (c.x86_model) {
 	case 10:
 		msr = rdmsr(0x1153);
 		brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
-		printk_info("Model A ");
+		printk(BIOS_INFO, "Model A ");
 		break;
 	case 13:
 		msr = rdmsr(0x1154);
 		brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
-		printk_info("Model D ");
+		printk(BIOS_INFO, "Model D ");
 		break;
 	default:
-		printk_info("Model Unknown ");
+		printk(BIOS_INFO, "Model Unknown ");
 		brand = 0xff;
 	}
 
 	switch (brand) {
 	case 0:
-		printk_info("C7-M\n");
+		printk(BIOS_INFO, "C7-M\n");
 		break;
 	case 1:
-		printk_info("C7\n");
+		printk(BIOS_INFO, "C7\n");
 		break;
 	case 2:
-		printk_info("Eden\n");
+		printk(BIOS_INFO, "Eden\n");
 		break;
 	case 3:
-		printk_info("C7-D\n");
+		printk(BIOS_INFO, "C7-D\n");
 		break;
 	default:
-		printk_info("%02x (please report)\n", brand);
+		printk(BIOS_INFO, "%02x (please report)\n", brand);
 	}
 
 	/* Gear up */
Index: src/cpu/amd/model_gx2/model_gx2_init.c
===================================================================
--- src/cpu/amd/model_gx2/model_gx2_init.c	(revision 5263)
+++ src/cpu/amd/model_gx2/model_gx2_init.c	(working copy)
@@ -19,7 +19,7 @@
 
 static void model_gx2_init(device_t dev)
 {
-	printk_debug("model_gx2_init\n");
+	printk(BIOS_DEBUG, "model_gx2_init\n");
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -29,7 +29,7 @@
 
 	vsm_end_post_smi();
 
-	printk_debug("model_gx2_init DONE\n");
+	printk(BIOS_DEBUG, "model_gx2_init DONE\n");
 };
 
 static struct device_operations cpu_dev_ops = {
Index: src/cpu/amd/model_gx2/cpubug.c
===================================================================
--- src/cpu/amd/model_gx2/cpubug.c	(revision 5263)
+++ src/cpu/amd/model_gx2/cpubug.c	(working copy)
@@ -169,7 +169,7 @@
 {
 	msr_t msr;
 
-	printk_debug("CPU_BUG:%s\n", __func__);
+	printk(BIOS_DEBUG, "CPU_BUG:%s\n", __func__);
 	/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
 	msr = rdmsr(0x3003);
 	msr.hi &= 0xFFFFF7FF;
@@ -356,10 +356,10 @@
 
 	rev = msr.lo & 0xff;
 	if (rev < 0x20) {
-		printk_err("%s: rev < 0x20! bailing!\n");
+		printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n");
 		return;
 	}
-	printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
+	printk(BIOS_DEBUG, "Doing cpubug fixes for rev 0x%x\n", rev);
 	switch(rev)
 	{
 		case 0x20:
@@ -379,11 +379,11 @@
 		case 0x30: 
 			break;
 		default:
-			printk_err("unknown rev %x, bailing\n", rev);
+			printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);
 			return;
 	}
 	bug784();
 	bug118253();
 	disablememoryreadorder();
-	printk_debug("Done cpubug fixes \n");
+	printk(BIOS_DEBUG, "Done cpubug fixes \n");
 }
Index: src/cpu/amd/model_gx2/vsmsetup.c
===================================================================
--- src/cpu/amd/model_gx2/vsmsetup.c	(revision 5263)
+++ src/cpu/amd/model_gx2/vsmsetup.c	(working copy)
@@ -187,16 +187,16 @@
 	unsigned char *buf;
 	int i;
 
-	printk_err( "do_vsmbios\n");
+	printk(BIOS_ERR,  "do_vsmbios\n");
 	/* Clear VSM BIOS data area. */
 	for (i = 0x400; i < 0x500; i++)
 		*(volatile unsigned char *)i = 0;
 	if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
-		printk_err("do_vsmbios: Failed to load VSA.\n");
+		printk(BIOS_ERR, "do_vsmbios: Failed to load VSA.\n");
 	}
 	buf = VSA2_BUFFER;
 
-	printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",
+	printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n",
 	       buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
 	/* Check for POST code at start of vsainit.bin. If you don't see it,
 	 * don't bother.
@@ -207,7 +207,7 @@
 	}
 
 	/* ecx gets smm, edx gets sysm. */
-	printk_err("Call real_mode_switch_call_vsm\n");
+	printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n");
 //	real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
 
 	/* Restart Timer 1. */
@@ -216,7 +216,7 @@
 
 	/* Check that VSA is running OK. */
 	if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
-		printk_debug("do_vsmbios: VSA2 VR signature verified\n");
+		printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n");
 	else
 		die("FATAL: VSA2 VR signature not valid, install failed!\n");
 }
Index: src/cpu/amd/mtrr/amd_mtrr.c
===================================================================
--- src/cpu/amd/mtrr/amd_mtrr.c	(revision 5263)
+++ src/cpu/amd/mtrr/amd_mtrr.c	(working copy)
@@ -95,7 +95,7 @@
 	if (start_mtrr >= NUM_FIXED_RANGES) {
 		return;
 	}
-	printk_debug("Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
+	printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
 		start_mtrr, last_mtrr);
 	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
 	
@@ -116,9 +116,9 @@
 	wrmsr(SYSCFG_MSR, msr);
 	enable_cache();
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	/* Initialized the fixed_mtrrs to uncached */
-	printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n", 
+	printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n", 
 		0, NUM_FIXED_RANGES);
 	set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
 
@@ -130,7 +130,7 @@
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_fixed_mtrr_resource, &state);
-	printk_debug("DONE fixed MTRRs\n");
+	printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
 
 	if (state.mmio_basek > state.tomk) {
 		state.mmio_basek = state.tomk;
Index: src/cpu/amd/model_fxx/processor_name.c
===================================================================
--- src/cpu/amd/model_fxx/processor_name.c	(revision 5263)
+++ src/cpu/amd/model_fxx/processor_name.c	(working copy)
@@ -443,7 +443,7 @@
 		}
 	}
 	
-	printk_debug("CPU model %s\n", program_string);
+	printk(BIOS_DEBUG, "CPU model %s\n", program_string);
 
 	for (i=0; i<6; i++) {
 		progmsr.lo = program_values[(2*i)+0];
Index: src/cpu/amd/model_fxx/fidvid.c
===================================================================
--- src/cpu/amd/model_fxx/fidvid.c	(revision 5263)
+++ src/cpu/amd/model_fxx/fidvid.c	(working copy)
@@ -15,21 +15,21 @@
 static inline void print_debug_fv(const char *str, unsigned val)
 {
 #if K8_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%x\r\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\r\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_8(const char *str, unsigned val)
 {
 #if K8_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%02x\r\n", str, val);
+		printk(BIOS_DEBUG, "%s%02x\r\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
 {
 #if K8_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%x%x\r\n", str, val, val2);
+		printk(BIOS_DEBUG, "%s%x%x\r\n", str, val, val2);
 #endif
 }
 
@@ -131,7 +131,7 @@
 	apicidx = lapicid();
 
 	if (apicid != apicidx) {
-		printk_err("wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
+		printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
 		return fidvid;
 	}
 
@@ -201,8 +201,8 @@
 	 *	transition to target fid
 	 */
 
-	printk_debug("Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max);
-	printk_debug("Requested fid_new: 0x%x\n", fid_new);
+	printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max);
+	printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new);
 
 	step_limit = 8; /* max 8 steps just in case... */
 	while ((fid_cur != fid_new) && (step_limit--)) {
@@ -218,7 +218,7 @@
 		/* If 200Mhz step OR past 3200 max table value */
 		if ((step == 2) || (fid_new >= 0x18 || fid_cur >= 0x18)) {
 
-			printk_debug("200MHZ step ");
+			printk(BIOS_DEBUG, "200MHZ step ");
 
 			/* Step +/- 200MHz at a time */
 			if (fid_cur < fid_new)
@@ -231,7 +231,7 @@
 			int temp;
 
 			/* look it up in the table */
-			printk_debug("FidVid table step ");
+			printk(BIOS_DEBUG, "FidVid table step ");
 
 			temp = next_fid_200[((fid_new/2) * 13) + (fid_cur/2)];
 
@@ -243,7 +243,7 @@
 				break; /* table error */
 
 		} else { /* step < 2 (100MHZ) */
-			printk_debug("100MHZ step ");
+			printk(BIOS_DEBUG, "100MHZ step ");
 
 			/* The table adjust in 200MHz increments. If requested,
 			 * do the 100MHz increment if the CPU supports it.*/
@@ -251,17 +251,17 @@
 				fid_temp = fid_cur + 1;
 			} else {
 				/* 100 MHZ not supported. Get out of the loop */
-				printk_debug("is not supported.\n");
+				printk(BIOS_DEBUG, "is not supported.\n");
 				break;
 			}
 		}
 
 		if(fid_temp > fid_max) {
-			printk_debug("fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max);
+			printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max);
 			break;
 		}
 
-		printk_debug("fidvid: 0x%x\n", fid_temp);
+		printk(BIOS_DEBUG, "fidvid: 0x%x\n", fid_temp);
 
 		/* set target fid */
 		msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */
Index: src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- src/cpu/amd/model_fxx/model_fxx_init.c	(revision 5263)
+++ src/cpu/amd/model_fxx/model_fxx_init.c	(working copy)
@@ -150,16 +150,16 @@
 {
 	int i;
 	for(i = 0; i < MTRR_COUNT; i++) {
-		printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
+		printk(BIOS_DEBUG, "var mtrr %d: %08x%08x mask: %08x%08x\n",
 			i,
 			state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
 			state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
 	}
-	printk_debug("top_mem:  %08x%08x\n",
+	printk(BIOS_DEBUG, "top_mem:  %08x%08x\n",
 		state->top_mem.hi, state->top_mem.lo);
-	printk_debug("top_mem2: %08x%08x\n",
+	printk(BIOS_DEBUG, "top_mem2: %08x%08x\n",
 		state->top_mem2.hi, state->top_mem2.lo);
-	printk_debug("def_type: %08x%08x\n",
+	printk(BIOS_DEBUG, "def_type: %08x%08x\n",
 		state->def_type.hi, state->def_type.lo);
 }
 #endif
@@ -214,7 +214,7 @@
                         enable_lapic();
 
                         /* Print a status message */
-                        printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
+                        printk(BIOS_DEBUG, "%c", (basek >= TOLM_KB)?'+':'-');
 
                         /* Return to the initialization state */
                         set_init_ecc_mtrrs();
@@ -232,7 +232,7 @@
                 size = (limitk - basek) << 10;
                 addr = map_2M_page(basek >> 11);
                 if (addr == MAPPING_ERROR) {
-                        printk_err("Cannot map page: %lx\n", basek >> 11);
+                        printk(BIOS_ERR, "Cannot map page: %lx\n", basek >> 11);
                         return;
                 }
 
@@ -276,14 +276,14 @@
 	} else {
 		pci_write_config32(f3_dev, SCRUB_CONTROL,
 			(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
-		printk_debug("Scrubbing Disabled\n");
+		printk(BIOS_DEBUG, "Scrubbing Disabled\n");
 	}
 
 
 	/* If ecc support is not enabled don't touch memory */
 	dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
 	if (!(dcl & DCL_DimmEccEn)) {
-		printk_debug("ECC Disabled\n");
+		printk(BIOS_DEBUG, "ECC Disabled\n");
 		return;
 	}
 
@@ -313,7 +313,7 @@
 		begink = (CONFIG_RAMTOP >>10);
 	}
 
-	printk_debug("Clearing memory %luK - %luK: ", begink, endk);
+	printk(BIOS_DEBUG, "Clearing memory %luK - %luK: ", begink, endk);
 
 	/* Save the normal state */
 	save_mtrr_state(&mtrr_state);
@@ -362,7 +362,7 @@
 			(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
 	}
 
-	printk_debug(" done\n");
+	printk(BIOS_DEBUG, " done\n");
 }
 
 
Index: src/cpu/amd/model_fxx/powernow_acpi.c
===================================================================
--- src/cpu/amd/model_fxx/powernow_acpi.c	(revision 5263)
+++ src/cpu/amd/model_fxx/powernow_acpi.c	(working copy)
@@ -156,14 +156,14 @@
 	v[10] = cpuid1.ecx;
 	v[11] = cpuid1.edx;
 	processor_brand[48] = 0;
-	printk_info("processor_brand=%s\n", processor_brand);
+	printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
 
 	/*
 	 * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
 	 * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
 	 * cmp_cap : 0x0 SingleCore ; 0x1 DualCore
 	 */
-	printk_info("Pstates Algorithm ...\n");
+	printk(BIOS_INFO, "Pstates Algorithm ...\n");
 	cmp_cap =
 	    (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
 	     0x3000) >> 12;
@@ -181,7 +181,7 @@
 	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) != 0x6) {
-		printk_info("No valid set of P-states\n");
+		printk(BIOS_INFO, "No valid set of P-states\n");
 		goto write_pstates;
 	}
 
@@ -204,7 +204,7 @@
 		PstateStep_coef = 2;
 
 	if (IntPstateSup == 0) {
-		printk_info("No intermediate P-states are supported\n");
+		printk(BIOS_INFO, "No intermediate P-states are supported\n");
 		goto write_pstates;
 	}
 
@@ -352,12 +352,12 @@
 	/* Print Pstate freq,vid,volt,power */
 
 	for (index = 0; index < Pstate_num; index++) {
-		printk_info("Pstate_freq[%d] = %dMHz\t", index,
+		printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
 			    Pstate_feq[index]);
-		printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
-		printk_info("Pstate_volt[%d] = %dmv\t", index,
+		printk(BIOS_INFO, "Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
+		printk(BIOS_INFO, "Pstate_volt[%d] = %dmv\t", index,
 			    Pstate_volt[index]);
-		printk_info("Pstate_power[%d] = %dmw\n", index,
+		printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
 			    Pstate_power[index]);
 	}
 
Index: src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_fxx/init_cpus.c	(revision 5263)
+++ src/cpu/amd/model_fxx/init_cpus.c	(working copy)
@@ -16,23 +16,23 @@
 
 static inline void print_initcpu8 (const char *strval, unsigned val)
 {
-        printk_debug("%s%02x\r\n", strval, val);
+        printk(BIOS_DEBUG, "%s%02x\r\n", strval, val);
 }
 
 static inline void print_initcpu8_nocr (const char *strval, unsigned val)
 {
-        printk_debug("%s%02x", strval, val);
+        printk(BIOS_DEBUG, "%s%02x", strval, val);
 }
 
 
 static inline void print_initcpu16 (const char *strval, unsigned val)
 {
-        printk_debug("%s%04x\r\n", strval, val);
+        printk(BIOS_DEBUG, "%s%04x\r\n", strval, val);
 }
 
 static inline void print_initcpu(const char *strval, unsigned val)
 {
-        printk_debug("%s%08x\r\n", strval, val);
+        printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
 }
 
 typedef void (*process_ap_t)(unsigned apicid, void *gp);
@@ -155,7 +155,7 @@
 
 static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
 {
-                printk_debug("%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
+                printk(BIOS_DEBUG, "%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
 }
 
 
Index: src/cpu/amd/sc520/sc520.c
===================================================================
--- src/cpu/amd/sc520/sc520.c	(revision 5263)
+++ src/cpu/amd/sc520/sc520.c	(working copy)
@@ -36,9 +36,9 @@
   unsigned long *l = (unsigned long *) 0xfffef088;
   int i;
   for(i = 0; i < 16; i++, l++)
-    printk_err("Par%d: 0x%lx\n", i, *l);
+    printk(BIOS_ERR, "Par%d: 0x%lx\n", i, *l);
 
-  printk_spew("SC520 random fixup ...\n");
+  printk(BIOS_SPEW, "SC520 random fixup ...\n");
 }
 
 
@@ -49,14 +49,14 @@
 void sc520_enable_resources(struct device *dev) {
 	unsigned char command;
 
-	printk_spew("%s\n", __func__);
+	printk(BIOS_SPEW, "%s\n", __func__);
         command = pci_read_config8(dev, PCI_COMMAND);
-        printk_spew("========>%s, command 0x%x\n", __func__, command);
+        printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
         command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
-        printk_spew("========>%s, command 0x%x\n", __func__, command);
+        printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
         pci_write_config8(dev, PCI_COMMAND, command);
         command = pci_read_config8(dev, PCI_COMMAND);
-        printk_spew("========>%s, command 0x%x\n", __func__, command);
+        printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
 /*
  */
 
@@ -100,7 +100,7 @@
         unsigned long basek, unsigned long sizek)
 {
         struct resource *resource;
-  printk_spew("%s sizek 0x%x\n", __func__, sizek);
+  printk(BIOS_SPEW, "%s sizek 0x%x\n", __func__, sizek);
         if (!sizek) {
                 return;
         }
@@ -126,14 +126,14 @@
 {
 	struct resource *min;
 	uint32_t tolm;
-  printk_spew("%s\n", __func__);
+  printk(BIOS_SPEW, "%s\n", __func__);
 	min = 0;
 	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 	tolm = 0xffffffffUL;
 	if (min && tolm > min->base) {
 		tolm = min->base;
 	}
-  printk_spew("%s returns 0x%x\n", __func__, tolm);
+  printk(BIOS_SPEW, "%s returns 0x%x\n", __func__, tolm);
 	return tolm;
 }
 
@@ -141,7 +141,7 @@
 {
 	device_t mc_dev;
         uint32_t pci_tolm;
-  printk_spew("%s\n", __func__);
+  printk(BIOS_SPEW, "%s\n", __func__);
         pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
@@ -162,10 +162,10 @@
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk_err("ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
 					ramregs[i]);
 		}
-		printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 		tomk = rambits*8*1024;
 #endif
 		tomk = 32 * 1024;
@@ -186,20 +186,20 @@
 #if 0
 void sc520_enable_resources(device_t dev) {
 
-	printk_spew("%s\n", __func__);
-	printk_spew("THIS IS FOR THE SC520 =============================\n");
+	printk(BIOS_SPEW, "%s\n", __func__);
+	printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n");
 
 /*
 	command = pci_read_config8(dev, PCI_COMMAND);
-	printk_spew("%s, command 0x%x\n", __func__, command);
+	printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 	command |= PCI_COMMAND_MEMORY;
-	printk_spew("%s, command 0x%x\n", __func__, command);
+	printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 	pci_write_config8(dev, PCI_COMMAND, command);
 	command = pci_read_config8(dev, PCI_COMMAND);
-	printk_spew("%s, command 0x%x\n", __func__, command);
+	printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
  */
 	enable_childrens_resources(dev);
-	printk_spew("%s\n", __func__);
+	printk(BIOS_SPEW, "%s\n", __func__);
 }
 #endif
 
@@ -220,7 +220,7 @@
 #if 0
 static void cpu_bus_init(device_t dev)
 {
-  printk_spew("cpu_bus_init\n");
+  printk(BIOS_SPEW, "cpu_bus_init\n");
 }
 
 static void cpu_bus_noop(device_t dev)
@@ -238,7 +238,7 @@
 
 static void enable_dev(struct device *dev)
 {
-  printk_spew("%s\n", __func__);
+  printk(BIOS_SPEW, "%s\n", __func__);
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
Index: src/cpu/amd/dualcore/amd_sibling.c
===================================================================
--- src/cpu/amd/dualcore/amd_sibling.c	(revision 5263)
+++ src/cpu/amd/dualcore/amd_sibling.c	(working copy)
@@ -109,7 +109,7 @@
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n");
+		printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n");
 		enable_apic_ext_id(nodes);
 	}
 	
@@ -140,7 +140,7 @@
 	}
 
 #if 1
-	printk_debug("CPU: %u %d siblings\n",
+	printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
 		cpu->path.apic.apic_id,
 		siblings);
 #endif
@@ -191,7 +191,7 @@
                 new->path.apic.core_id = i;
 
 #if 1
-		printk_debug("CPU: %u has sibling %u\n", 
+		printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", 
 			cpu->path.apic.apic_id,
 			new->path.apic.apic_id);
 #endif
Index: src/cpu/amd/model_lx/cpubug.c
===================================================================
--- src/cpu/amd/model_lx/cpubug.c	(revision 5263)
+++ src/cpu/amd/model_lx/cpubug.c	(working copy)
@@ -87,5 +87,5 @@
 {
 	pcideadlock();
 	disablememoryreadorder();
-	printk_debug("Done cpubug fixes \n");
+	printk(BIOS_DEBUG, "Done cpubug fixes \n");
 }
Index: src/cpu/amd/model_lx/model_lx_init.c
===================================================================
--- src/cpu/amd/model_lx/model_lx_init.c	(revision 5263)
+++ src/cpu/amd/model_lx/model_lx_init.c	(working copy)
@@ -40,7 +40,7 @@
 
 static void model_lx_init(device_t dev)
 {
-	printk_debug("model_lx_init\n");
+	printk(BIOS_DEBUG, "model_lx_init\n");
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -52,11 +52,11 @@
 	vsm_end_post_smi();
 
 	// Set gate A20 (legacy vsm disables it in late init)
-	printk_debug("A20 (0x92): %d\n", inb(0x92));
+	printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
 	outb(0x02, 0x92);
-	printk_debug("A20 (0x92): %d\n", inb(0x92));
+	printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
 
-	printk_debug("CPU model_lx_init DONE\n");
+	printk(BIOS_DEBUG, "CPU model_lx_init DONE\n");
 };
 
 static struct device_operations cpu_dev_ops = {
Index: src/cpu/amd/model_lx/vsmsetup.c
===================================================================
--- src/cpu/amd/model_lx/vsmsetup.c	(revision 5263)
+++ src/cpu/amd/model_lx/vsmsetup.c	(working copy)
@@ -274,7 +274,7 @@
 	unsigned int size = SMM_SIZE * 1024;
 	int i;
 
-	printk_err("do_vsmbios\n");
+	printk(BIOS_ERR, "do_vsmbios\n");
 	/* clear vsm bios data area */
 	for (i = 0x400; i < 0x500; i++) {
 		*(volatile unsigned char *)i = 0;
@@ -288,23 +288,23 @@
 	 */
 
 	if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
-		printk_err("do_vsmbios: Failed to load VSA.\n");
+		printk(BIOS_ERR, "do_vsmbios: Failed to load VSA.\n");
 	}
 	buf = (unsigned char *)VSA2_BUFFER;
-	printk_debug("buf %p *buf %d buf[256k] %d\n",
+	printk(BIOS_DEBUG, "buf %p *buf %d buf[256k] %d\n",
 		     buf, buf[0], buf[SMM_SIZE * 1024]);
-	printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",
+	printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n",
 		     buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
 	/* check for post code at start of vsainit.bin. If you don't see it,
 	   don't bother. */
 	if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
 	    (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
-		printk_err("do_vsmbios: no vsainit.bin signature, skipping!\n");
+		printk(BIOS_ERR, "do_vsmbios: no vsainit.bin signature, skipping!\n");
 		return;
 	}
 
 	/* ecx gets smm, edx gets sysm */
-	printk_err("Call real_mode_switch_call_vsm\n");
+	printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n");
 	real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
 
 	/* restart timer 1 */
@@ -313,10 +313,9 @@
 
 	// check that VSA is running OK
 	if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
-		printk_debug("do_vsmbios: VSA2 VR signature verified\n");
+		printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n");
 	else
-		printk_err
-		    ("do_vsmbios: VSA2 VR signature not valid, install failed!\n");
+		printk(BIOS_ERR, "do_vsmbios: VSA2 VR signature not valid, install failed!\n");
 }
 
 // we had hoped to avoid this.
@@ -495,30 +494,30 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
 		     eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     (u32)ip, (u32)cs, (u32)flags);
-	printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n",
+	printk(BIOS_DEBUG, "biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n",
 		     (u16)(gsfs >> 16), (u16)(gsfs & 0xffff), (u16)(dses >> 16), (u16)(dses & 0xffff));
 
 	// cases in a good compiler are just as good as your own tables.
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception 0x%x\n", (u32)intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception 0x%x\n", (u32)intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *)esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *)esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out ... not now\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out ... not now\n");
 		// "longjmp"
 		//vga_exit();
 		break;
@@ -537,7 +536,7 @@
 				  &ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupported int #0x%x\n", (u32)intnumber);
+		printk(BIOS_INFO, "BIOSINT: Unsupported int #0x%x\n", (u32)intnumber);
 		break;
 	}
 	if (ret)
@@ -648,7 +647,7 @@
 				// devfn is an int, so we mask it off.
 				busdevfn = (dev->bus->secondary << 8)
 				    | (dev->path.pci.devfn & 0xff);
-				printk_debug("0x%x: return 0x%x\n", func,
+				printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
 					     busdevfn);
 				*pebx = busdevfn;
 				retval = 0;
@@ -675,8 +674,7 @@
 			reg = *pedi;
 			dev = dev_find_slot(bus, devfn);
 			if (!dev) {
-				printk_debug
-				    ("0x%x: BAD DEVICE bus %d devfn 0x%x\n",
+				printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n",
 				     func, bus, devfn);
 				// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 				*peax = PCIBIOS_BADREG;
@@ -711,15 +709,14 @@
 
 			if (retval)
 				retval = PCIBIOS_BADREG;
-			printk_debug
-			    ("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+			printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 			*peax = 0;
 			retval = 0;
 		}
 		break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
 		break;
 	}
 
@@ -731,7 +728,7 @@
 		unsigned long *ecx, unsigned long *eax, unsigned long *flags)
 {
 	int res = -1;
-	printk_debug("handleint21, eax 0x%x\n", (u32)*eax);
+	printk(BIOS_DEBUG, "handleint21, eax 0x%x\n", (u32)*eax);
 	switch (*eax & 0xffff) {
 	case 0x5f19:
 		break;
Index: src/cpu/amd/quadcore/quadcore.c
===================================================================
--- src/cpu/amd/quadcore/quadcore.c	(revision 5263)
+++ src/cpu/amd/quadcore/quadcore.c	(working copy)
@@ -59,7 +59,7 @@
 {
 	u32 dword, i;
 
-	printk_debug("Start other core - nodeid: %02x  cores: %02x\n", nodeid, cores);
+	printk(BIOS_DEBUG, "Start other core - nodeid: %02x  cores: %02x\n", nodeid, cores);
 
 	/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
 	   accesses and error logging to core0 */
@@ -88,7 +88,7 @@
 
 	// disable quad_core
 	if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0)  {
-		printk_debug("Skip additional core init\n");
+		printk(BIOS_DEBUG, "Skip additional core init\n");
 		return;
 	}
 
@@ -96,7 +96,7 @@
 
 	for (nodeid = 0; nodeid < nodes; nodeid++) {
 		u32 cores = get_core_num_in_bsp(nodeid);
-		printk_debug("init node: %02x  cores: %02x \n", nodeid, cores);
+		printk(BIOS_DEBUG, "init node: %02x  cores: %02x \n", nodeid, cores);
 		if (cores > 0) {
 			real_start_other_core(nodeid, cores);
 		}
Index: src/cpu/amd/quadcore/amd_sibling.c
===================================================================
--- src/cpu/amd/quadcore/amd_sibling.c	(revision 5263)
+++ src/cpu/amd/quadcore/amd_sibling.c	(working copy)
@@ -114,7 +114,7 @@
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
+		printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
 		enable_apic_ext_id(sysconf.nodes);
 	}
 
Index: src/cpu/amd/microcode/microcode.c
===================================================================
--- src/cpu/amd/microcode/microcode.c	(revision 5263)
+++ src/cpu/amd/microcode/microcode.c	(working copy)
@@ -61,8 +61,8 @@
 {
 
 	if (m->processor_rev_id != equivalent_processor_rev_id) {
-		printk_err("microcode: rev id (%x) does not match this patch.\n", m->processor_rev_id);
-		printk_err("microcode: Not updated! Fix microcode_updates[] \n");
+		printk(BIOS_ERR, "microcode: rev id (%x) does not match this patch.\n", m->processor_rev_id);
+		printk(BIOS_ERR, "microcode: Not updated! Fix microcode_updates[] \n");
 		return 0;
 	}
 	if (m->nb_dev_id) {
@@ -93,7 +93,7 @@
 	msr = rdmsr(0x8b);
 	patch_id = msr.lo;
 
-	printk_debug("microcode: equivalent rev id  = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id);
+	printk(BIOS_DEBUG, "microcode: equivalent rev id  = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id);
 
 	m = microcode_updates;
 
@@ -107,13 +107,13 @@
 
 			wrmsr(0xc0010020, msr);
 
-			printk_debug("microcode: patch id to apply = 0x%08x\n", m->patch_id);
+			printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
 
 			//read the patch_id again
 			msr = rdmsr(0x8b);
 			new_patch_id = msr.lo;
 
-			printk_debug("microcode: updated to patch id = 0x%08x %s\n", new_patch_id , (new_patch_id == m->patch_id)?" success\n":" fail\n" );
+			printk(BIOS_DEBUG, "microcode: updated to patch id = 0x%08x %s\n", new_patch_id , (new_patch_id == m->patch_id)?" success\n":" fail\n" );
 			break;
 		}
 		c += 2048;
Index: src/cpu/amd/car/post_cache_as_ram.c
===================================================================
--- src/cpu/amd/car/post_cache_as_ram.c	(revision 5263)
+++ src/cpu/amd/car/post_cache_as_ram.c	(working copy)
@@ -5,7 +5,7 @@
 
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
-	printk_debug("%s%08x\r\n", strval, val);
+	printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
 }
 
 /* from linux kernel 2.6.32 asm/string_32.h */
Index: src/cpu/amd/model_10xxx/fidvid.c
===================================================================
--- src/cpu/amd/model_10xxx/fidvid.c	(revision 5263)
+++ src/cpu/amd/model_10xxx/fidvid.c	(working copy)
@@ -28,21 +28,21 @@
 static void print_debug_fv(const char *str, u32 val)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%x\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
 static void print_debug_fv_8(const char *str, u8 val)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%02x\n", str, val);
+		printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
 static void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%x%x\n", str, val, val2);
+		printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
 
@@ -68,7 +68,7 @@
 		dword |= (u32) fid & 0x1F;
 		dword |= 1 << 5;	// enable
 		pci_write_config32(dev, 0xd4, dword);
-		printk_debug("FID Change Node:%02x, F3xD4: %08x \n", i, dword);
+		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword);
 	}
 }
 
@@ -186,7 +186,7 @@
 	nodes = get_nodes();
 
 	for(i = 0; i < nodes; i++) {
-		printk_debug("Prep FID/VID Node:%02x \n", i);
+		printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
 		dev = NODE_PCI(i,3);
 
 		dword = pci_read_config32(dev, 0xd8);
@@ -286,15 +286,15 @@
 		pci_write_config32(dev, 0x80, dword);
 
 		dword = pci_read_config32(dev, 0x80);
-		printk_debug("  F3x80: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3x80: %08x \n", dword);
 		dword = pci_read_config32(dev, 0x84);
-		printk_debug("  F3x84: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3x84: %08x \n", dword);
 		dword = pci_read_config32(dev, 0xD4);
-		printk_debug("  F3xD4: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3xD4: %08x \n", dword);
 		dword = pci_read_config32(dev, 0xD8);
-		printk_debug("  F3xD8: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3xD8: %08x \n", dword);
 		dword = pci_read_config32(dev, 0xDC);
-		printk_debug("  F3xDC: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3xDC: %08x \n", dword);
 
 
 	}
@@ -495,7 +495,7 @@
 	u8 nodes;
 	u8 i;
 
-	printk_debug("FIDVID on AP: %02x\n", apicid);
+	printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
 
 	/* Steps 1-6 of BIOS NB COF and VID Configuration
 	 * for SVI and Single-Plane PVI Systems.
@@ -773,7 +773,7 @@
 	u32 reg1fc;
 	u8 pvimode;
 
-	printk_debug("FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
 	/* FIXME: The first half of this function is nearly the same as
 	 * init_fidvid_bsp() and the code could be combined.
 	 */
Index: src/cpu/amd/model_10xxx/update_microcode.c
===================================================================
--- src/cpu/amd/model_10xxx/update_microcode.c	(revision 5263)
+++ src/cpu/amd/model_10xxx/update_microcode.c	(working copy)
@@ -97,7 +97,7 @@
 	if (equivalent_processor_rev_id != 0) {
 		amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id);
 	} else {
-		printk_debug("microcode: rev id not found. Skipping microcode patch!\n");
+		printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n");
 	}
 
 }
Index: src/cpu/amd/model_10xxx/processor_name.c
===================================================================
--- src/cpu/amd/model_10xxx/processor_name.c	(revision 5263)
+++ src/cpu/amd/model_10xxx/processor_name.c	(working copy)
@@ -226,7 +226,7 @@
 	strcpymax(&program_string[j], processor_name_string,
 		  sizeof(program_string) - j);
 
-	printk_debug("CPU model: %s\n", program_string);
+	printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
 
 	for (i = 0; i < 6; i++) {
 		msr.lo = p_program_string[(2 * i) + 0];
Index: src/cpu/amd/model_10xxx/model_10xxx_init.c
===================================================================
--- src/cpu/amd/model_10xxx/model_10xxx_init.c	(revision 5263)
+++ src/cpu/amd/model_10xxx/model_10xxx_init.c	(working copy)
@@ -77,7 +77,7 @@
 #endif
 
 	id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
-	printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
+	printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -114,7 +114,7 @@
 		msr.hi |= 1 << (33-32);
 		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
-	printk_debug("siblings = %02d, ", siblings);
+	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 #endif
 
 	/* DisableCf8ExtCfg */
Index: src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_10xxx/init_cpus.c	(revision 5263)
+++ src/cpu/amd/model_10xxx/init_cpus.c	(working copy)
@@ -32,24 +32,24 @@
 
 static void print_initcpu8 (const char *strval, u8 val)
 {
-	printk_debug("%s%02x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%02x\n", strval, val);
 }
 
 static void print_initcpu8_nocr (const char *strval, u8 val)
 {
-	printk_debug("%s%02x", strval, val);
+	printk(BIOS_DEBUG, "%s%02x", strval, val);
 }
 
 
 static void print_initcpu16 (const char *strval, u16 val)
 {
-	printk_debug("%s%04x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%04x\n", strval, val);
 }
 
 
 static void print_initcpu(const char *strval, u32 val)
 {
-	printk_debug("%s%08x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 }
 
 
@@ -223,7 +223,7 @@
 
 static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str)
 {
-		printk_debug("%s --- {	 APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
+		printk(BIOS_DEBUG, "%s --- {	 APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
 }
 
 
@@ -406,10 +406,10 @@
 		{
 		// check warm(bios) reset to call stage2 otherwise do stage1
 			if (warm_reset_detect(id.nodeid)) {
-				printk_debug("init_fidvid_stage2 apicid: %02x\n", apicid);
+				printk(BIOS_DEBUG, "init_fidvid_stage2 apicid: %02x\n", apicid);
 				init_fidvid_stage2(apicid, id.nodeid);
 			} else {
-				printk_debug("init_fidvid_ap(stage1) apicid: %02x\n", apicid);
+				printk(BIOS_DEBUG, "init_fidvid_ap(stage1) apicid: %02x\n", apicid);
 				init_fidvid_ap(bsp_apicid, apicid, id.nodeid, id.coreid);
 			}
 		}
@@ -424,7 +424,7 @@
 		set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 
 		STOP_CAR_AND_CPU();
-		printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);
+		printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid);
 	}
 
 	return bsp_apicid;
@@ -449,12 +449,12 @@
 	u32 i;
 	u32 nodes = get_nodes();
 
-	printk_debug("Wait all core0s started \n");
+	printk(BIOS_DEBUG, "Wait all core0s started \n");
 	for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
 		while(!is_core0_started(i)) {}
 		print_initcpu8("  Core0 started on node: ", i);
 	}
-	printk_debug("Wait all core0s started done\n");
+	printk(BIOS_DEBUG, "Wait all core0s started done\n");
 }
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 /**
@@ -471,7 +471,7 @@
 	u32 val;
 
 	/* Enable routing table */
-	printk_debug("Start node %02x", node);
+	printk(BIOS_DEBUG, "Start node %02x", node);
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
 	/* For FAM10 support, we need to set Dram base/limit for the new node */
@@ -484,7 +484,7 @@
 	val &= ~(1 << 1);
 	pci_write_config32(NODE_HT(node), 0x6c, val);
 
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 }
 
 
@@ -514,7 +514,7 @@
 	};
 	u16 i;
 
-	printk_debug("setup_remote_node: %02x", node);
+	printk(BIOS_DEBUG, "setup_remote_node: %02x", node);
 
 	/* copy the default resource map from node 0 */
 	for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
@@ -525,7 +525,7 @@
 		pci_write_config32(NODE_MP(node), reg, value);
 
 	}
-	printk_debug(" done\n");
+	printk(BIOS_DEBUG, " done\n");
 }
 #endif	/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
@@ -845,7 +845,7 @@
 	u8 i;
 	u32 revision, platform;
 
-	printk_debug("cpuSetAMDMSR ");
+	printk(BIOS_DEBUG, "cpuSetAMDMSR ");
 
 	revision = mctGetLogicalCPUID(0xFF);
 	platform = get_platform_type();
@@ -863,7 +863,7 @@
 	}
 	AMD_Errata298();
 
-	printk_debug(" done\n");
+	printk(BIOS_DEBUG, " done\n");
 }
 
 
@@ -879,7 +879,7 @@
 	u32 val;
 	u8 offset;
 
-	printk_debug("cpuSetAMDPCI %02d", node);
+	printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
 
 
 	revision = mctGetLogicalCPUID(node);
@@ -933,7 +933,7 @@
 	if (revision & (AMD_DR_B2 | AMD_DR_B3))
 		dctPhyDiag(); */
 
-	printk_debug(" done\n");
+	printk(BIOS_DEBUG, " done\n");
 }
 
 
Index: src/cpu/x86/cache/cache.c
===================================================================
--- src/cpu/x86/cache/cache.c	(revision 5263)
+++ src/cpu/x86/cache/cache.c	(working copy)
@@ -4,7 +4,7 @@
 void x86_enable_cache(void)
 {
 	post_code(0x60);
-	printk_info("Enabling cache\n");
+	printk(BIOS_INFO, "Enabling cache\n");
 	enable_cache();
 }
 
Index: src/cpu/x86/mtrr/mtrr.c
===================================================================
--- src/cpu/x86/mtrr/mtrr.c	(revision 5263)
+++ src/cpu/x86/mtrr/mtrr.c	(working copy)
@@ -98,7 +98,7 @@
 	base.hi = basek >> 22;
 	base.lo  = basek << 10;
 
-	printk_spew("ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
+	printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
 
 	if (sizek < 4*1024*1024) {
 		mask.hi = address_mask_high;
@@ -236,12 +236,12 @@
 		/* If there's no MTRR hole, this function will bail out
 		 * here when called for the hole.
 		 */
-		printk_spew("Zero-sized MTRR range @%ldKB\n", range_startk);
+		printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk);
 		return reg;
 	}
 
 	if (reg >= BIOS_MTRRS) {
-		printk_err("Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
+		printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
 				range_startk >>10, range_sizek >> 10,
 				(type==MTRR_TYPE_UNCACHEABLE)?"UC":
 				   ((type==MTRR_TYPE_WRBACK)?"WB":"Other") );
@@ -258,7 +258,7 @@
 			align = max_align;
 		}
 		sizek = 1 << align;
-		printk_debug("Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
+		printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
 			reg, range_startk >>10, sizek >> 10,
 			(type==MTRR_TYPE_UNCACHEABLE)?"UC":
 			    ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -267,7 +267,7 @@
 		range_startk += sizek;
 		range_sizek -= sizek;
 		if (reg >= BIOS_MTRRS) {
-			printk_err("Running out of variable MTRRs!\n");
+			printk(BIOS_ERR, "Running out of variable MTRRs!\n");
 			break;
 		}
 	}
@@ -295,7 +295,7 @@
 	if (start_mtrr >= NUM_FIXED_RANGES) {
 		return;
 	}
-	printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
+	printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n",
 		start_mtrr, last_mtrr);
 	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
 	
@@ -357,7 +357,7 @@
 #endif
 	}
 	/* Allocate an msr */  
-	printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
+	printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
 	state->range_startk = basek;
 	state->range_sizek  = sizek;
 }
@@ -369,9 +369,9 @@
          * and clear out the mtrrs.
          */
 
-        printk_debug("\n");
+        printk(BIOS_DEBUG, "\n");
         /* Initialized the fixed_mtrrs to uncached */
-        printk_debug("Setting fixed MTRRs(%d-%d) Type: UC\n",
+        printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n",
 	        0, NUM_FIXED_RANGES);
         set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
 
@@ -380,10 +380,10 @@
         search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_fixed_mtrr_resource, NULL);
-        printk_debug("DONE fixed MTRRs\n");
+        printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
 
         /* enable fixed MTRR */
-        printk_spew("call enable_fixed_mtrr()\n");
+        printk(BIOS_SPEW, "call enable_fixed_mtrr()\n");
         enable_fixed_mtrr();
 
 }
@@ -421,7 +421,7 @@
 #if (CONFIG_GFXUMA == 1) /* UMA or SP. */
 	// For now we assume the UMA space is at the end of memory
 	if (var_state.hole_startk || var_state.hole_sizek) {
-		printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
+		printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
 	} else {
 		// Increase the base range and set up UMA as an UC hole instead
 		var_state.range_sizek += (uma_memory_size >> 10);
@@ -437,15 +437,15 @@
 	var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
 		var_state.hole_sizek,  0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
 #endif
-	printk_debug("DONE variable MTRRs\n");
-	printk_debug("Clear out the extra MTRR's\n");
+	printk(BIOS_DEBUG, "DONE variable MTRRs\n");
+	printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
 	while(var_state.reg < MTRRS) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
-	printk_spew("call enable_var_mtrr()\n");
+	printk(BIOS_SPEW, "call enable_var_mtrr()\n");
 	enable_var_mtrr();
-	printk_spew("Leave %s\n", __func__);
+	printk(BIOS_SPEW, "Leave %s\n", __func__);
 	post_code(0x6A);
 }
 
@@ -460,24 +460,24 @@
 {
 	/* Only Pentium Pro and later have MTRR */
 	msr_t msr;
-	printk_debug("\nMTRR check\n");
+	printk(BIOS_DEBUG, "\nMTRR check\n");
 
 	msr = rdmsr(0x2ff);
 	msr.lo >>= 10;
 
-	printk_debug("Fixed MTRRs   : ");
+	printk(BIOS_DEBUG, "Fixed MTRRs   : ");
 	if (msr.lo & 0x01)
-		printk_debug("Enabled\n");
+		printk(BIOS_DEBUG, "Enabled\n");
 	else
-		printk_debug("Disabled\n");
+		printk(BIOS_DEBUG, "Disabled\n");
 
-	printk_debug("Variable MTRRs: ");
+	printk(BIOS_DEBUG, "Variable MTRRs: ");
 	if (msr.lo & 0x02)
-		printk_debug("Enabled\n");
+		printk(BIOS_DEBUG, "Enabled\n");
 	else
-		printk_debug("Disabled\n");
+		printk(BIOS_DEBUG, "Disabled\n");
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 	post_code(0x93);
 	return ((int) msr.lo);
Index: src/cpu/x86/pae/pgtbl.c
===================================================================
--- src/cpu/x86/pae/pgtbl.c	(revision 5263)
+++ src/cpu/x86/pae/pgtbl.c	(working copy)
@@ -66,7 +66,7 @@
                 #warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n"
 #endif
 	if(x_end > (CONFIG_RAMTOP)) {
-                        printk_debug("map_2M_page: Please increase the CONFIG_RAMTOP more than %dK\n", x_end);
+                        printk(BIOS_DEBUG, "map_2M_page: Please increase the CONFIG_RAMTOP more than %dK\n", x_end);
                         die("Can not go on");
 	}
 #else
Index: src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- src/cpu/x86/lapic/lapic_cpu_init.c	(revision 5263)
+++ src/cpu/x86/lapic/lapic_cpu_init.c	(working copy)
@@ -66,7 +66,7 @@
 	/* copy the _secondary_start to the ram below 1M*/
 	memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
 
-	printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
+	printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
 #endif
 }
 
@@ -80,7 +80,7 @@
 	 * Starting actual IPI sequence...
 	 */
 
-	printk_spew("Asserting INIT.\n");
+	printk(BIOS_SPEW, "Asserting INIT.\n");
 
 	/*
 	 * Turn INIT on target chip
@@ -94,28 +94,28 @@
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
 				| LAPIC_DM_INIT);
 
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 	timeout = 0;
 	do {
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("CPU %ld: First apic write timed out. Disabling\n",
+		printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n",
 			 apicid);
 		// too bad.
-		printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+		printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 		if (lapic_read(LAPIC_ESR)) {
-			printk_err("Try to reset ESR\n");
+			printk(BIOS_ERR, "Try to reset ESR\n");
 			lapic_write_around(LAPIC_ESR, 0);
-			printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+			printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 		}
 		return 0;
 	}
 	mdelay(10);
 
-	printk_spew("Deasserting INIT.\n");
+	printk(BIOS_SPEW, "Deasserting INIT.\n");
 
 	/* Target chip */
 	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
@@ -123,15 +123,15 @@
 	/* Send IPI */
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 	timeout = 0;
 	do {
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("CPU %ld: Second apic write timed out. Disabling\n",
+		printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n",
 			 apicid);
 		// too bad.
 		return 0;
@@ -148,16 +148,16 @@
 	/*
 	 * Run STARTUP IPI loop.
 	 */
-	printk_spew("#startup loops: %d.\n", num_starts);
+	printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
 
 	maxlvt = 4;
 
 	for (j = 1; j <= num_starts; j++) {
-		printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid);
+		printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
 		lapic_read_around(LAPIC_SPIV);
 		lapic_write(LAPIC_ESR, 0);
 		lapic_read(LAPIC_ESR);
-		printk_spew("After apic_write.\n");
+		printk(BIOS_SPEW, "After apic_write.\n");
 
 		/*
 		 * STARTUP IPI
@@ -176,12 +176,12 @@
 		 */
 		udelay(300);
 
-		printk_spew("Startup point 1.\n");
+		printk(BIOS_SPEW, "Startup point 1.\n");
 
-		printk_spew("Waiting for send to finish...\n");
+		printk(BIOS_SPEW, "Waiting for send to finish...\n");
 		timeout = 0;
 		do {
-			printk_spew("+");
+			printk(BIOS_SPEW, "+");
 			udelay(100);
 			send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 		} while (send_status && (timeout++ < 1000));
@@ -201,11 +201,11 @@
 		if (send_status || accept_status)
 			break;
 	}
-	printk_spew("After Startup.\n");
+	printk(BIOS_SPEW, "After Startup.\n");
 	if (send_status)
-		printk_warning("APIC never delivered???\n");
+		printk(BIOS_WARNING, "APIC never delivered???\n");
 	if (accept_status)
-		printk_warning("APIC delivery error (%lx).\n", accept_status);
+		printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status);
 	if (send_status || accept_status)
 		return 0;
 	return 1;
@@ -294,7 +294,7 @@
 
 	id = lapic_read(LAPIC_ID) >> 24;
 
-	printk_debug("CPU %ld going down...\n", id);
+	printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
 
 	/* send an LAPIC INIT to myself */
 	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
@@ -302,37 +302,37 @@
 
 	/* wait for the ipi send to finish */
 #if 0
-	// When these two printk_spew calls are not removed, the
+	// When these two printk(BIOS_SPEW, ...) calls are not removed, the
 	// machine will hang when log level is SPEW. Why?
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 #endif
 	timeout = 0;
 	do {
 #if 0
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 #endif
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("timed out\n");
+		printk(BIOS_ERR, "timed out\n");
 	}
 	mdelay(10);
 
-	printk_spew("Deasserting INIT.\n");
+	printk(BIOS_SPEW, "Deasserting INIT.\n");
 	/* Deassert the LAPIC INIT */
 	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 	lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 
-	printk_spew("Waiting for send to finish...\n");
+	printk(BIOS_SPEW, "Waiting for send to finish...\n");
 	timeout = 0;
 	do {
-		printk_spew("+");
+		printk(BIOS_SPEW, "+");
 		udelay(100);
 		send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (send_status && (timeout++ < 1000));
 	if (timeout >= 1000) {
-		printk_err("timed out\n");
+		printk(BIOS_ERR, "timed out\n");
 	}
 
 	while(1) {
@@ -387,7 +387,7 @@
 
 		if (!start_cpu(cpu)) {
 			/* Record the error in cpu? */
-			printk_err("CPU 0x%02x would not start!\n",
+			printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
 				cpu->path.apic.apic_id);
 		}
 #if CONFIG_SERIAL_CPU_INIT == 1
@@ -408,7 +408,7 @@
 	active_count = atomic_read(&active_cpus);
 	while(active_count > 1) {
 		if (active_count != old_active_count) {
-			printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
+			printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1);
 			old_active_count = active_count;
 		}
 		udelay(10);
@@ -419,11 +419,11 @@
 			continue;
 		}
 		if (!cpu->initialized) {
-			printk_err("CPU 0x%02x did not initialize!\n",
+			printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
 				cpu->path.apic.apic_id);
 		}
 	}
-	printk_debug("All AP CPUs stopped\n");
+	printk(BIOS_DEBUG, "All AP CPUs stopped\n");
 }
 
 #else /* CONFIG_SMP */
Index: src/cpu/x86/lapic/lapic.c
===================================================================
--- src/cpu/x86/lapic/lapic.c	(revision 5263)
+++ src/cpu/x86/lapic/lapic.c	(working copy)
@@ -17,7 +17,7 @@
 	/* Only Pentium Pro and later have those MSR stuff */
 	msr_t msr;
 
-	printk_info("Setting up local apic...");
+	printk(BIOS_INFO, "Setting up local apic...");
 
 	/* Enable the local apic */
 	msr = rdmsr(LAPIC_BASE_MSR);
@@ -55,18 +55,18 @@
 			LAPIC_DELIVERY_MODE_NMI)
 		);
 
-	printk_debug(" apic_id: 0x%02lx ", lapicid());
+	printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid());
 
 #else /* !NEED_LLAPIC */
 	/* Only Pentium Pro and later have those MSR stuff */
 	msr_t msr;
 
-	printk_info("Disabling local apic...");
+	printk(BIOS_INFO, "Disabling local apic...");
 
 	msr = rdmsr(LAPIC_BASE_MSR);
 	msr.lo &= ~LAPIC_BASE_MSR_ENABLE;
 	wrmsr(LAPIC_BASE_MSR, msr);
 #endif /* !NEED_LAPIC */
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 	post_code(0x9b);
 }
Index: src/cpu/x86/tsc/delay_tsc.c
===================================================================
--- src/cpu/x86/tsc/delay_tsc.c	(revision 5263)
+++ src/cpu/x86/tsc/delay_tsc.c	(working copy)
@@ -78,7 +78,7 @@
 	 * 32 bits..
 	 */
 bad_ctc:
-	printk_err("bad_ctc\n");
+	printk(BIOS_ERR, "bad_ctc\n");
 	return 0;
 }
 
@@ -104,7 +104,7 @@
 	unsigned long long start, end, delta;
 	unsigned long result, count;
 	
-	printk_spew("Calibrating delay loop...\n");
+	printk(BIOS_SPEW, "Calibrating delay loop...\n");
 	start = rdtscll();
 	// no udivdi3 because we don't like libgcc. (only in x86emu)
 	// so we count to 1<< 20 and then right shift 20
@@ -128,10 +128,10 @@
 	delta >>= 20;
 	// save this for microsecond timing.
 	result = delta;
-	printk_spew("end %llx, start %llx\n", end, start);
-	printk_spew("32-bit delta %ld\n", (unsigned long) delta);
+	printk(BIOS_SPEW, "end %llx, start %llx\n", end, start);
+	printk(BIOS_SPEW, "32-bit delta %ld\n", (unsigned long) delta);
 	
-	printk_spew("%s 32-bit result is %ld\n",
+	printk(BIOS_SPEW, "%s 32-bit result is %ld\n",
 			__func__,
 			result);
 	return delta;
@@ -144,7 +144,7 @@
 {
 	if (!clocks_per_usec) {
 		clocks_per_usec = calibrate_tsc();
-		printk_info("clocks_per_usec: %lu\n", clocks_per_usec);
+		printk(BIOS_INFO, "clocks_per_usec: %lu\n", clocks_per_usec);
 	}
 }
 
Index: src/cpu/x86/smm/smihandler.c
===================================================================
--- src/cpu/x86/smm/smihandler.c	(revision 5263)
+++ src/cpu/x86/smm/smihandler.c	(working copy)
@@ -68,7 +68,7 @@
 	/* If a handler function handled a given IO trap, it
 	 * shall return a non-zero value
 	 */
-        printk_debug("SMI function trap 0x%x: ", smif);
+        printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif);
 
 	if (southbridge_io_trap_handler(smif))
 		return;
@@ -76,7 +76,7 @@
 	if (mainboard_io_trap_handler(smif))
 		return;
 
-	printk_debug("Unknown function\n");
+	printk(BIOS_DEBUG, "Unknown function\n");
 }
 
 /**
@@ -111,7 +111,7 @@
 
 	console_init();
 
-	printk_spew("\nSMI# #%d\n", node);
+	printk(BIOS_SPEW, "\nSMI# #%d\n", node);
 
 	switch (smm_revision) {
 	case 0x00030002:
@@ -131,8 +131,8 @@
 			(0xa8000 + 0x7e00 - (node * 0x400));
 		break;
 	default:
-		printk_debug("smm_revision: 0x%08x\n", smm_revision);
-		printk_debug("SMI# not supported on your CPU\n");
+		printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
+		printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
 		/* Don't release lock, so no further SMI will happen,
 		 * if we don't handle it anyways.
 		 */
Index: src/cpu/intel/model_106cx/model_106cx_init.c
===================================================================
--- src/cpu/intel/model_106cx/model_106cx_init.c	(revision 5263)
+++ src/cpu/intel/model_106cx/model_106cx_init.c	(working copy)
@@ -171,7 +171,7 @@
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
-	printk_info("CPU: %s.\n", processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
Index: src/cpu/intel/model_106cx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram_disable.c	(revision 5263)
+++ src/cpu/intel/model_106cx/cache_as_ram_disable.c	(working copy)
@@ -36,12 +36,12 @@
         	        "movl   %%esp, %0\n\t"
 	                : "=a" (v_esp)
 	        );
-	        printk_spew("v_esp=%08x\r\n", v_esp);
+	        printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp);
         }
 
 cpu_reset_x:
 
-        printk_spew("cpu_reset = %08x\r\n",cpu_reset);
+        printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset);
 
 	if(cpu_reset == 0) {
 	        print_spew("Clearing initial memory region: ");
Index: src/cpu/intel/model_6ex/model_6ex_init.c
===================================================================
--- src/cpu/intel/model_6ex/model_6ex_init.c	(revision 5263)
+++ src/cpu/intel/model_6ex/model_6ex_init.c	(working copy)
@@ -200,7 +200,7 @@
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
-	printk_info("CPU: %s.\n", processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
Index: src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram_disable.c	(revision 5263)
+++ src/cpu/intel/model_6ex/cache_as_ram_disable.c	(working copy)
@@ -37,13 +37,13 @@
         	"movl   %%esp, %0\n"
 		: "=a" (v_esp)
 	);
-	printk_spew("v_esp=%08x\n", v_esp);
+	printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
 #endif
 
 cpu_reset_x:
 
-        printk_spew("cpu_reset = %08x\n", cpu_reset);
-	printk_spew("No cache as ram now - ");
+        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
+	printk(BIOS_SPEW, "No cache as ram now - ");
 
 	/* store cpu_reset to ebx */
         __asm__ volatile (
@@ -83,5 +83,5 @@
 	}
 
 	/* We will not return */
-	printk_debug("sorry. parachute did not open.\n");
+	printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
 }
Index: src/cpu/intel/model_6fx/model_6fx_init.c
===================================================================
--- src/cpu/intel/model_6fx/model_6fx_init.c	(revision 5263)
+++ src/cpu/intel/model_6fx/model_6fx_init.c	(working copy)
@@ -227,7 +227,7 @@
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
-	printk_info("CPU: %s.\n", processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
Index: src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram_disable.c	(revision 5263)
+++ src/cpu/intel/model_6fx/cache_as_ram_disable.c	(working copy)
@@ -38,13 +38,13 @@
         	"movl   %%esp, %0\n"
 		: "=a" (v_esp)
 	);
-	printk_spew("v_esp=%08x\n", v_esp);
+	printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
 #endif
 
 cpu_reset_x:
 
-        printk_spew("cpu_reset = %08x\n", cpu_reset);
-	printk_spew("No cache as ram now - ");
+        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
+	printk(BIOS_SPEW, "No cache as ram now - ");
 
 	/* store cpu_reset to ebx */
         __asm__ volatile (
@@ -84,5 +84,5 @@
 	}
 
 	/* We will not return */
-	printk_debug("sorry. parachute did not open.\n");
+	printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
 }
Index: src/cpu/intel/speedstep/acpi.c
===================================================================
--- src/cpu/intel/speedstep/acpi.c	(revision 5263)
+++ src/cpu/intel/speedstep/acpi.c	(working copy)
@@ -56,7 +56,7 @@
 		case 3: return 166;
 		case 5: return 100;
 	}
-	printk_debug("Warning: No supported FSB frequency. Assuming 200MHz\n");
+	printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
 	return 200;
 }
 
@@ -68,7 +68,7 @@
 	int totalcores = determine_total_number_of_cores();
 	int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
 	int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
-	printk_debug("Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
 
 	for (cpuID=1; cpuID <=numcpus; cpuID++) {
 		for (coreID=1; coreID<=cores_per_package; coreID++) {
@@ -93,7 +93,7 @@
 			int vid_max=msr.lo & 0x3f;
 			int clock_max=get_fsb()*busratio_max;
 			int clock_min=get_fsb()*busratio_min;
-			printk_debug("clocks between %d and %d MHz.\n", clock_min, clock_max);
+			printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
 #define MEROM_MIN_POWER 16000
 #define MEROM_MAX_POWER 35000
 			int power_max=MEROM_MAX_POWER;
@@ -104,7 +104,7 @@
 				busratio_step <<= 1;
 				num_states >>= 1;
 			}
-			printk_debug("adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max);
+			printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max);
 			int vid_step=(vid_max-vid_min)/num_states;
 			int power_step=(power_max-power_min)/num_states;
 			int clock_step=(clock_max-clock_min)/num_states;
Index: src/cpu/intel/model_1067x/model_1067x_init.c
===================================================================
--- src/cpu/intel/model_1067x/model_1067x_init.c	(revision 5263)
+++ src/cpu/intel/model_1067x/model_1067x_init.c	(working copy)
@@ -210,7 +210,7 @@
 
 	/* Print processor name */
 	fill_processor_name(processor_name);
-	printk_info("CPU: %s.\n", processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
Index: src/cpu/intel/hyperthreading/intel_sibling.c
===================================================================
--- src/cpu/intel/hyperthreading/intel_sibling.c	(revision 5263)
+++ src/cpu/intel/hyperthreading/intel_sibling.c	(working copy)
@@ -31,7 +31,7 @@
 	}
 
 #if 1
-	printk_debug("CPU: %u %d siblings\n",
+	printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
 		cpu->path.apic.apic_id,
 		siblings);
 #endif
@@ -61,14 +61,14 @@
 		}
 
 #if 1
-		printk_debug("CPU: %u has sibling %u\n", 
+		printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", 
 			cpu->path.apic.apic_id,
 			new->path.apic.apic_id);
 #endif
 		/* Start the new cpu */
 		if (!start_cpu(new)) {
 			/* Record the error in cpu? */
-			printk_err("CPU %u would not start!\n",
+			printk(BIOS_ERR, "CPU %u would not start!\n",
 				new->path.apic.apic_id);
 		}
 	}
Index: src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- src/cpu/emulation/qemu-x86/northbridge.c	(revision 5263)
+++ src/cpu/emulation/qemu-x86/northbridge.c	(working copy)
@@ -81,14 +81,14 @@
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk_err("ERROR! register 0x%x is not set!\n",
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 					ramregs[i]);
 		}
 		if (rambits == 0) {
-			printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n");
+			printk(BIOS_ERR, "RAM size config registers are empty; defaulting to 64 MBytes\n");
 			rambits = 8;
 		}
-		printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 		tomk = rambits*8*1024;
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
Index: src/mainboard/iwill/dk8_htx/acpi_tables.c
===================================================================
--- src/mainboard/iwill/dk8_htx/acpi_tables.c	(revision 5263)
+++ src/mainboard/iwill/dk8_htx/acpi_tables.c	(working copy)
@@ -30,9 +30,9 @@
         print_debug("dump_mem:");
         for(i=start;i<end;i++) {
                 if((i & 0xf)==0) {
-                        printk_debug("\n%08x:", i);
+                        printk(BIOS_DEBUG, "\n%08x:", i);
                 }
-                printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+                printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
         }
         print_debug("\n");
  }
@@ -211,7 +211,7 @@
 	start   = ( start + 0x0f ) & -0x10;
 	current = start;
 	
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -228,14 +228,14 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp,hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current+=madt->header.length;
@@ -243,21 +243,21 @@
 
 
 	/* SRAT */
-        printk_debug("ACPI:    * SRAT\n");
+        printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
         srat = (acpi_srat_t *) current;
         acpi_create_srat(srat);
         current+=srat->header.length;
         acpi_add_table(rsdp,srat);
 
 	/* SLIT */
-        printk_debug("ACPI:    * SLIT\n");
+        printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
         slit = (acpi_slit_t *) current;
         acpi_create_slit(slit);
         current+=slit->header.length;
         acpi_add_table(rsdp,slit);
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -277,7 +277,7 @@
                 else {
                         c  = (uint8_t) ('A' + i - 1 - 6);
                 }
-                printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
+                printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
                 current   = ( current + 0x07) & -0x08;
                 ssdtx = (acpi_header_t *)current;
                 switch(sysconf.hcid[i]) {
@@ -305,21 +305,21 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *)current;
 	current += ((acpi_header_t *)AmlCode)->length;
 	memcpy((void *)dsdt,(void *)AmlCode, \
 			((acpi_header_t *)AmlCode)->length);
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	/* FDAT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -327,29 +327,29 @@
 	acpi_add_table(rsdp,fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-        printk_debug("rsdt\n");
+        printk(BIOS_DEBUG, "rsdt\n");
         dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-        printk_debug("madt\n");
+        printk(BIOS_DEBUG, "madt\n");
         dump_mem(madt, ((void *)madt) + madt->header.length);
 
-        printk_debug("srat\n");
+        printk(BIOS_DEBUG, "srat\n");
         dump_mem(srat, ((void *)srat) + srat->header.length);
 
-        printk_debug("slit\n");
+        printk(BIOS_DEBUG, "slit\n");
         dump_mem(slit, ((void *)slit) + slit->header.length);
 
-        printk_debug("ssdt\n");
+        printk(BIOS_DEBUG, "ssdt\n");
         dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-        printk_debug("fadt\n");
+        printk(BIOS_DEBUG, "fadt\n");
         dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/iwill/dk8_htx/fadt.c
===================================================================
--- src/mainboard/iwill/dk8_htx/fadt.c	(revision 5263)
+++ src/mainboard/iwill/dk8_htx/fadt.c	(working copy)
@@ -13,7 +13,7 @@
 
 	acpi_header_t *header=&(fadt->header);
 
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt,0,sizeof(acpi_fadt_t));
Index: src/mainboard/iwill/dk8_htx/mptable.c
===================================================================
--- src/mainboard/iwill/dk8_htx/mptable.c	(revision 5263)
+++ src/mainboard/iwill/dk8_htx/mptable.c	(working copy)
@@ -212,7 +212,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/iwill/dk8_htx/irq_tables.c
===================================================================
--- src/mainboard/iwill/dk8_htx/irq_tables.c	(revision 5263)
+++ src/mainboard/iwill/dk8_htx/irq_tables.c	(working copy)
@@ -58,7 +58,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -98,13 +98,13 @@
         }
 
 //pci bridge
-        printk_debug("setting Onboard AMD Southbridge \n");
+        printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n");
         static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
         pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
 	write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Onboard AMD USB \n");
+        printk(BIOS_DEBUG, "setting Onboard AMD USB \n");
         static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
         pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
         write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
@@ -138,7 +138,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/iwill/dk8_htx/get_bus_conf.c
===================================================================
--- src/mainboard/iwill/dk8_htx/get_bus_conf.c	(revision 5263)
+++ src/mainboard/iwill/dk8_htx/get_bus_conf.c	(working copy)
@@ -112,11 +112,11 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
-//		printk_debug("bus_isa=%d\n",bus_isa);
+//		printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
         }
 	else {
-                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
         }
 
         /* 8132-1 */
@@ -125,7 +125,7 @@
                 m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
         }
 
         /* 8132-2 */
@@ -135,11 +135,11 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
-//              printk_debug("bus_isa=%d\n",bus_isa);
+//              printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
         }
 
         /* HT chain 1 */
@@ -165,7 +165,7 @@
                                 m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
                         }
                         else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
                         }
 
                         /* 8132-2 */
@@ -174,10 +174,10 @@
                                 m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
                                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                                 m->bus_isa++;
-                //              printk_debug("bus_isa=%d\n",bus_isa);
+                //              printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
                                 }
                         else {
-                                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
+                                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
                         }
 
                         break;
@@ -191,12 +191,12 @@
 
                         if (dev) {
                                 m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-        //                        printk_debug("bus_8151_1=%d\n",bus_8151[j][1]);
+        //                        printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]);
                                 m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                                 m->bus_isa++;
                         }
                         else {
-                                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
+                                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
                         }
 
                         break;
Index: src/mainboard/iwill/dk8s2/mptable.c
===================================================================
--- src/mainboard/iwill/dk8s2/mptable.c	(revision 5263)
+++ src/mainboard/iwill/dk8s2/mptable.c	(working copy)
@@ -46,7 +46,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
 			bus_8111_1 = 4;
 			bus_isa = 5;
@@ -58,7 +58,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
 			bus_8131_1 = 2;
 		}
@@ -69,7 +69,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_8131_2 = 3;
 		}
@@ -218,7 +218,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/iwill/dk8x/mptable.c
===================================================================
--- src/mainboard/iwill/dk8x/mptable.c	(revision 5263)
+++ src/mainboard/iwill/dk8x/mptable.c	(working copy)
@@ -46,7 +46,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
 			bus_8111_1 = 4;
 			bus_isa = 5;
@@ -58,7 +58,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
 			bus_8131_1 = 2;
 		}
@@ -69,7 +69,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_8131_2 = 3;
 		}
@@ -218,7 +218,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/broadcom/blast/mptable.c
===================================================================
--- src/mainboard/broadcom/blast/mptable.c	(revision 5263)
+++ src/mainboard/broadcom/blast/mptable.c	(working copy)
@@ -177,7 +177,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/broadcom/blast/irq_tables.c
===================================================================
--- src/mainboard/broadcom/blast/irq_tables.c	(revision 5263)
+++ src/mainboard/broadcom/blast/irq_tables.c	(working copy)
@@ -60,7 +60,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -99,7 +99,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/broadcom/blast/get_bus_conf.c
===================================================================
--- src/mainboard/broadcom/blast/get_bus_conf.c	(revision 5263)
+++ src/mainboard/broadcom/blast/get_bus_conf.c	(working copy)
@@ -86,12 +86,12 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
 	                bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 	                bus_isa++;
-//        	        printk_debug("bus_isa=%d\n",bus_isa);
+//        	        printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
 		}
         }
 	else {
-                printk_debug("ERROR - could not find PCI %02x:07.0, using defaults\n", bus_bcm5785_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:07.0, using defaults\n", bus_bcm5785_0);
         }
 
 		/* bcm5780 */
@@ -102,12 +102,12 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                         bus_isa++;
-//                      printk_debug("bus_isa=%d\n",bus_isa);
+//                      printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
 
 		}
         	else {
-                	printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_bcm5780[i]);
+                	printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_bcm5780[i]);
 	        }
 	}
 
Index: src/mainboard/thomson/ip1000/mainboard_smi.c
===================================================================
--- src/mainboard/thomson/ip1000/mainboard_smi.c	(revision 5263)
+++ src/mainboard/thomson/ip1000/mainboard_smi.c	(working copy)
@@ -26,6 +26,6 @@
 
 int mainboard_io_trap_handler(int smif)
 {
-	printk_debug("MAINBOARD IO TRAP HANDLER!\n");
+	printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
 	return 1;
 }
Index: src/mainboard/supermicro/x6dai_g/mptable.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/x6dai_g/mptable.c	(working copy)
@@ -44,7 +44,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 			bus_6300 = 5;
 			bus_isa = 6;
 		}
@@ -128,7 +128,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/h8dmr/mptable.c
===================================================================
--- src/mainboard/supermicro/h8dmr/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/h8dmr/mptable.c	(working copy)
@@ -162,7 +162,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/h8dmr/irq_tables.c
===================================================================
--- src/mainboard/supermicro/h8dmr/irq_tables.c	(revision 5263)
+++ src/mainboard/supermicro/h8dmr/irq_tables.c	(working copy)
@@ -75,7 +75,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -112,7 +112,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/supermicro/h8dmr/get_bus_conf.c
===================================================================
--- src/mainboard/supermicro/h8dmr/get_bus_conf.c	(revision 5263)
+++ src/mainboard/supermicro/h8dmr/get_bus_conf.c	(working copy)
@@ -114,7 +114,7 @@
                         bus_mcp55[2]++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
 
                         bus_mcp55[1] = 2;
                         bus_mcp55[2] = 3;
@@ -128,7 +128,7 @@
         	                bus_isa++;
 	                }
         	        else {
-                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
+                	        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
 	                        bus_isa = bus_mcp55[i-1]+1;
         	        }
 		}
Index: src/mainboard/supermicro/x6dhe_g/mptable.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/x6dhe_g/mptable.c	(working copy)
@@ -45,7 +45,7 @@
 			bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1c.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
 
 			bus_esb6300_2 = 6;
 		}
@@ -57,7 +57,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 
 			bus_esb6300_1 = 7;
 			bus_isa = 8;
@@ -69,7 +69,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
 
 			bus_pxhd_1 = 2;
 		}
@@ -80,7 +80,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_pxhd_2 = 3;
 		}
@@ -108,8 +108,8 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
-			printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
+			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
 		/* PXHd apic 5 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
@@ -120,8 +120,8 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
-			printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
+			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
 	}
 
@@ -188,7 +188,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/h8dme/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/romstage.c	(revision 5263)
+++ src/mainboard/supermicro/h8dme/romstage.c	(working copy)
@@ -102,7 +102,7 @@
 		int j;
 		if (smbus_read_byte(device, 0) < 0)
 			continue;
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for (j = 0; j < 256; j++) {
 			int status;
 			unsigned char byte;
@@ -111,10 +111,10 @@
 				break;
 			}
 			if ((j & 0xf) == 0) {
-				printk_debug("\r\n%02x: ", j);
+				printk(BIOS_DEBUG, "\r\n%02x: ", j);
 			}
 			byte = status & 0xff;
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		print_debug("\r\n");
 	}
Index: src/mainboard/supermicro/h8dme/mptable.c
===================================================================
--- src/mainboard/supermicro/h8dme/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/h8dme/mptable.c	(working copy)
@@ -162,7 +162,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/h8dme/irq_tables.c
===================================================================
--- src/mainboard/supermicro/h8dme/irq_tables.c	(revision 5263)
+++ src/mainboard/supermicro/h8dme/irq_tables.c	(working copy)
@@ -75,7 +75,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -112,7 +112,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/supermicro/h8dme/get_bus_conf.c
===================================================================
--- src/mainboard/supermicro/h8dme/get_bus_conf.c	(revision 5263)
+++ src/mainboard/supermicro/h8dme/get_bus_conf.c	(working copy)
@@ -114,7 +114,7 @@
                         bus_mcp55[2]++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
 
                         bus_mcp55[1] = 2;
                         bus_mcp55[2] = 3;
@@ -128,7 +128,7 @@
         	                bus_isa++;
 	                }
         	        else {
-                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
+                	        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
 	                        bus_isa = bus_mcp55[i-1]+1;
         	        }
 		}
Index: src/mainboard/supermicro/h8dmr_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c	(revision 5263)
+++ src/mainboard/supermicro/h8dmr_fam10/romstage.c	(working copy)
@@ -197,17 +197,17 @@
 
         uart_init();
         console_init();
-  printk_debug("\n");
+  printk(BIOS_DEBUG, "\n");
 
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
  val = cpuid_eax(1);
- printk_debug("BSP Family_Model: %08x \n", val);
- printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
- printk_debug("bsp_apicid = %02x \n", bsp_apicid);
- printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+ printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 
  /* Setup sysinfo defaults */
  set_sysinfo_in_ram(0);
@@ -238,7 +238,7 @@
         wait_all_core0_started();
 #if CONFIG_LOGICAL_CPUS==1
  /* Core0 on each node is configured. Now setup any additional cores. */
- printk_debug("start_other_cores()\n");
+ printk(BIOS_DEBUG, "start_other_cores()\n");
         start_other_cores();
  post_code(0x37);
         wait_all_other_cores_started(bsp_apicid);
@@ -248,7 +248,7 @@
 
 #if FAM10_SET_FIDVID == 1
  msr = rdmsr(0xc0010071);
- printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
  /* FIXME: The sb fid change may survive the warm reset and only
   * need to be done once.*/
@@ -266,7 +266,7 @@
 
  /* show final fid and vid */
  msr=rdmsr(0xc0010071);
- printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 #endif
 
  wants_reset = mcp55_early_setup_x();
@@ -279,17 +279,17 @@
         }
 
  if (wants_reset)
-   printk_debug("mcp55_early_setup_x wanted additional reset!\n");
+   printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 
  post_code(0x3B);
 
 /* It's the time to set ctrl in sysinfo now; */
-printk_debug("fill_mem_ctrl()\n");
+printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
 post_code(0x3D);
 
-//printk_debug("enable_smbus()\n");
+//printk(BIOS_DEBUG, "enable_smbus()\n");
 //        enable_smbus(); /* enable in sio_setup */
 
 post_code(0x3E);
@@ -299,11 +299,11 @@
 post_code(0x40);
 
 
- printk_debug("raminit_amdmct()\n");
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
  post_code(0x41);
 
-// printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
  post_code(0x42);  // Should never see this post code.
 
Index: src/mainboard/supermicro/h8dmr_fam10/mptable.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/h8dmr_fam10/mptable.c	(working copy)
@@ -149,7 +149,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/h8dmr_fam10/irq_tables.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/irq_tables.c	(revision 5263)
+++ src/mainboard/supermicro/h8dmr_fam10/irq_tables.c	(working copy)
@@ -76,7 +76,7 @@
 	addr &= ~15;
 
 	/* This table must be between 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -131,7 +131,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c	(revision 5263)
+++ src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c	(working copy)
@@ -102,7 +102,7 @@
 			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
 		for(i=2; i<8;i++) {
@@ -111,7 +111,7 @@
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			}
 			else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
 			}
 		}
 
@@ -124,7 +124,7 @@
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max)
 			m->bus_isa = busn_max + 1;
-		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+		printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
 	}
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
Index: src/mainboard/supermicro/h8qme_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/romstage.c	(revision 5263)
+++ src/mainboard/supermicro/h8qme_fam10/romstage.c	(working copy)
@@ -241,16 +241,16 @@
 	uart_init();
 	console_init();
 	write_GPIO();
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
  val = cpuid_eax(1);
- printk_debug("BSP Family_Model: %08x \n", val);
- printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
- printk_debug("bsp_apicid = %02x \n", bsp_apicid);
- printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+ printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 
  /* Setup sysinfo defaults */
  set_sysinfo_in_ram(0);
@@ -281,7 +281,7 @@
         wait_all_core0_started();
 #if CONFIG_LOGICAL_CPUS==1
  /* Core0 on each node is configured. Now setup any additional cores. */
- printk_debug("start_other_cores()\n");
+ printk(BIOS_DEBUG, "start_other_cores()\n");
         start_other_cores();
  post_code(0x37);
         wait_all_other_cores_started(bsp_apicid);
@@ -291,7 +291,7 @@
 
 #if FAM10_SET_FIDVID == 1
  msr = rdmsr(0xc0010071);
- printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
  /* FIXME: The sb fid change may survive the warm reset and only
   * need to be done once.*/
@@ -309,7 +309,7 @@
 
  /* show final fid and vid */
  msr=rdmsr(0xc0010071);
- printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 #endif
 
  wants_reset = mcp55_early_setup_x();
@@ -322,17 +322,17 @@
         }
 
  if (wants_reset)
-   printk_debug("mcp55_early_setup_x wanted additional reset!\n");
+   printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 
  post_code(0x3B);
 
 /* It's the time to set ctrl in sysinfo now; */
-printk_debug("fill_mem_ctrl()\n");
+printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
 post_code(0x3D);
 
-//printk_debug("enable_smbus()\n");
+//printk(BIOS_DEBUG, "enable_smbus()\n");
 //        enable_smbus(); /* enable in sio_setup */
 
 post_code(0x3E);
@@ -342,11 +342,11 @@
 post_code(0x40);
 
 
- printk_debug("raminit_amdmct()\n");
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
  post_code(0x41);
 
-// printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
  post_code(0x42);  // Should never see this post code.
 
Index: src/mainboard/supermicro/h8qme_fam10/mptable.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/h8qme_fam10/mptable.c	(working copy)
@@ -146,7 +146,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/h8qme_fam10/irq_tables.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/irq_tables.c	(revision 5263)
+++ src/mainboard/supermicro/h8qme_fam10/irq_tables.c	(working copy)
@@ -76,7 +76,7 @@
 	addr &= ~15;
 
 	/* This table must be between 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -131,7 +131,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c	(revision 5263)
+++ src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c	(working copy)
@@ -108,7 +108,7 @@
 			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
 		for(i=2; i<8;i++) {
@@ -117,7 +117,7 @@
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			}
 			else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
 			}
 		}
 
@@ -143,7 +143,7 @@
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max)
 			m->bus_isa = busn_max + 1;
-		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+		printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
 	}
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
Index: src/mainboard/supermicro/x6dhe_g2/mptable.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/x6dhe_g2/mptable.c	(working copy)
@@ -45,7 +45,7 @@
 			bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1c.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
 
 			bus_esb6300_2 = 6;
 		}
@@ -57,7 +57,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 
 			bus_esb6300_1 = 7;
 			bus_isa = 8;
@@ -69,7 +69,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
 
 			bus_pxhd_1 = 2;
 		}
@@ -80,7 +80,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_pxhd_2 = 3;
 		}
@@ -108,8 +108,8 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
-			printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
+			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
 		/* PXHd apic 5 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
@@ -120,8 +120,8 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
-			printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
+			printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 		}
 	}
 
@@ -188,7 +188,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/x6dhr_ig/mptable.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/x6dhr_ig/mptable.c	(working copy)
@@ -48,7 +48,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1f.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
 
 			bus_ich5r_1 = 9;
 			bus_isa = 10;
@@ -60,7 +60,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
 
 			bus_pxhd_1 = 3;
 		}
@@ -71,7 +71,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_pxhd_2 = 4;
 		}
@@ -83,7 +83,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
 
 			bus_pxhd_3 = 6;
 		}
@@ -94,7 +94,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_pxhd_4 = 7;
 		}
@@ -122,7 +122,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 2:00.1\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 2:00.1\n");
 		}
 		/* pxhd apic 4 */
 		dev = dev_find_slot(2, PCI_DEVFN(0x00,3));
@@ -133,7 +133,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 2:00.3\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 2:00.3\n");
 		}
 		/* pxhd apic 5 */
 		dev = dev_find_slot(5, PCI_DEVFN(0x00,1));
@@ -144,7 +144,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 5:00.1\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 5:00.1\n");
 		}
 		/* pxhd apic 8 */
 		dev = dev_find_slot(5, PCI_DEVFN(0x00,3));
@@ -155,7 +155,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 5:00.3\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 5:00.3\n");
 		}
 	}
 
@@ -222,7 +222,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/supermicro/x6dhr_ig2/mptable.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/mptable.c	(revision 5263)
+++ src/mainboard/supermicro/x6dhr_ig2/mptable.c	(working copy)
@@ -48,7 +48,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 
 			bus_ich5r_1 = 7;
 			bus_isa = 8;
@@ -60,7 +60,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
 
 			bus_pxhd_1 = 2;
 		}
@@ -71,7 +71,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.2, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
 
 			bus_pxhd_2 = 3;
 		}
@@ -83,7 +83,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:04.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
 
 			bus_pxhd_3 = 5;
 		}
@@ -94,7 +94,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:06.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
 
 			bus_pxhd_4 = 6;
 		}
@@ -122,7 +122,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 		}
 		/* pxhd apic 4 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
@@ -133,7 +133,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 		}
 	}	
 	/* ISA backward compatibility interrupts  */
@@ -205,7 +205,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/kontron/986lcd-m/mainboard_smi.c
===================================================================
--- src/mainboard/kontron/986lcd-m/mainboard_smi.c	(revision 5263)
+++ src/mainboard/kontron/986lcd-m/mainboard_smi.c	(working copy)
@@ -32,7 +32,7 @@
 {
 	switch (smif) {
 	case 0x99:
-		printk_debug("Sample\n");
+		printk(BIOS_DEBUG, "Sample\n");
 		gnvs->smif = 0;
 		break;
 	default:
Index: src/mainboard/kontron/986lcd-m/acpi_tables.c
===================================================================
--- src/mainboard/kontron/986lcd-m/acpi_tables.c	(revision 5263)
+++ src/mainboard/kontron/986lcd-m/acpi_tables.c	(working copy)
@@ -150,7 +150,7 @@
 	/* Align ACPI tables to 16byte */
 	ALIGN_CURRENT;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -173,7 +173,7 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
@@ -182,7 +182,7 @@
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
@@ -190,14 +190,14 @@
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	ALIGN_CURRENT;
@@ -213,7 +213,7 @@
 	/* Pack GNVS into the ACPI table area */
 	for (i=0; i < dsdt->length; i++) {
 		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
 			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
 			break;
 		}
@@ -232,18 +232,18 @@
 	dsdt->checksum = 0;
 	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
 
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
 
 #if CONFIG_HAVE_ACPI_SLIC
-	printk_debug("ACPI:     * SLIC\n");
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
 	slic = (acpi_header_t *)current;
 	current += acpi_create_slic(current);
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, slic);
 #endif
 
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 	ALIGN_CURRENT;
@@ -251,16 +251,16 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_debug("ACPI:     * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 	acpi_create_ssdt_generator(ssdt, "COREBOOT");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
 
-	printk_debug("current = %lx\n", current);
+	printk(BIOS_DEBUG, "current = %lx\n", current);
 
-	printk_debug("ACPI:     * DMI (Linux workaround)\n");
+	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
 	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
@@ -268,6 +268,6 @@
 	ALIGN_CURRENT;
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/kontron/986lcd-m/romstage.c
===================================================================
--- src/mainboard/kontron/986lcd-m/romstage.c	(revision 5263)
+++ src/mainboard/kontron/986lcd-m/romstage.c	(working copy)
@@ -68,7 +68,7 @@
 #include "southbridge/intel/i82801gx/i82801gx.h"
 static void setup_ich7_gpios(void)
 {
-	printk_debug(" GPIOS...");
+	printk(BIOS_DEBUG, " GPIOS...");
 	/* General Registers */
 	outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
 	outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
@@ -265,18 +265,18 @@
 	reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
 
 	if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) {
-		printk_debug("Disabling ethernet adapter 1.\n");
+		printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
 		reg32 |= FD_PCIE1;
 	}
 	if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) {
-		printk_debug("Disabling ethernet adapter 2.\n");
+		printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
 		reg32 |= FD_PCIE2;
 	} else {
 		if (reg32 & FD_PCIE1)
 			port_shuffle = 1;
 	}
 	if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) {
-		printk_debug("Disabling ethernet adapter 3.\n");
+		printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
 		reg32 |= FD_PCIE3;
 	} else {
 		if (reg32 & FD_PCIE1)
@@ -392,7 +392,7 @@
 	report_bist_failure(bist);
 
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk_debug("soft reset detected.\n");
+		printk(BIOS_DEBUG, "soft reset detected.\n");
 		boot_mode = 1;
 	}
 
@@ -403,10 +403,10 @@
 
 	/* Read PM1_CNT */
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
-	printk_debug("PM1_CNT: %08x\n", reg32);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
 #if CONFIG_HAVE_ACPI_RESUME
-		printk_debug("Resume from S3 detected.\n");
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 		boot_mode = 2;
 		/* Clear SLP_TYPE. This will break stage2 but
 		 * we care for that when we get there.
@@ -414,7 +414,7 @@
 		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 
 #else
-		printk_debug("Resume from S3 detected, but disabled.\n");
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 #endif
 	}
 
@@ -451,7 +451,7 @@
 		/* This will not work if TSEG is in place! */
 		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 
-		printk_debug("TOM: 0x%08x\n", tom);
+		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
 		//ram_check(0x00100000, tom);
 	}
Index: src/mainboard/kontron/986lcd-m/mptable.c
===================================================================
--- src/mainboard/kontron/986lcd-m/mptable.c	(revision 5263)
+++ src/mainboard/kontron/986lcd-m/mptable.c	(working copy)
@@ -59,7 +59,7 @@
 	firewire = dev_find_device(0x104c, 0x8023, 0);
 	if (firewire) {
 		firewire_bus = firewire->bus->secondary;
-		printk_spew("Firewire device is on bus %x\n",
+		printk(BIOS_SPEW, "Firewire device is on bus %x\n",
 				firewire_bus);
 		max_pci_bus = firewire_bus;
 	}
@@ -71,7 +71,7 @@
 		riser = dev_find_device(0x3388, 0x0022, 0);
 	if (riser) {
 		riser_bus = riser->link[0].secondary;
-		printk_spew("Riser bus is %x\n", riser_bus);
+		printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
 		max_pci_bus = riser_bus;
 	}
 
@@ -153,7 +153,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 
-	printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
 
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/kontron/986lcd-m/rtl8168.c
===================================================================
--- src/mainboard/kontron/986lcd-m/rtl8168.c	(revision 5263)
+++ src/mainboard/kontron/986lcd-m/rtl8168.c	(working copy)
@@ -27,7 +27,7 @@
 
 static void nic_init(struct device *dev)
 {
-	printk_debug("Initializing RTL8168 Gigabit Ethernet\n");
+	printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
 	// Nothing to do yet, but this has to be here to keep 
 	// coreboot from trying to execute an option ROM.
 }
Index: src/mainboard/kontron/986lcd-m/mainboard.c
===================================================================
--- src/mainboard/kontron/986lcd-m/mainboard.c	(revision 5263)
+++ src/mainboard/kontron/986lcd-m/mainboard.c	(working copy)
@@ -47,7 +47,7 @@
 #define BOOT_DISPLAY_EFP2	(1 << 6)
 #define BOOT_DISPLAY_LCD2	(1 << 7)
 
-	printk_debug("%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
 			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
 
 	switch (M.x86.R_AX) {
@@ -176,12 +176,12 @@
 
 	switch (cpufan_control) {
 	case FAN_CRUISE_CONTROL_SPEED:
-		printk_debug("Fan Cruise Control setting CPU fan to %d RPM\n",
+		printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
 				fan_speeds[cpufan_speed].fan_speed);
 		hwm_write(0x06, fan_speeds[cpufan_speed].fan_in);  // CPUFANIN target speed
 		break;
 	case FAN_CRUISE_CONTROL_THERMAL:
-		printk_debug("Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+		printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
 				temperatures[cpufan_temperature].deg_celsius,
 				temperatures[cpufan_temperature].deg_fahrenheit);
 		hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius);  // CPUFANIN target temperature
@@ -190,12 +190,12 @@
 
 	switch (sysfan_control) {
 	case FAN_CRUISE_CONTROL_SPEED:
-		printk_debug("Fan Cruise Control setting system fan to %d RPM\n",
+		printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
 				fan_speeds[sysfan_speed].fan_speed);
 		hwm_write(0x05, fan_speeds[sysfan_speed].fan_in);  // SYSFANIN target speed
 		break;
 	case FAN_CRUISE_CONTROL_THERMAL:
-		printk_debug("Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+		printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
 				temperatures[sysfan_temperature].deg_celsius,
 				temperatures[sysfan_temperature].deg_fahrenheit);
 		hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
Index: src/mainboard/kontron/kt690/fadt.c
===================================================================
--- src/mainboard/kontron/kt690/fadt.c	(revision 5263)
+++ src/mainboard/kontron/kt690/fadt.c	(working copy)
@@ -46,7 +46,7 @@
 	acpi_header_t *header = &(fadt->header);
 
 	pm_base &= 0xFFFF;
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/mainboard/kontron/kt690/romstage.c
===================================================================
--- src/mainboard/kontron/kt690/romstage.c	(revision 5263)
+++ src/mainboard/kontron/kt690/romstage.c	(working copy)
@@ -136,7 +136,7 @@
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
-	printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 
 	setup_kt690_resource_map();
 
@@ -162,7 +162,7 @@
 
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
-		printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
 		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -170,17 +170,17 @@
 
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
-		printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 	} else {
-		printk_debug("Changing FIDVID not supported\n");
-		printk_spew("... because cpuid returned %08x\n", cpuid1.edx);
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
+		printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
 	}
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs690_htinit();
-	printk_debug("needs_reset=0x%x\n", needs_reset);
+	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 
 	if (needs_reset) {
@@ -191,7 +191,7 @@
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now; */
-	printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
+	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
Index: src/mainboard/kontron/kt690/mptable.c
===================================================================
--- src/mainboard/kontron/kt690/mptable.c	(revision 5263)
+++ src/mainboard/kontron/kt690/mptable.c	(working copy)
@@ -199,7 +199,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/kontron/kt690/irq_tables.c
===================================================================
--- src/mainboard/kontron/kt690/irq_tables.c	(revision 5263)
+++ src/mainboard/kontron/kt690/irq_tables.c	(working copy)
@@ -73,7 +73,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *) (addr);
@@ -113,7 +113,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/kontron/kt690/acpi_tables.c
===================================================================
--- src/mainboard/kontron/kt690/acpi_tables.c	(revision 5263)
+++ src/mainboard/kontron/kt690/acpi_tables.c	(working copy)
@@ -49,9 +49,9 @@
 	print_debug("dump_mem:");
 	for (i = start; i < end; i++) {
 		if ((i & 0xf) == 0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
@@ -147,7 +147,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -165,13 +165,13 @@
 	 * We explicitly add these tables later on:
 	 */
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -179,14 +179,14 @@
 
 #if 0
 	/* SRAT */
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current += slit->header.length;
@@ -194,7 +194,7 @@
 #endif
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -214,7 +214,7 @@
 		} else {
 			c = (uint8_t) ('A' + i - 1 - 6);
 		}
-		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
 		current = (current + 0x07) & -0x08;
 		ssdtx = (acpi_header_t *) current;
 		switch (sysconf.hcid[i]) {
@@ -243,20 +243,20 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *) current;
 	memcpy((void *)dsdt, (void *)AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
 	current += dsdt->length;
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 	/* FADT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -264,28 +264,28 @@
 	acpi_add_table(rsdp, fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/kontron/kt690/mainboard.c
===================================================================
--- src/mainboard/kontron/kt690/mainboard.c	(revision 5263)
+++ src/mainboard/kontron/kt690/mainboard.c	(working copy)
@@ -61,7 +61,7 @@
 {
 	u8 byte;
 
-	printk_info("%s.\n", __func__);
+	printk(BIOS_INFO, "%s.\n", __func__);
 
 	/* set index register 0C50h to 13h (miscellaneous control) */
 	outb(0x13, 0xC50);	/* CMIndex */
@@ -100,7 +100,7 @@
 	struct device *sm_dev;
 	struct device *ide_dev;
 
-	printk_info("%s.\n", __func__);
+	printk(BIOS_INFO, "%s.\n", __func__);
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	byte = pci_read_config8(sm_dev, 0xA9);
@@ -137,7 +137,7 @@
 
 	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
 	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
-	printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
+	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
 
 	/* sb600 settings for thermal config */
 	/* set SB600 GPIO 64 to GPIO with pull-up */
@@ -190,19 +190,19 @@
 	struct mainboard_config *mainboard =
 	    (struct mainboard_config *)dev->chip_info;
 
-	printk_info("Mainboard KT690 Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
 		    __func__, msr2.lo, msr2.hi);
 
 	switch (msr.lo) {
@@ -224,7 +224,7 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
@@ -244,7 +244,7 @@
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
-	printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
+	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
Index: src/mainboard/gigabyte/m57sli/acpi_tables.c
===================================================================
--- src/mainboard/gigabyte/m57sli/acpi_tables.c	(revision 5263)
+++ src/mainboard/gigabyte/m57sli/acpi_tables.c	(working copy)
@@ -119,7 +119,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
@@ -134,7 +134,7 @@
 	acpi_write_rsdt(rsdt);
 
 	/* We explicitly add these tables later on: */
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 
 	/* we should align FACS to 64B as per ACPI specs */
 	current = ALIGN(current, 64);
@@ -148,9 +148,9 @@
 	       ((acpi_header_t *) AmlCode)->length);
 	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
@@ -158,46 +158,46 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET timers Linux wants an MADT. */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current+=slit->header.length;
 	acpi_add_table(rsdp, slit);
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/gigabyte/m57sli/mptable.c
===================================================================
--- src/mainboard/gigabyte/m57sli/mptable.c	(revision 5263)
+++ src/mainboard/gigabyte/m57sli/mptable.c	(working copy)
@@ -164,7 +164,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/gigabyte/m57sli/irq_tables.c
===================================================================
--- src/mainboard/gigabyte/m57sli/irq_tables.c	(revision 5263)
+++ src/mainboard/gigabyte/m57sli/irq_tables.c	(working copy)
@@ -75,7 +75,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -112,7 +112,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/gigabyte/m57sli/get_bus_conf.c
===================================================================
--- src/mainboard/gigabyte/m57sli/get_bus_conf.c	(revision 5263)
+++ src/mainboard/gigabyte/m57sli/get_bus_conf.c	(working copy)
@@ -115,7 +115,7 @@
 			for(j=bus_mcp55[1];j<bus_mcp55[2]; j++) bus_type[j] = 1;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
 
                         bus_mcp55[1] = 2;
                         bus_mcp55[2] = 3;
@@ -130,7 +130,7 @@
 				for(j=bus_mcp55[i];j<bus_isa; j++) bus_type[j] = 1;
 	                }
         	        else {
-                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
+                	        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
 	                        bus_isa = bus_mcp55[i-1]+1;
         	        }
 		}
Index: src/mainboard/gigabyte/ga_2761gxdk/mptable.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/mptable.c	(revision 5263)
+++ src/mainboard/gigabyte/ga_2761gxdk/mptable.c	(working copy)
@@ -156,7 +156,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	(revision 5263)
+++ src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	(working copy)
@@ -77,7 +77,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -114,7 +114,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
         {
                 device_t dev;
@@ -141,7 +141,7 @@
                     pci_write_config8(dev, reg[i], irq[i]);
 		} // endif
 
-                printk_debug("Setting Onboard SiS Southbridge\n");
+                printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
 
                 dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
                 pci_write_config8(dev, 0x3C, 0x0A);
@@ -163,9 +163,9 @@
                 pci_write_config8(dev, 0x3C, 0x05);
         }
 
-	printk_debug("pirq routing table, size=%d\n", pirq->size);
+	printk(BIOS_DEBUG, "pirq routing table, size=%d\n", pirq->size);
 	for (i = 0; i < pirq->size; i+=4)
-		printk_debug("%.2x%.2x%.2x%.2x\n", v[i+3],v[i+2],v[i+1],v[i]);
+		printk(BIOS_DEBUG, "%.2x%.2x%.2x%.2x\n", v[i+3],v[i+2],v[i+1],v[i]);
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	(revision 5263)
+++ src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	(working copy)
@@ -117,7 +117,7 @@
 			for(j=bus_sis966[1];j<bus_sis966[2]; j++) bus_type[j] = 1;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
 
                         bus_sis966[1] = 2;
                         bus_sis966[2] = 3;
@@ -132,7 +132,7 @@
 				for(j=bus_sis966[i];j<bus_isa; j++) bus_type[j] = 1;
 	                }
         	        else {
-                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_sis966[0], sbdn + 0x0a + i - 2 );
+                	        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_sis966[0], sbdn + 0x0a + i - 2 );
 	                        bus_isa = bus_sis966[i-1]+1;
         	        }
 		}
Index: src/mainboard/digitallogic/msm800sev/mainboard.c
===================================================================
--- src/mainboard/digitallogic/msm800sev/mainboard.c	(revision 5263)
+++ src/mainboard/digitallogic/msm800sev/mainboard.c	(working copy)
@@ -23,8 +23,8 @@
 
 static void init(struct device *dev)
 {
-	printk_debug("MSM800SEV ENTER %s\n", __func__);
-	printk_debug("MSM800SEV EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "MSM800SEV ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "MSM800SEV EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/digitallogic/msm586seg/mainboard.c
===================================================================
--- src/mainboard/digitallogic/msm586seg/mainboard.c	(revision 5263)
+++ src/mainboard/digitallogic/msm586seg/mainboard.c	(working copy)
@@ -23,10 +23,10 @@
 		-1};
   mmcr = (void *) 0xfffef000;
 
-  printk_err("mmcr is %p\n", mmcr);
+  printk(BIOS_ERR, "mmcr is %p\n", mmcr);
   for(i = 0; irqlist[i] >= 0; i++) {
     irq = mmcr + irqlist[i];
-    printk_err("0x%x register @%p is 0x%lx\n", irqlist[i], irq, *irq);
+    printk(BIOS_ERR, "0x%x register @%p is 0x%lx\n", irqlist[i], irq, *irq);
   }
 
 }
@@ -43,7 +43,7 @@
 	 */
 
 	/* currently, nothing in the device to use, so ignore it. */
-	printk_err("digital logic msm586 seg ENTER %s\n", __func__);
+	printk(BIOS_ERR, "digital logic msm586 seg ENTER %s\n", __func__);
 
 
 	/* from fuctory bios */
@@ -77,10 +77,10 @@
 
 
 	irqdump();
-	printk_err("uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
+	printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
 
-	printk_err("0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
-	printk_err("0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b);
+	printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
+	printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b);
 
 	/* The following block has NOT proven sufficient to get
 	 * the VGA hardware to talk to us 
@@ -92,7 +92,7 @@
 	mmcr->sysarb.prictl = 0xc0000f0f;
 	/* this is bios setting, depends on sysarb above */
 	mmcr->hostbridge.ctl = 0x108;
-	printk_err("digital logic msm586 seg EXIT %s\n", __func__);
+	printk(BIOS_ERR, "digital logic msm586 seg EXIT %s\n", __func__);
 
 	/* pio */
 	mmcr->pio.data31_16 = 0xffbf;
Index: src/mainboard/emulation/qemu-x86/mainboard.c
===================================================================
--- src/mainboard/emulation/qemu-x86/mainboard.c	(revision 5263)
+++ src/mainboard/emulation/qemu-x86/mainboard.c	(working copy)
@@ -28,7 +28,7 @@
 	/* The PIRQ table is not working well for interrupt routing purposes. 
 	 * so we'll just set the IRQ directly. 
 	*/
-	printk_info("setting ethernet\n");
+	printk(BIOS_INFO, "setting ethernet\n");
 	pci_assign_irqs(0, 3, enetIrqs);
 }
 
Index: src/mainboard/olpc/btest/mainboard.c
===================================================================
--- src/mainboard/olpc/btest/mainboard.c	(revision 5263)
+++ src/mainboard/olpc/btest/mainboard.c	(working copy)
@@ -49,22 +49,22 @@
   unsigned short rev = 0;
   unsigned short iobase = _getsmbusbase();
 
-  printk_debug("CHECKING FOR DCON (%x)\n", iobase);
+  printk(BIOS_DEBUG, "CHECKING FOR DCON (%x)\n", iobase);
 
   /* Get the IO base for the SMBUS */
 
   rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
 
   if (rev & 0xDC00) {
-	printk_debug("DCON FOUND - REV %x\n", rev);
+	printk(BIOS_DEBUG, "DCON FOUND - REV %x\n", rev);
 
 	/* Enable the DCON */
 	ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
 	if (ret != 0)
-		printk_debug("DCON ENABLE FAILED\n", ret);
+		printk(BIOS_DEBUG, "DCON ENABLE FAILED\n", ret);
   }
   else
-	  printk_debug("DCON NOT FOUND (%x)\n", rev);
+	  printk(BIOS_DEBUG, "DCON NOT FOUND (%x)\n", rev);
 
   write_bit(rev > 0 ? 1 : 0);
 }
@@ -104,18 +104,18 @@
 	unsigned char usbirq = 0xa;
 */
 
-	printk_debug("OLPC BTEST ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "OLPC BTEST ENTER %s\n", __func__);
 
 #if 0
 	/* I can't think of any reason NOT to just set this. If it turns out we want this to be
 	  * conditional we can make it a config variable later.
 	  */
 
-	printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n", 
+	printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", 
 		__func__, bus, devfn, usbirq);
 	usb = dev_find_slot(bus, devfn);
 	if (! usb){
-		printk_err("Could not find USB\n");
+		printk(BIOS_ERR, "Could not find USB\n");
 	} else {
 		pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
 	}
@@ -123,7 +123,7 @@
 
 	init_dcon();
 	init_cafe_irq();
-	printk_debug("OLPC BTEST EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "OLPC BTEST EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/olpc/rev_a/mainboard.c
===================================================================
--- src/mainboard/olpc/rev_a/mainboard.c	(revision 5263)
+++ src/mainboard/olpc/rev_a/mainboard.c	(working copy)
@@ -48,22 +48,22 @@
   unsigned short rev = 0;
   unsigned short iobase = _getsmbusbase();
 
-  printk_debug("CHECKING FOR DCON (%x)\n", iobase);
+  printk(BIOS_DEBUG, "CHECKING FOR DCON (%x)\n", iobase);
 
   /* Get the IO base for the SMBUS */
 
   rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
 
   if (rev & 0xDC00) {
-	printk_debug("DCON FOUND - REV %x\n", rev);
+	printk(BIOS_DEBUG, "DCON FOUND - REV %x\n", rev);
 
 	/* Enable the DCON */
 	ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
 	if (ret != 0)
-		printk_debug("DCON ENABLE FAILED\n", ret);
+		printk(BIOS_DEBUG, "DCON ENABLE FAILED\n", ret);
   }
   else
-	  printk_debug("DCON NOT FOUND (%x)\n", rev);
+	  printk(BIOS_DEBUG, "DCON NOT FOUND (%x)\n", rev);
 
   write_bit(rev > 0 ? 1 : 0);
 }
@@ -76,25 +76,25 @@
 	unsigned char usbirq = 0xa;
 */
 
-	printk_debug("OLPC REVA ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "OLPC REVA ENTER %s\n", __func__);
 
 #if 0
 	/* I can't think of any reason NOT to just set this. If it turns out we want this to be
 	  * conditional we can make it a config variable later.
 	  */
 
-	printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n", 
+	printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", 
 		__func__, bus, devfn, usbirq);
 	usb = dev_find_slot(bus, devfn);
 	if (! usb){
-		printk_err("Could not find USB\n");
+		printk(BIOS_ERR, "Could not find USB\n");
 	} else {
 		pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
 	}
 #endif
 
 	init_dcon();
-	printk_debug("OLPC REVA EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "OLPC REVA EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/technologic/ts5300/mainboard.c
===================================================================
--- src/mainboard/technologic/ts5300/mainboard.c	(revision 5263)
+++ src/mainboard/technologic/ts5300/mainboard.c	(working copy)
@@ -23,10 +23,10 @@
 		-1};
   mmcr = (void *) 0xfffef000;
 
-  printk_err("mmcr is %p\n", mmcr);
+  printk(BIOS_ERR, "mmcr is %p\n", mmcr);
   for(i = 0; irqlist[i] >= 0; i++) {
     irq = mmcr + irqlist[i];
-    printk_err("0x%x register @%p is 0x%lx\n", irqlist[i], irq, *irq);
+    printk(BIOS_ERR, "0x%x register @%p is 0x%lx\n", irqlist[i], irq, *irq);
   }
 
 }
@@ -39,14 +39,14 @@
 	volatile struct mmcr *mmcr = MMCRDEFAULT;
 
 	/* currently, nothing in the device to use, so ignore it. */
-	printk_err("Technologic Systems 5300 ENTER %s\n", __func__);
+	printk(BIOS_ERR, "Technologic Systems 5300 ENTER %s\n", __func__);
 
 	/* from fuctory bios */
 	/* NOTE: the following interrupt settings made interrupts work
 	 * for hard drive, and serial, but not for ethernet 
 	 */
 
-	printk_err("Setting up PIC\n");
+	printk(BIOS_ERR, "Setting up PIC\n");
 	/* just do what they say and nobody gets hurt. */
 	mmcr->pic.pcicr = 0 ;
 	/* all ints to level */
@@ -77,7 +77,7 @@
 
 	// irqdump();
 
-	printk_err("Setting up sysarb\n");
+	printk(BIOS_ERR, "Setting up sysarb\n");
 	mmcr->dbctl.dbctl = 0x01;
 	mmcr->sysarb.ctl = 0x00;
 	mmcr->sysarb.menb = 0x1f;
@@ -90,7 +90,7 @@
 	mmcr->hostbridge.mstirqctl = 0x0;
 	mmcr->hostbridge.mstirqsta = 0x708;
 
-	printk_err("Setting up pio\n");
+	printk(BIOS_ERR, "Setting up pio\n");
 	/* pio */
 	mmcr->pio.pfs15_0 = 0xffff;
 	mmcr->pio.pfs31_16 = 0xffff;
@@ -100,7 +100,7 @@
 	mmcr->pio.data15_0 = 0xde04;
 	mmcr->pio.data31_16 = 0xef9f;
 
-	printk_err("Setting up sysmap\n");
+	printk(BIOS_ERR, "Setting up sysmap\n");
 	/* system memory map */
 	mmcr->sysmap.adddecctl = 0x04;
 	mmcr->sysmap.wpvsta = 0x8006;
@@ -116,7 +116,7 @@
 	mmcr->sysmap.par[13] = 0x8a07c940;
 	mmcr->sysmap.par[15] = 0xee00400e;
 
-	printk_err("Setting up gpctl\n");
+	printk(BIOS_ERR, "Setting up gpctl\n");
 	mmcr->gpctl.gpcsrt = 0x01;
 	mmcr->gpctl.gpcspw = 0x09;
 	mmcr->gpctl.gpcsoff = 0x01;
@@ -138,7 +138,7 @@
 	mmcr->dmacontrol.extchanmapa = 0xf210;
 	mmcr->dmacontrol.extchanmapb = 0xffff;
 
-	printk_err("TS5300 EXIT %s\n", __func__);
+	printk(BIOS_ERR, "TS5300 EXIT %s\n", __func__);
 }
 
 struct chip_operations mainboard_ops = {
Index: src/mainboard/amd/pistachio/fadt.c
===================================================================
--- src/mainboard/amd/pistachio/fadt.c	(revision 5263)
+++ src/mainboard/amd/pistachio/fadt.c	(working copy)
@@ -46,7 +46,7 @@
 	acpi_header_t *header = &(fadt->header);
 
 	pm_base &= 0xFFFF;
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/mainboard/amd/pistachio/romstage.c
===================================================================
--- src/mainboard/amd/pistachio/romstage.c	(revision 5263)
+++ src/mainboard/amd/pistachio/romstage.c	(working copy)
@@ -132,7 +132,7 @@
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
-	printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 
 	setup_pistachio_resource_map();
 
@@ -162,7 +162,7 @@
 
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
-		printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
 		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -170,10 +170,10 @@
 
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
-		printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 	} else {
-		printk_debug("Changing FIDVID not supported\n");
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
 
 	post_code(0x05);
@@ -181,7 +181,7 @@
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs690_htinit();
-	printk_debug("needs_reset=0x%x\n", needs_reset);
+	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	post_code(0x06);
 
@@ -193,7 +193,7 @@
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now; */
-	printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
+	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
Index: src/mainboard/amd/pistachio/mptable.c
===================================================================
--- src/mainboard/amd/pistachio/mptable.c	(revision 5263)
+++ src/mainboard/amd/pistachio/mptable.c	(working copy)
@@ -199,7 +199,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/amd/pistachio/irq_tables.c
===================================================================
--- src/mainboard/amd/pistachio/irq_tables.c	(revision 5263)
+++ src/mainboard/amd/pistachio/irq_tables.c	(working copy)
@@ -73,7 +73,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *) (addr);
@@ -113,7 +113,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/amd/pistachio/acpi_tables.c
===================================================================
--- src/mainboard/amd/pistachio/acpi_tables.c	(revision 5263)
+++ src/mainboard/amd/pistachio/acpi_tables.c	(working copy)
@@ -49,9 +49,9 @@
 	print_debug("dump_mem:");
 	for (i = start; i < end; i++) {
 		if ((i & 0xf) == 0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
@@ -147,7 +147,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -165,13 +165,13 @@
 	 * We explicitly add these tables later on:
 	 */
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -179,14 +179,14 @@
 
 #if 0
 	/* SRAT */
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current += slit->header.length;
@@ -194,7 +194,7 @@
 #endif
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -214,7 +214,7 @@
 		} else {
 			c = (uint8_t) ('A' + i - 1 - 6);
 		}
-		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
 		current = (current + 0x07) & -0x08;
 		ssdtx = (acpi_header_t *) current;
 		switch (sysconf.hcid[i]) {
@@ -243,21 +243,21 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *) current;
 	memcpy((void *)dsdt, (void *)AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
 
 	current += dsdt->length;
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 	/* FADT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -265,28 +265,28 @@
 	acpi_add_table(rsdp, fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/amd/pistachio/mainboard.c
===================================================================
--- src/mainboard/amd/pistachio/mainboard.c	(revision 5263)
+++ src/mainboard/amd/pistachio/mainboard.c	(working copy)
@@ -61,7 +61,7 @@
 {
 	u8 byte;
 
-	printk_info("%s.\n", __func__);
+	printk(BIOS_INFO, "%s.\n", __func__);
 
 	/* enable GPM8 output */
 	byte = pm_ioread(0x95);
@@ -155,7 +155,7 @@
 	/* remote 1 temperature offset */
 	ADT7475_write_byte(0x70, 0x00);
 
-	printk_info("Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
+	printk(BIOS_INFO, "Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
 		    byte2, byte);
 
 	/* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
@@ -261,19 +261,19 @@
 	struct mainboard_config *mainboard =
 	    (struct mainboard_config *)dev->chip_info;
 
-	printk_info("Mainboard Pistachio Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
 		    __func__, msr2.lo, msr2.hi);
 
 	switch (msr.lo) {
@@ -295,7 +295,7 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
@@ -315,7 +315,7 @@
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
-	printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
+	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
Index: src/mainboard/amd/mahogany/fadt.c
===================================================================
--- src/mainboard/amd/mahogany/fadt.c	(revision 5263)
+++ src/mainboard/amd/mahogany/fadt.c	(working copy)
@@ -46,7 +46,7 @@
 	acpi_header_t *header = &(fadt->header);
 
 	pm_base &= 0xFFFF;
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/mainboard/amd/mahogany/romstage.c
===================================================================
--- src/mainboard/amd/mahogany/romstage.c	(revision 5263)
+++ src/mainboard/amd/mahogany/romstage.c	(working copy)
@@ -133,7 +133,7 @@
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
-	printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 
 	setup_mahogany_resource_map();
 
@@ -159,7 +159,7 @@
 
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
-		printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
 		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -167,16 +167,16 @@
 
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
-		printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 	} else {
-		printk_debug("Changing FIDVID not supported\n");
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs780_htinit();
-	printk_debug("needs_reset=0x%x\n", needs_reset);
+	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 	if (needs_reset) {
 		print_info("ht reset -\r\n");
@@ -186,7 +186,7 @@
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now; */
-	printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
+	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
Index: src/mainboard/amd/mahogany/mptable.c
===================================================================
--- src/mainboard/amd/mahogany/mptable.c	(revision 5263)
+++ src/mainboard/amd/mahogany/mptable.c	(working copy)
@@ -206,7 +206,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/amd/mahogany/irq_tables.c
===================================================================
--- src/mainboard/amd/mahogany/irq_tables.c	(revision 5263)
+++ src/mainboard/amd/mahogany/irq_tables.c	(working copy)
@@ -73,7 +73,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *) (addr);
@@ -113,7 +113,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/amd/mahogany/acpi_tables.c
===================================================================
--- src/mainboard/amd/mahogany/acpi_tables.c	(revision 5263)
+++ src/mainboard/amd/mahogany/acpi_tables.c	(working copy)
@@ -49,9 +49,9 @@
 	print_debug("dump_mem:");
 	for (i = start; i < end; i++) {
 		if ((i & 0xf) == 0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
@@ -147,7 +147,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -165,13 +165,13 @@
 	 * We explicitly add these tables later on:
 	 */
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -179,14 +179,14 @@
 
 #if 0
 	/* SRAT */
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current += slit->header.length;
@@ -194,7 +194,7 @@
 #endif
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -214,7 +214,7 @@
 		} else {
 			c = (uint8_t) ('A' + i - 1 - 6);
 		}
-		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
 		current = (current + 0x07) & -0x08;
 		ssdtx = (acpi_header_t *) current;
 		switch (sysconf.hcid[i]) {
@@ -243,20 +243,20 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *) current;
 	memcpy((void *)dsdt, (void *)AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
 	current += dsdt->length;
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 	/* FADT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -264,28 +264,28 @@
 	acpi_add_table(rsdp, fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/amd/mahogany/mainboard.c
===================================================================
--- src/mainboard/amd/mahogany/mainboard.c	(revision 5263)
+++ src/mainboard/amd/mahogany/mainboard.c	(working copy)
@@ -101,21 +101,21 @@
 	struct mainboard_config *mainboard =
 	    (struct mainboard_config *)dev->chip_info;
 
-	printk_info("Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info
-	    ("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 	     __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info
-	    ("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
 	     __func__, msr2.lo, msr2.hi);
 
 	/* refer to UMA Size Consideration in 780 BDG. */
@@ -134,7 +134,7 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
@@ -153,7 +153,7 @@
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
-	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
+	printk(BIOS_INFO, "uma_memory_start=0x%x, uma_memory_size=0x%x \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
Index: src/mainboard/amd/dbm690t/fadt.c
===================================================================
--- src/mainboard/amd/dbm690t/fadt.c	(revision 5263)
+++ src/mainboard/amd/dbm690t/fadt.c	(working copy)
@@ -46,7 +46,7 @@
 	acpi_header_t *header = &(fadt->header);
 
 	pm_base &= 0xFFFF;
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/mainboard/amd/dbm690t/romstage.c
===================================================================
--- src/mainboard/amd/dbm690t/romstage.c	(revision 5263)
+++ src/mainboard/amd/dbm690t/romstage.c	(working copy)
@@ -134,7 +134,7 @@
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
-	printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 
 	setup_dbm690t_resource_map();
 
@@ -160,7 +160,7 @@
 
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
-		printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
 		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -168,16 +168,16 @@
 
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
-		printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 	} else {
-		printk_debug("Changing FIDVID not supported\n");
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs690_htinit();
-	printk_debug("needs_reset=0x%x\n", needs_reset);
+	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 
 	if (needs_reset) {
@@ -188,7 +188,7 @@
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now; */
-	printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
+	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
Index: src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- src/mainboard/amd/dbm690t/mptable.c	(revision 5263)
+++ src/mainboard/amd/dbm690t/mptable.c	(working copy)
@@ -199,7 +199,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/amd/dbm690t/irq_tables.c
===================================================================
--- src/mainboard/amd/dbm690t/irq_tables.c	(revision 5263)
+++ src/mainboard/amd/dbm690t/irq_tables.c	(working copy)
@@ -73,7 +73,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *) (addr);
@@ -113,7 +113,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/amd/dbm690t/acpi_tables.c
===================================================================
--- src/mainboard/amd/dbm690t/acpi_tables.c	(revision 5263)
+++ src/mainboard/amd/dbm690t/acpi_tables.c	(working copy)
@@ -49,9 +49,9 @@
 	print_debug("dump_mem:");
 	for (i = start; i < end; i++) {
 		if ((i & 0xf) == 0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
@@ -147,7 +147,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -165,13 +165,13 @@
 	 * We explicitly add these tables later on:
 	 */
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -179,14 +179,14 @@
 
 #if 0
 	/* SRAT */
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current += slit->header.length;
@@ -194,7 +194,7 @@
 #endif
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -214,7 +214,7 @@
 		} else {
 			c = (uint8_t) ('A' + i - 1 - 6);
 		}
-		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
 		current = (current + 0x07) & -0x08;
 		ssdtx = (acpi_header_t *) current;
 		switch (sysconf.hcid[i]) {
@@ -243,20 +243,20 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *) current;
 	memcpy((void *)dsdt, (void *)AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
 	current += dsdt->length;
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 	/* FADT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -264,28 +264,28 @@
 	acpi_add_table(rsdp, fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- src/mainboard/amd/dbm690t/mainboard.c	(revision 5263)
+++ src/mainboard/amd/dbm690t/mainboard.c	(working copy)
@@ -61,7 +61,7 @@
 {
 	u8 byte;
 
-	printk_info("%s.\n", __func__);
+	printk(BIOS_INFO, "%s.\n", __func__);
 
 	/* set index register 0C50h to 13h (miscellaneous control) */
 	outb(0x13, 0xC50);	/* CMIndex */
@@ -100,7 +100,7 @@
 	struct device *sm_dev;
 	struct device *ide_dev;
 
-	printk_info("%s.\n", __func__);
+	printk(BIOS_INFO, "%s.\n", __func__);
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	byte = pci_read_config8(sm_dev, 0xA9);
@@ -137,7 +137,7 @@
 
 	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
 	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
-	printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
+	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
 
 	/* sb600 settings for thermal config */
 	/* set SB600 GPIO 64 to GPIO with pull-up */
@@ -190,19 +190,19 @@
 	struct mainboard_config *mainboard =
 	    (struct mainboard_config *)dev->chip_info;
 
-	printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
 		    __func__, msr2.lo, msr2.hi);
 
 	switch (msr.lo) {
@@ -224,7 +224,7 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
@@ -244,7 +244,7 @@
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
-	printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
+	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
Index: src/mainboard/amd/rumba/mainboard.c
===================================================================
--- src/mainboard/amd/rumba/mainboard.c	(revision 5263)
+++ src/mainboard/amd/rumba/mainboard.c	(working copy)
@@ -16,19 +16,19 @@
 	if (mainboard->nicirq)
 		nicirq = mainboard->nicirq;
 
-	printk_debug("AMD RUMBA ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__);
 
 	if (nicirq) {
-		printk_debug("%s (%x,%x)SET PCI interrupt line to %d\n", 
+		printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n", 
 			__func__, bus, devfn, nicirq);
 		nic = dev_find_slot(bus, devfn);
 		if (! nic){
-			printk_err("Could not find NIC\n");
+			printk(BIOS_ERR, "Could not find NIC\n");
 		} else {
 			pci_write_config8(nic, PCI_INTERRUPT_LINE, nicirq);
 		}
 	}
-	printk_debug("AMD RUMBA EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "AMD RUMBA EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/amd/serengeti_cheetah/ap_romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/ap_romstage.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah/ap_romstage.c	(working copy)
@@ -82,7 +82,7 @@
 	id = get_node_core_id_x();
 
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("CODE IN CACHE ON NODE: %02x\n");
+        printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
 #else
         print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
 #endif
Index: src/mainboard/amd/serengeti_cheetah/acpi_tables.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/acpi_tables.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah/acpi_tables.c	(working copy)
@@ -30,9 +30,9 @@
         print_debug("dump_mem:");
         for(i=start;i<end;i++) {
                 if((i & 0xf)==0) {
-                        printk_debug("\n%08x:", i);
+                        printk(BIOS_DEBUG, "\n%08x:", i);
                 }
-                printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+                printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
         }
         print_debug("\n");
  }
@@ -208,7 +208,7 @@
 	start   = ( start + 0x0f ) & -0x10;
 	current = start;
 	
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -225,14 +225,14 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp,hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current+=madt->header.length;
@@ -240,21 +240,21 @@
 
 
 	/* SRAT */
-        printk_debug("ACPI:    * SRAT\n");
+        printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
         srat = (acpi_srat_t *) current;
         acpi_create_srat(srat);
         current+=srat->header.length;
         acpi_add_table(rsdp,srat);
 
 	/* SLIT */
-        printk_debug("ACPI:    * SLIT\n");
+        printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
         slit = (acpi_slit_t *) current;
         acpi_create_slit(slit);
         current+=slit->header.length;
         acpi_add_table(rsdp,slit);
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -274,7 +274,7 @@
                 else {
                         c  = (uint8_t) ('A' + i - 1 - 6);
                 }
-                printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
+                printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
                 current   = ( current + 0x07) & -0x08;
                 ssdtx = (acpi_header_t *)current;
                 switch(sysconf.hcid[i]) {
@@ -300,21 +300,21 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *)current;
 	current += ((acpi_header_t *)AmlCode)->length;
 	memcpy((void *)dsdt,(void *)AmlCode, \
 			((acpi_header_t *)AmlCode)->length);
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	/* FDAT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -322,29 +322,29 @@
 	acpi_add_table(rsdp,fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-        printk_debug("rsdt\n");
+        printk(BIOS_DEBUG, "rsdt\n");
         dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-        printk_debug("madt\n");
+        printk(BIOS_DEBUG, "madt\n");
         dump_mem(madt, ((void *)madt) + madt->header.length);
 
-        printk_debug("srat\n");
+        printk(BIOS_DEBUG, "srat\n");
         dump_mem(srat, ((void *)srat) + srat->header.length);
 
-        printk_debug("slit\n");
+        printk(BIOS_DEBUG, "slit\n");
         dump_mem(slit, ((void *)slit) + slit->header.length);
 
-        printk_debug("ssdt\n");
+        printk(BIOS_DEBUG, "ssdt\n");
         dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-        printk_debug("fadt\n");
+        printk(BIOS_DEBUG, "fadt\n");
         dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/amd/serengeti_cheetah/fadt.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/fadt.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah/fadt.c	(working copy)
@@ -13,7 +13,7 @@
 
 	acpi_header_t *header=&(fadt->header);
 
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt,0,sizeof(acpi_fadt_t));
Index: src/mainboard/amd/serengeti_cheetah/mptable.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/mptable.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah/mptable.c	(working copy)
@@ -199,7 +199,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/amd/serengeti_cheetah/irq_tables.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/irq_tables.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah/irq_tables.c	(working copy)
@@ -58,7 +58,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -98,13 +98,13 @@
         }
 
 //pci bridge
-        printk_debug("setting Onboard AMD Southbridge \n");
+        printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n");
         static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
         pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
 	write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Onboard AMD USB \n");
+        printk(BIOS_DEBUG, "setting Onboard AMD USB \n");
         static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
         pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
         write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
@@ -138,7 +138,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	(working copy)
@@ -112,11 +112,11 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
-//		printk_debug("bus_isa=%d\n",bus_isa);
+//		printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
         }
 	else {
-                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
         }
 
         /* 8132-1 */
@@ -125,7 +125,7 @@
                 m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
         }
 
         /* 8132-2 */
@@ -135,11 +135,11 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
-//              printk_debug("bus_isa=%d\n",bus_isa);
+//              printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
         }
 
         /* HT chain 1 */
@@ -165,7 +165,7 @@
                                 m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
                         }
                         else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
                         }
 
                         /* 8132-2 */
@@ -174,10 +174,10 @@
                                 m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
                                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                                 m->bus_isa++;
-                //              printk_debug("bus_isa=%d\n",bus_isa);
+                //              printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
                                 }
                         else {
-                                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
+                                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
                         }
 
                         break;
@@ -191,12 +191,12 @@
 
                         if (dev) {
                                 m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-        //                        printk_debug("bus_8151_1=%d\n",bus_8151[j][1]);
+        //                        printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]);
                                 m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                                 m->bus_isa++;
                         }
                         else {
-                                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
+                                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
                         }
 
                         break;
Index: src/mainboard/amd/mahogany_fam10/acpi_tables.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/acpi_tables.c	(revision 5263)
+++ src/mainboard/amd/mahogany_fam10/acpi_tables.c	(working copy)
@@ -38,9 +38,9 @@
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 	}
 	print_debug("\n");
 }
@@ -140,7 +140,7 @@
 	start	= ( start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -158,7 +158,7 @@
 	 * We explicitly add these tables later on:
 	 */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * HPET at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
@@ -166,7 +166,7 @@
 
 	/* If we want to use HPET Timers Linux wants an MADT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * MADT at %lx\n",current);
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current+=madt->header.length;
@@ -174,7 +174,7 @@
 
 	/* SRAT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * SRAT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current+=srat->header.length;
@@ -182,7 +182,7 @@
 
 	/* SLIT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:   * SLIT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current+=slit->header.length;
@@ -190,7 +190,7 @@
 
 	/* SSDT */
 	current	  = ( current + 0x0f) & -0x10;
-	printk_debug("ACPI:    * SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)current;
 	current += ((acpi_header_t *)AmlCode_ssdt)->length;
 	memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
@@ -201,7 +201,7 @@
 	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
 	acpi_add_table(rsdp,ssdt);
 
-	printk_debug("ACPI:    * SSDT for PState at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 	current = acpi_add_ssdt_pstates(rsdp, current);
 
 #if 0 //CONFIG_ACPI_SSDTX_NUM >= 1
@@ -219,7 +219,7 @@
 			c  = (u8) ('A' + i - 1 - 6);
 		}
 		current	  = ( current + 0x07) & -0x08;
-		printk_debug("ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
 		ssdtx = (acpi_header_t *)current;
 		switch(sysconf.hcid[i]) {
 		case 1:
@@ -246,23 +246,23 @@
 
 	/* DSDT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * DSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
 	dsdt = (acpi_header_t *)current; // it will used by fadt
 	current += ((acpi_header_t *)AmlCode)->length;
 	memcpy((void *)dsdt,(void *)AmlCode, \
 			((acpi_header_t *)AmlCode)->length);
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	/* FACS */ // it needs 64 bit alignment
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:	* FACS at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
 	facs = (acpi_facs_t *) current; // it will be used by fadt
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* FDAT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * FADT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -270,29 +270,29 @@
 	acpi_add_table(rsdp,fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/amd/mahogany_fam10/fadt.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/fadt.c	(revision 5263)
+++ src/mainboard/amd/mahogany_fam10/fadt.c	(working copy)
@@ -46,7 +46,7 @@
 	acpi_header_t *header = &(fadt->header);
 
 	pm_base &= 0xFFFF;
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/mainboard/amd/mahogany_fam10/romstage.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/romstage.c	(revision 5263)
+++ src/mainboard/amd/mahogany_fam10/romstage.c	(working copy)
@@ -72,9 +72,9 @@
 #if 0
 void die(const char *msg);
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
+#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
 #endif
-#define printk_info(fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
+#define printk(BIOS_INFO, fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
 #include "cpu/x86/bist.h"
 
 
@@ -174,7 +174,7 @@
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
@@ -183,10 +183,10 @@
 
 	// Load MPB
 	val = cpuid_eax(1);
-	printk_debug("BSP Family_Model: %08x \n", val);
-	printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
-	printk_debug("bsp_apicid = %02x \n", bsp_apicid);
-	printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 
 	/* Setup sysinfo defaults */
 	set_sysinfo_in_ram(0);
@@ -217,7 +217,7 @@
 
  #if CONFIG_LOGICAL_CPUS==1
 	/* Core0 on each node is configured. Now setup any additional cores. */
-	printk_debug("start_other_cores()\n");
+	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
 	post_code(0x37);
 	wait_all_other_cores_started(bsp_apicid);
@@ -231,7 +231,7 @@
 
  #if FAM10_SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
-	printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
 	/* FIXME: The sb fid change may survive the warm reset and only
 	   need to be done once.*/
@@ -249,7 +249,7 @@
 
 	/* show final fid and vid */
 	msr=rdmsr(0xc0010071);
-	printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
  #endif
 
 	rs780_htinit();
@@ -264,7 +264,7 @@
 	post_code(0x3B);
 
 	/* It's the time to set ctrl in sysinfo now; */
-	printk_debug("fill_mem_ctrl()\n");
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	post_code(0x3D);
 
@@ -273,7 +273,7 @@
 
 //	die("Die Before MCT init.");
 
-	printk_debug("raminit_amdmct()\n");
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
 	post_code(0x41);
 
@@ -294,7 +294,7 @@
 	sb700_before_pci_init();
 
 	post_code(0x42);
-	printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
Index: src/mainboard/amd/mahogany_fam10/mptable.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/mptable.c	(revision 5263)
+++ src/mainboard/amd/mahogany_fam10/mptable.c	(working copy)
@@ -206,7 +206,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/amd/mahogany_fam10/irq_tables.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/irq_tables.c	(revision 5263)
+++ src/mainboard/amd/mahogany_fam10/irq_tables.c	(working copy)
@@ -67,7 +67,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *) (addr);
@@ -107,7 +107,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/amd/mahogany_fam10/apc_auto.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/apc_auto.c	(revision 5263)
+++ src/mainboard/amd/mahogany_fam10/apc_auto.c	(working copy)
@@ -80,7 +80,7 @@
 
 	id = get_node_core_id_x();
 
-	printk_debug("CODE IN CACHE ON NODE: %02x\n");
+	printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/amd/mahogany_fam10/mainboard.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/mainboard.c	(revision 5263)
+++ src/mainboard/amd/mahogany_fam10/mainboard.c	(working copy)
@@ -101,21 +101,21 @@
 	struct mainboard_config *mainboard =
 	    (struct mainboard_config *)dev->chip_info;
 
-	printk_info("Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info
-	    ("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 	     __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info
-	    ("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
 	     __func__, msr2.lo, msr2.hi);
 
 	/* refer to UMA Size Consideration in 780 BDG. */
@@ -134,7 +134,7 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
@@ -153,7 +153,7 @@
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
-	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
+	printk(BIOS_INFO, "uma_memory_start=0x%x, uma_memory_size=0x%x \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
Index: src/mainboard/amd/norwich/mainboard.c
===================================================================
--- src/mainboard/amd/norwich/mainboard.c	(revision 5263)
+++ src/mainboard/amd/norwich/mainboard.c	(working copy)
@@ -23,8 +23,8 @@
 
 static void init(struct device *dev)
 {
-	printk_debug("Norwich ENTER %s\n", __func__);
-	printk_debug("Norwich EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "Norwich ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "Norwich EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/amd/serengeti_cheetah_fam10/ap_romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/ap_romstage.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah_fam10/ap_romstage.c	(working copy)
@@ -80,7 +80,7 @@
 
 	id = get_node_core_id_x();
 
-	printk_debug("CODE IN CACHE ON NODE: %02x\n");
+	printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	(working copy)
@@ -38,9 +38,9 @@
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 	}
 	print_debug("\n");
 }
@@ -212,7 +212,7 @@
 	start	= ( start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -230,7 +230,7 @@
 	 * We explicitly add these tables later on:
 	 */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * HPET at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
@@ -238,7 +238,7 @@
 
 	/* If we want to use HPET Timers Linux wants an MADT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * MADT at %lx\n",current);
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current+=madt->header.length;
@@ -246,7 +246,7 @@
 
 	/* SRAT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * SRAT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current+=srat->header.length;
@@ -254,7 +254,7 @@
 
 	/* SLIT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:   * SLIT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current+=slit->header.length;
@@ -262,7 +262,7 @@
 
 	/* SSDT */
 	current	  = ( current + 0x0f) & -0x10;
-	printk_debug("ACPI:    * SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)current;
 	current += ((acpi_header_t *)AmlCode_ssdt)->length;
 	memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
@@ -273,7 +273,7 @@
 	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
 	acpi_add_table(rsdp,ssdt);
 
-	printk_debug("ACPI:    * SSDT for PState at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 	current = acpi_add_ssdt_pstates(rsdp, current);
 
 #if CONFIG_ACPI_SSDTX_NUM >= 1
@@ -291,7 +291,7 @@
 			c  = (u8) ('A' + i - 1 - 6);
 		}
 		current	  = ( current + 0x07) & -0x08;
-		printk_debug("ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
 		ssdtx = (acpi_header_t *)current;
 		switch(sysconf.hcid[i]) {
 		case 1:
@@ -318,23 +318,23 @@
 
 	/* DSDT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * DSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
 	dsdt = (acpi_header_t *)current; // it will used by fadt
 	current += ((acpi_header_t *)AmlCode)->length;
 	memcpy((void *)dsdt,(void *)AmlCode, \
 			((acpi_header_t *)AmlCode)->length);
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	/* FACS */ // it needs 64 bit alignment
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:	* FACS at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
 	facs = (acpi_facs_t *) current; // it will be used by fadt
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* FDAT */
 	current	  = ( current + 0x07) & -0x08;
-	printk_debug("ACPI:    * FADT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -342,29 +342,29 @@
 	acpi_add_table(rsdp,fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah_fam10/fadt.c	(working copy)
@@ -34,7 +34,7 @@
 
 	acpi_header_t *header=&(fadt->header);
 
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt,0,sizeof(acpi_fadt_t));
Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(working copy)
@@ -73,7 +73,7 @@
 #if 0
 void die(const char *msg);
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
+#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
 #endif
 #include "cpu/x86/bist.h"
 
@@ -105,7 +105,7 @@
 	int ret,i;
 	u8 device = ctrl->spd_switch_addr;
 
-	printk_debug("switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
+	printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
 
 	/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
 	i=2;
@@ -176,7 +176,7 @@
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
@@ -185,10 +185,10 @@
 
 	// Load MPB
 	val = cpuid_eax(1);
-	printk_debug("BSP Family_Model: %08x \n", val);
-	printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
-	printk_debug("bsp_apicid = %02x \n", bsp_apicid);
-	printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 
 	/* Setup sysinfo defaults */
 	set_sysinfo_in_ram(0);
@@ -219,7 +219,7 @@
 
  #if CONFIG_LOGICAL_CPUS==1
 	/* Core0 on each node is configured. Now setup any additional cores. */
-	printk_debug("start_other_cores()\n");
+	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
 	post_code(0x37);
 	wait_all_other_cores_started(bsp_apicid);
@@ -229,7 +229,7 @@
 
  #if FAM10_SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
-	printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
 	/* FIXME: The sb fid change may survive the warm reset and only
 	   need to be done once.*/
@@ -247,7 +247,7 @@
 
 	/* show final fid and vid */
 	msr=rdmsr(0xc0010071);
-	printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
  #endif
 
 
@@ -268,12 +268,12 @@
 	post_code(0x3C);
 
 	/* It's the time to set ctrl in sysinfo now; */
-	printk_debug("fill_mem_ctrl()\n");
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	post_code(0x3D);
 
 
-	printk_debug("enable_smbus()\n");
+	printk(BIOS_DEBUG, "enable_smbus()\n");
 	enable_smbus();
 	post_code(0x3E);
 
@@ -283,7 +283,7 @@
 
 //	die("Die Before MCT init.");
 
-	printk_debug("raminit_amdmct()\n");
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
 	post_code(0x41);
 
@@ -302,7 +302,7 @@
 //	die("After MCT init before CAR disabled.");
 
 	post_code(0x42);
-	printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 
Index: src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/mptable.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah_fam10/mptable.c	(working copy)
@@ -224,7 +224,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c	(working copy)
@@ -70,7 +70,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *)(addr);
@@ -137,7 +137,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c	(revision 5263)
+++ src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c	(working copy)
@@ -133,7 +133,7 @@
 	if (dev) {
 		m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	} else {
-		printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
+		printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
 	}
 
 	/* 8132-1 */
@@ -141,7 +141,7 @@
 	if (dev) {
 		m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	} else {
-		printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
+		printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
 	}
 
 	/* 8132-2 */
@@ -149,7 +149,7 @@
 	if (dev) {
 		m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	} else {
-		printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
+		printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
 	}
 
 	for(i=0; i< sysconf.hc_possible_num; i++) {
@@ -161,7 +161,7 @@
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max)
 			m->bus_isa = busn_max + 1;
-		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+		printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
 	}
 
 	 /* HT chain 1 */
@@ -186,7 +186,7 @@
 			if (dev) {
 				m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			} else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
 			}
 
 			/* 8132-2 */
@@ -194,7 +194,7 @@
 			if (dev) {
 				m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			} else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
 			}
 
 			break;
@@ -209,7 +209,7 @@
 			if (dev) {
 				m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			} else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
 			}
 
 			break;
Index: src/mainboard/amd/db800/mainboard.c
===================================================================
--- src/mainboard/amd/db800/mainboard.c	(revision 5263)
+++ src/mainboard/amd/db800/mainboard.c	(working copy)
@@ -23,8 +23,8 @@
 
 static void init(struct device *dev)
 {
-	printk_debug("AMD DB800 ENTER %s\n", __func__);
-	printk_debug("AMD DB800 EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "AMD DB800 ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "AMD DB800 EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/rca/rm4100/mainboard_smi.c
===================================================================
--- src/mainboard/rca/rm4100/mainboard_smi.c	(revision 5263)
+++ src/mainboard/rca/rm4100/mainboard_smi.c	(working copy)
@@ -25,6 +25,6 @@
 
 int mainboard_io_trap_handler(int smif)
 {
-	printk_debug("MAINBOARD IO TRAP HANDLER!\n");
+	printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
 	return 1;
 }
Index: src/mainboard/hp/dl145_g3/mptable.c
===================================================================
--- src/mainboard/hp/dl145_g3/mptable.c	(revision 5263)
+++ src/mainboard/hp/dl145_g3/mptable.c	(working copy)
@@ -80,7 +80,7 @@
 	/* define bus and isa numbers */
 /*	for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
 		smp_write_bus(mc, bus_num, "PCI   ");
-		printk_debug("writing bus %d as PCI...\n",bus_num);
+		printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num);
 	}
 	*/
 	smp_write_bus(mc, 0, "PCI   ");
@@ -89,7 +89,7 @@
 	smp_write_bus(mc, 8, "PCI   ");
 
 	smp_write_bus(mc,m->bus_isa, "ISA   ");
-	printk_debug("writing %d as ISA...\n",m->bus_isa);
+	printk(BIOS_DEBUG, "writing %d as ISA...\n",m->bus_isa);
 
 	/*I/O APICs:   APIC ID Version State           Address*/
 	{
@@ -101,7 +101,7 @@
 			if (dev) {
 				res = find_resource(dev, PCI_BASE_ADDRESS_0);
 				if (res) {
-					printk_debug("APIC %d base address: %x\n",m->apicid_bcm5785[i],  res->base);
+					printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i],  res->base);
 					smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
 				}
 			}
@@ -160,14 +160,14 @@
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x5, m->apicid_bcm5785[0], 0x5);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_bcm5785[0], 0x6);
 	//SATA
-/* 	printk_debug("MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
+/* 	printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
 /*	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
-	printk_debug("MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
+	printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_bcm5785[0], 0x8);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x9, m->apicid_bcm5785[0], 0x9);
 	//USB
-	printk_debug("sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
+	printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
 
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xb, m->apicid_bcm5785[0], 0xb);
@@ -188,7 +188,7 @@
 
 	//IDE
 //     	outb(0x02, 0xc00); outb(0x0e, 0xc01);
-//	printk_debug("MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
+//	printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
 //		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
 
 	//onboard Broadcom GbE
@@ -206,13 +206,13 @@
 			uint32_t dword;
 			dword = pci_read_config32(dev, 0x6c);
 			dword |= (1<<4); // enable interrupts
-			printk_debug("6ch: %x\n",dword);
+			printk(BIOS_DEBUG, "6ch: %x\n",dword);
 			pci_write_config32(dev, 0x6c, dword);
 		}
 	}
 
 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-	printk_debug("m->bus_isa is: %x\n",m->bus_isa);
+	printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa);
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1);
 
@@ -231,7 +231,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/hp/dl145_g3/get_bus_conf.c
===================================================================
--- src/mainboard/hp/dl145_g3/get_bus_conf.c	(revision 5263)
+++ src/mainboard/hp/dl145_g3/get_bus_conf.c	(working copy)
@@ -98,25 +98,25 @@
 	m->bus_bcm5780[0] = m->bus_bcm5785_0;
 
 		/* bcm5785 */
-	printk_debug("search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0);
+	printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0);
 	dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));
 	if (dev) {
-		printk_debug("found dev %s...\n",dev_path(dev));
+		printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev));
 		m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		printk_debug("secondary is %d...\n",m->bus_bcm5785_1);
+		printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1);
 		dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0));
-		printk_debug("now found %s...\n",dev_path(dev));
+		printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev));
 		if(dev) {
 			m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 #if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
 			m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			m->bus_isa++;
-			printk_debug("bus_isa 1=%d\n",m->bus_isa);
+			printk(BIOS_DEBUG, "bus_isa 1=%d\n",m->bus_isa);
 #endif
 		}
 	}
 	else {
-		printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
+		printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
 	}
 
 		/* bcm5780 */
@@ -127,12 +127,12 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 			m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			m->bus_isa++;
-			printk_debug("bus_isa 2=%d\n",m->bus_isa);
+			printk(BIOS_DEBUG, "bus_isa 2=%d\n",m->bus_isa);
 #endif
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
 		}
 	}
 
Index: src/mainboard/tyan/s2912/mptable.c
===================================================================
--- src/mainboard/tyan/s2912/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2912/mptable.c	(working copy)
@@ -147,7 +147,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2912/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2912/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2912/irq_tables.c	(working copy)
@@ -76,7 +76,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -122,7 +122,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2912/get_bus_conf.c
===================================================================
--- src/mainboard/tyan/s2912/get_bus_conf.c	(revision 5263)
+++ src/mainboard/tyan/s2912/get_bus_conf.c	(working copy)
@@ -128,7 +128,7 @@
 			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
 		for(i=2; i<8;i++) {
@@ -137,7 +137,7 @@
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			}
 			else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
 			}
 		}
 
@@ -150,7 +150,7 @@
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max)
 			m->bus_isa = busn_max + 1;
-		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+		printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
 	}
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
Index: src/mainboard/tyan/s2850/mptable.c
===================================================================
--- src/mainboard/tyan/s2850/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2850/mptable.c	(working copy)
@@ -30,7 +30,7 @@
                 dst_link = (config_map >> 8) & 3;
                 bus_base = (config_map >> 16) & 0xff;
 #if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
                         dst_node, dst_link, bus_base,
                         reg, config_map);
 #endif
@@ -81,7 +81,7 @@
                 /* HT chain 0 */
                 bus_chain_0 = node_link_to_bus(0, 0);
                 if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
                         bus_chain_0 = 1;
                 }
                 /* 8111 */
@@ -92,7 +92,7 @@
                         bus_isa++;
                 }     
                 else {  
-                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
                         bus_8111_1 = 2;
                         bus_isa = 3;
@@ -194,7 +194,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2735/romstage.c
===================================================================
--- src/mainboard/tyan/s2735/romstage.c	(revision 5263)
+++ src/mainboard/tyan/s2735/romstage.c	(working copy)
@@ -145,7 +145,7 @@
 	                : "=a" (v_esp)
 	        );
 #if CONFIG_USE_INIT
-	        printk_debug("v_esp=%08x\r\n", v_esp);
+	        printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
 #else
 	        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
 #endif
@@ -157,7 +157,7 @@
 cpu_reset_x:
 
 #if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
+        printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset);
 #else
         print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
 #endif
@@ -206,7 +206,7 @@
                         print_debug("Use Ram as Stack now - \r\n");
                 }
 #if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+                printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
 #else
                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
 #endif
Index: src/mainboard/tyan/s2735/mptable.c
===================================================================
--- src/mainboard/tyan/s2735/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2735/mptable.c	(working copy)
@@ -154,7 +154,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2880/mptable.c
===================================================================
--- src/mainboard/tyan/s2880/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2880/mptable.c	(working copy)
@@ -30,7 +30,7 @@
                 dst_link = (config_map >> 8) & 3;
                 bus_base = (config_map >> 16) & 0xff;
 #if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
                         dst_node, dst_link, bus_base,
                         reg, config_map);
 #endif
@@ -86,7 +86,7 @@
                 /* HT chain 0 */
                 bus_chain_0 = node_link_to_bus(0, 0);
                 if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
                         bus_chain_0 = 1;
                 }
                 
@@ -98,7 +98,7 @@
                         bus_isa++; 
                 }       
                 else {
-                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
                         bus_8111_1 = 4;
                         bus_isa = 5;
@@ -110,7 +110,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
                         bus_8131_1 = 2;
                 }
@@ -121,7 +121,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
                         bus_8131_2 = 3;
                 }
@@ -237,7 +237,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2881/mptable.c
===================================================================
--- src/mainboard/tyan/s2881/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2881/mptable.c	(working copy)
@@ -141,7 +141,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2881/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2881/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2881/irq_tables.c	(working copy)
@@ -58,7 +58,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -100,7 +100,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2881/mainboard.c
===================================================================
--- src/mainboard/tyan/s2881/mainboard.c	(revision 5263)
+++ src/mainboard/tyan/s2881/mainboard.c	(working copy)
@@ -41,7 +41,7 @@
 	smbus_dev = dev_find_device(0x1022, 0x746b, 0);
 	if (!smbus_dev)
 		die("SMBus controller not found\n");
-	printk_debug("SMBus controller found\n");
+	printk(BIOS_DEBUG, "SMBus controller found\n");
 
 	/* Find the ADT7463 device. */
 	path.type = DEVICE_PATH_I2C;
@@ -49,7 +49,7 @@
 	adt7463 = find_dev_path(smbus_dev->link, &path);
 	if (!adt7463)
 		die("ADT7463 not found\n");
-	printk_debug("ADT7463 found\n");
+	printk(BIOS_DEBUG, "ADT7463 found\n");
 
 	/* Set all fans to 'Fastest Speed Calculated by All 3 Temperature
 	 * Channels Controls PWMx'.
@@ -95,7 +95,7 @@
 	/* Set TACH measurements to normal (1/second). */
 	result = smbus_write_byte(adt7463, 0x78, 0xf0);
 
-	printk_debug("ADT7463 properly initialized\n");
+	printk(BIOS_DEBUG, "ADT7463 properly initialized\n");
 }
 
 static void dummy_noop(device_t dummy)
@@ -117,7 +117,7 @@
 
 	max = root_dev_scan_bus(root, max);
 
-	printk_debug("scan_root_bus ok\n");
+	printk(BIOS_DEBUG, "scan_root_bus ok\n");
 
 	/* The following is a little silly. We need a hook into the boot
 	 * process *after* the ADT7463 device has been initialized. So we
@@ -128,7 +128,7 @@
 
 	link_i = root->links;
 	if (link_i >= MAX_LINKS) {
-		printk_debug("Reached MAX_LINKS, not configuring ADT7463");
+		printk(BIOS_DEBUG, "Reached MAX_LINKS, not configuring ADT7463");
 		return max;
 	}
 	root->link[link_i].link = link_i;
Index: src/mainboard/tyan/s2881/get_bus_conf.c
===================================================================
--- src/mainboard/tyan/s2881/get_bus_conf.c	(revision 5263)
+++ src/mainboard/tyan/s2881/get_bus_conf.c	(working copy)
@@ -85,11 +85,11 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                 bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 bus_isa++;
-//		printk_debug("bus_isa=%d\n",bus_isa);
+//		printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
         }
 	else {
-                printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
         }
 
         /* 8131-1 */
@@ -98,7 +98,7 @@
                 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
         }
 
         /* 8132-2 */
@@ -108,11 +108,11 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                 bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 bus_isa++;
-//              printk_debug("bus_isa=%d\n",bus_isa);
+//              printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
         }
 
 
Index: src/mainboard/tyan/s4880/mptable.c
===================================================================
--- src/mainboard/tyan/s4880/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s4880/mptable.c	(working copy)
@@ -29,7 +29,7 @@
                 dst_link = (config_map >> 8) & 3;
                 bus_base = (config_map >> 16) & 0xff;
 #if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
                         dst_node, dst_link, bus_base,
                         reg, config_map);
 #endif
@@ -85,7 +85,7 @@
                 /* HT chain 0 */
                 bus_chain_0 = node_link_to_bus(0, 2);
                 if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
                         bus_chain_0 = 1;
                 }
                 
@@ -97,7 +97,7 @@
                         bus_isa++; 
                 }       
                 else {
-                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
                         bus_8111_1 = 4;
                         bus_isa = 5;
@@ -109,7 +109,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
                         bus_8131_1 = 2;
                 }
@@ -120,7 +120,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
                         bus_8131_2 = 3;
                 }
@@ -246,7 +246,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2891/romstage.c
===================================================================
--- src/mainboard/tyan/s2891/romstage.c	(revision 5263)
+++ src/mainboard/tyan/s2891/romstage.c	(working copy)
@@ -172,7 +172,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		printk_info("ht reset -\r\n");
+		printk(BIOS_INFO, "ht reset -\r\n");
 		soft_reset();
 	}
 
Index: src/mainboard/tyan/s2891/mptable.c
===================================================================
--- src/mainboard/tyan/s2891/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2891/mptable.c	(working copy)
@@ -177,7 +177,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2891/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2891/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2891/irq_tables.c	(working copy)
@@ -67,7 +67,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -162,7 +162,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2891/acpi_tables.c
===================================================================
--- src/mainboard/tyan/s2891/acpi_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2891/acpi_tables.c	(working copy)
@@ -113,7 +113,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -131,21 +131,21 @@
 
 	current = ALIGN(current, 64);
 	facs = (acpi_facs_t *) current;
-	printk_debug("ACPI:    * FACS %p\n", facs);
+	printk(BIOS_DEBUG, "ACPI:    * FACS %p\n", facs);
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
 	current = ALIGN(current, 16);
 	dsdt = (acpi_header_t *) current;
-	printk_debug("ACPI:    * DSDT %p\n", dsdt);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT %p\n", dsdt);
 	current += ((acpi_header_t *) AmlCode)->length;
 	memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length);
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	current = ALIGN(current, 16);
 	fadt = (acpi_fadt_t *) current;
-	printk_debug("ACPI:    * FACP (FADT) @ %p\n", fadt);
+	printk(BIOS_DEBUG, "ACPI:    * FACP (FADT) @ %p\n", fadt);
 	current += sizeof(acpi_fadt_t);
 
 	/* Add FADT now that we have facs and dsdt. */
@@ -154,21 +154,21 @@
 
 	current = ALIGN(current, 16);
 	hpet = (acpi_hpet_t *) current;
-	printk_debug("ACPI:    * HPET @ %p\n", hpet);
+	printk(BIOS_DEBUG, "ACPI:    * HPET @ %p\n", hpet);
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
 	current = ALIGN(current, 16);
 	madt = (acpi_madt_t *) current;
-	printk_debug("ACPI:    * APIC/MADT @ %p\n", madt);
+	printk(BIOS_DEBUG, "ACPI:    * APIC/MADT @ %p\n", madt);
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
 	current = ALIGN(current, 16);
 	srat = (acpi_srat_t *) current;
-	printk_debug("ACPI:    * SRAT @ %p\n", srat);
+	printk(BIOS_DEBUG, "ACPI:    * SRAT @ %p\n", srat);
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
@@ -176,7 +176,7 @@
 	/* SLIT */
 	current = ALIGN(current, 16);
 	slit = (acpi_slit_t *) current;
-	printk_debug("ACPI:    * SLIT @ %p\n", slit);
+	printk(BIOS_DEBUG, "ACPI:    * SLIT @ %p\n", slit);
 	acpi_create_slit(slit);
 	current+=slit->header.length;
 	acpi_add_table(rsdp,slit);
@@ -184,11 +184,11 @@
 	/* SSDT */
 	current = ALIGN(current, 16);
 	ssdt = (acpi_header_t *)current;
-	printk_debug("ACPI:    * SSDT @ %p\n", ssdt);
+	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
-	printk_info("ACPI: done %p.\n", (void *)current);
+	printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current);
 	return current;
 }
Index: src/mainboard/tyan/s2891/get_bus_conf.c
===================================================================
--- src/mainboard/tyan/s2891/get_bus_conf.c	(revision 5263)
+++ src/mainboard/tyan/s2891/get_bus_conf.c	(working copy)
@@ -96,7 +96,7 @@
                         bus_ck804_4++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
 
                         bus_ck804_1 = 2;
                         bus_ck804_4 = 3;
@@ -109,7 +109,7 @@
                         bus_ck804_5++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
 
                         bus_ck804_5 = bus_ck804_4+1;
                 }
@@ -121,7 +121,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
                 }
 
 		bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
@@ -133,7 +133,7 @@
                         bus_8131_2++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
 
                         bus_8131_1 = bus_8131_0+1;
                         bus_8131_2 = bus_8131_0+2;
@@ -146,7 +146,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
 
                         bus_8131_2 = bus_8131_1+1;
                         bus_isa = bus_8131_1+2;
Index: src/mainboard/tyan/s2882/mptable.c
===================================================================
--- src/mainboard/tyan/s2882/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2882/mptable.c	(working copy)
@@ -31,7 +31,7 @@
                 dst_link = (config_map >> 8) & 3;
                 bus_base = (config_map >> 16) & 0xff;
 #if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
                         dst_node, dst_link, bus_base,
                         reg, config_map);
 #endif
@@ -85,7 +85,7 @@
                 /* HT chain 0 */
                 bus_chain_0 = node_link_to_bus(0, 0);
                 if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
                         bus_chain_0 = 1;
                 }
 
@@ -97,7 +97,7 @@
                         bus_isa++;
                 }     
                 else {  
-                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
                         bus_8111_1 = 4;
                         bus_isa = 5;
@@ -109,7 +109,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
                         bus_8131_1 = 2;
                 }
@@ -120,7 +120,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
                         bus_8131_2 = 3;
                 }
@@ -248,7 +248,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2882/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2882/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2882/irq_tables.c	(working copy)
@@ -64,7 +64,7 @@
                 dst_link = (config_map >> 8) & 3;
                 bus_base = (config_map >> 16) & 0xff;
 #if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
                         dst_node, dst_link, bus_base,
                         reg, config_map);
 #endif
@@ -115,7 +115,7 @@
                 /* HT chain 0 */
                 bus_chain_0 = node_link_to_bus(0, 0);
                 if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
                         bus_chain_0 = 1;
                 }
 
@@ -125,7 +125,7 @@
                         bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
                         bus_8111_1 = 4;
                 }
@@ -136,7 +136,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
                         bus_8131_1 = 2;
                 }
@@ -147,7 +147,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
                         bus_8131_2 = 3;
                 }
@@ -158,7 +158,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...\n", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...\n", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -197,67 +197,67 @@
                 }
         }
 
-        printk_debug("setting Onboard AMD Southbridge \n");
+        printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n");
         static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
         pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4);
         write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
 	
-        printk_debug("setting Onboard AMD USB \n");
+        printk(BIOS_DEBUG, "setting Onboard AMD USB \n");
         static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
         pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
         write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Onboard ATI Display Adapter\n");
+        printk(BIOS_DEBUG, "setting Onboard ATI Display Adapter\n");
         static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
         pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
         write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Slot 1\n");
+        printk(BIOS_DEBUG, "setting Slot 1\n");
         static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
         pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
         write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Slot 2\n");
+        printk(BIOS_DEBUG, "setting Slot 2\n");
         static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
         pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
         write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Slot 3\n");
+        printk(BIOS_DEBUG, "setting Slot 3\n");
         static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
         pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
         write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Slot 4\n");
+        printk(BIOS_DEBUG, "setting Slot 4\n");
         static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
         pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
         write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Slot 5 \n");
+        printk(BIOS_DEBUG, "setting Slot 5 \n");
         static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
         pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
         write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Onboard SI Serial ATA\n");
+        printk(BIOS_DEBUG, "setting Onboard SI Serial ATA\n");
         static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
         pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
         write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Onboard Intel NIC\n");
+        printk(BIOS_DEBUG, "setting Onboard Intel NIC\n");
         static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
         pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
         write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
 	pirq_info++; slot_num++;
 
-        printk_debug("setting Onboard Adaptec  SCSI\n");
+        printk(BIOS_DEBUG, "setting Onboard Adaptec  SCSI\n");
         static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
         pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
         write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
@@ -268,7 +268,7 @@
 	pirq_info++; slot_num++;
 #endif
 
-        printk_debug("setting Onboard Broadcom NIC\n");
+        printk(BIOS_DEBUG, "setting Onboard Broadcom NIC\n");
         static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };
         pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
         write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
@@ -296,7 +296,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2892/romstage.c
===================================================================
--- src/mainboard/tyan/s2892/romstage.c	(revision 5263)
+++ src/mainboard/tyan/s2892/romstage.c	(working copy)
@@ -156,7 +156,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		printk_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/tyan/s2892/mptable.c
===================================================================
--- src/mainboard/tyan/s2892/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2892/mptable.c	(working copy)
@@ -198,7 +198,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2892/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2892/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2892/irq_tables.c	(working copy)
@@ -65,7 +65,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -155,7 +155,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2892/acpi_tables.c
===================================================================
--- src/mainboard/tyan/s2892/acpi_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2892/acpi_tables.c	(working copy)
@@ -113,7 +113,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -131,21 +131,21 @@
 
 	current = ALIGN(current, 64);
 	facs = (acpi_facs_t *) current;
-	printk_debug("ACPI:    * FACS %p\n", facs);
+	printk(BIOS_DEBUG, "ACPI:    * FACS %p\n", facs);
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
 	current = ALIGN(current, 16);
 	dsdt = (acpi_header_t *) current;
-	printk_debug("ACPI:    * DSDT %p\n", dsdt);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT %p\n", dsdt);
 	current += ((acpi_header_t *) AmlCode)->length;
 	memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length);
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	current = ALIGN(current, 16);
 	fadt = (acpi_fadt_t *) current;
-	printk_debug("ACPI:    * FACP (FADT) @ %p\n", fadt);
+	printk(BIOS_DEBUG, "ACPI:    * FACP (FADT) @ %p\n", fadt);
 	current += sizeof(acpi_fadt_t);
 
 	/* Add FADT now that we have facs and dsdt. */
@@ -154,21 +154,21 @@
 
 	current = ALIGN(current, 16);
 	hpet = (acpi_hpet_t *) current;
-	printk_debug("ACPI:    * HPET @ %p\n", hpet);
+	printk(BIOS_DEBUG, "ACPI:    * HPET @ %p\n", hpet);
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
 	current = ALIGN(current, 16);
 	madt = (acpi_madt_t *) current;
-	printk_debug("ACPI:    * APIC/MADT @ %p\n", madt);
+	printk(BIOS_DEBUG, "ACPI:    * APIC/MADT @ %p\n", madt);
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
 	current = ALIGN(current, 16);
 	srat = (acpi_srat_t *) current;
-	printk_debug("ACPI:    * SRAT @ %p\n", srat);
+	printk(BIOS_DEBUG, "ACPI:    * SRAT @ %p\n", srat);
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
@@ -176,7 +176,7 @@
 	/* SLIT */
 	current = ALIGN(current, 16);
 	slit = (acpi_slit_t *) current;
-	printk_debug("ACPI:    * SLIT @ %p\n", slit);
+	printk(BIOS_DEBUG, "ACPI:    * SLIT @ %p\n", slit);
 	acpi_create_slit(slit);
 	current+=slit->header.length;
 	acpi_add_table(rsdp,slit);
@@ -184,11 +184,11 @@
 	/* SSDT */
 	current = ALIGN(current, 16);
 	ssdt = (acpi_header_t *)current;
-	printk_debug("ACPI:    * SSDT @ %p\n", ssdt);
+	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
-	printk_info("ACPI: done %p.\n", (void *)current);
+	printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current);
 	return current;
 }
Index: src/mainboard/tyan/s2892/get_bus_conf.c
===================================================================
--- src/mainboard/tyan/s2892/get_bus_conf.c	(revision 5263)
+++ src/mainboard/tyan/s2892/get_bus_conf.c	(working copy)
@@ -93,7 +93,7 @@
                         bus_ck804_4++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
 
                         bus_ck804_1 = 2;
                         bus_ck804_4 = 3;
@@ -106,7 +106,7 @@
                         bus_ck804_5++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
 
                         bus_ck804_5 = bus_ck804_4+1;
                 }
@@ -118,7 +118,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
                 }
 
 		bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
@@ -130,7 +130,7 @@
                         bus_8131_2++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
 
                         bus_8131_1 = bus_8131_0+1;
                         bus_8131_2 = bus_8131_0+2;
@@ -143,7 +143,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
 
                         bus_8131_2 = bus_8131_1+1;
                         bus_isa = bus_8131_1+2;
Index: src/mainboard/tyan/s4882/mptable.c
===================================================================
--- src/mainboard/tyan/s4882/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s4882/mptable.c	(working copy)
@@ -30,7 +30,7 @@
                 dst_link = (config_map >> 8) & 3;
                 bus_base = (config_map >> 16) & 0xff;
 #if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
                         dst_node, dst_link, bus_base,
                         reg, config_map);
 #endif
@@ -86,7 +86,7 @@
                 /* HT chain 0 */
                 bus_chain_0 = node_link_to_bus(0, 1);
                 if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
                         bus_chain_0 = 1;
                 }
  
@@ -98,7 +98,7 @@
                         bus_isa++; 
                 }       
                 else {
-                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
                         bus_8111_1 = 4;
                         bus_isa = 5;
@@ -110,7 +110,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
                         bus_8131_1 = 2;
                 }
@@ -121,7 +121,7 @@
 
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
                         bus_8131_2 = 3;
                 }
@@ -246,7 +246,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2875/mptable.c
===================================================================
--- src/mainboard/tyan/s2875/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2875/mptable.c	(working copy)
@@ -29,7 +29,7 @@
                 dst_link = (config_map >> 8) & 3;
                 bus_base = (config_map >> 16) & 0xff;
 #if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
                         dst_node, dst_link, bus_base,
                         reg, config_map);
 #endif
@@ -81,7 +81,7 @@
                 /* HT chain 0 */
                 bus_chain_0 = node_link_to_bus(0, 0);
                 if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
                         bus_chain_0 = 1;
                 }
 
@@ -91,10 +91,10 @@
                         bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                         bus_isa++;
-			printk_debug("bus_isa=%d\n",bus_isa);
+			printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
                         bus_8111_1 = 3;
                         bus_isa = 4;
@@ -103,11 +103,11 @@
                 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
                 if (dev) {
                         bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        printk_debug("bus_8151_1=%d\n",bus_8151_1);
+                        printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1);
    
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
                         bus_8151_1 = 2;
                 }
@@ -209,7 +209,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2885/mptable.c
===================================================================
--- src/mainboard/tyan/s2885/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2885/mptable.c	(working copy)
@@ -152,7 +152,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2885/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2885/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2885/irq_tables.c	(working copy)
@@ -61,7 +61,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -105,7 +105,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2885/get_bus_conf.c
===================================================================
--- src/mainboard/tyan/s2885/get_bus_conf.c	(revision 5263)
+++ src/mainboard/tyan/s2885/get_bus_conf.c	(working copy)
@@ -88,11 +88,11 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                 bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 bus_isa++;
-//		printk_debug("bus_isa=%d\n",bus_isa);
+//		printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
         }
 	else {
-                printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
         }
 
         /* 8131-1 */
@@ -101,7 +101,7 @@
                 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
         }
 
         /* 8132-2 */
@@ -111,12 +111,12 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                 bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 bus_isa++;
-//              printk_debug("bus_isa=%d\n",bus_isa);
+//              printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
 #endif
 
         }
         else {
-                printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
         }
 
         /* HT chain 1 */
@@ -127,7 +127,7 @@
 
         if (dev) {
            	bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-//              printk_debug("bus_8151_1=%d\n",bus_8151_1);
+//              printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1);
                 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
        	        bus_isa++;
        	}
Index: src/mainboard/tyan/s2895/romstage.c
===================================================================
--- src/mainboard/tyan/s2895/romstage.c	(revision 5263)
+++ src/mainboard/tyan/s2895/romstage.c	(working copy)
@@ -200,7 +200,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		printk_info("ht reset -\n");
+		printk(BIOS_INFO, "ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/tyan/s2895/mptable.c
===================================================================
--- src/mainboard/tyan/s2895/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2895/mptable.c	(working copy)
@@ -226,7 +226,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2895/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2895/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2895/irq_tables.c	(working copy)
@@ -72,7 +72,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -174,7 +174,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2895/acpi_tables.c
===================================================================
--- src/mainboard/tyan/s2895/acpi_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2895/acpi_tables.c	(working copy)
@@ -138,7 +138,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -156,21 +156,21 @@
 
 	current = ALIGN(current, 64);
 	facs = (acpi_facs_t *) current;
-	printk_debug("ACPI:    * FACS %p\n", facs);
+	printk(BIOS_DEBUG, "ACPI:    * FACS %p\n", facs);
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
 	current = ALIGN(current, 16);
 	dsdt = (acpi_header_t *) current;
-	printk_debug("ACPI:    * DSDT %p\n", dsdt);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT %p\n", dsdt);
 	current += ((acpi_header_t *) AmlCode)->length;
 	memcpy((void*) dsdt, (void*)AmlCode, ((acpi_header_t*)AmlCode)->length);
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	current = ALIGN(current, 16);
 	fadt = (acpi_fadt_t *) current;
-	printk_debug("ACPI:    * FACP (FADT) @ %p\n", fadt);
+	printk(BIOS_DEBUG, "ACPI:    * FACP (FADT) @ %p\n", fadt);
 	current += sizeof(acpi_fadt_t);
 
 	/* Add FADT now that we have facs and dsdt. */
@@ -179,21 +179,21 @@
 
 	current = ALIGN(current, 16);
 	hpet = (acpi_hpet_t *) current;
-	printk_debug("ACPI:    * HPET @ %p\n", hpet);
+	printk(BIOS_DEBUG, "ACPI:    * HPET @ %p\n", hpet);
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
 	current = ALIGN(current, 16);
 	madt = (acpi_madt_t *) current;
-	printk_debug("ACPI:    * APIC/MADT @ %p\n", madt);
+	printk(BIOS_DEBUG, "ACPI:    * APIC/MADT @ %p\n", madt);
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
 	current = ALIGN(current, 16);
 	srat = (acpi_srat_t *) current;
-	printk_debug("ACPI:    * SRAT @ %p\n", srat);
+	printk(BIOS_DEBUG, "ACPI:    * SRAT @ %p\n", srat);
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
@@ -201,7 +201,7 @@
 	/* SLIT */
 	current = ALIGN(current, 16);
 	slit = (acpi_slit_t *) current;
-	printk_debug("ACPI:    * SLIT @ %p\n", slit);
+	printk(BIOS_DEBUG, "ACPI:    * SLIT @ %p\n", slit);
 	acpi_create_slit(slit);
 	current+=slit->header.length;
 	acpi_add_table(rsdp,slit);
@@ -209,11 +209,11 @@
 	/* SSDT */
 	current = ALIGN(current, 16);
 	ssdt = (acpi_header_t *)current;
-	printk_debug("ACPI:    * SSDT @ %p\n", ssdt);
+	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
-	printk_info("ACPI: done %p.\n", (void *)current);
+	printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current);
 	return current;
 }
Index: src/mainboard/tyan/s2895/get_bus_conf.c
===================================================================
--- src/mainboard/tyan/s2895/get_bus_conf.c	(revision 5263)
+++ src/mainboard/tyan/s2895/get_bus_conf.c	(working copy)
@@ -102,7 +102,7 @@
                         bus_ck804_5++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
 
                         bus_ck804_1 = 2;
                         bus_ck804_5 = 3;
@@ -113,7 +113,7 @@
                         bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
                 }
 
 		bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
@@ -125,7 +125,7 @@
                         bus_8131_2++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
 
                         bus_8131_1 = bus_8131_0+1;
                         bus_8131_2 = bus_8131_0+2;
@@ -138,7 +138,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
 
                         bus_8131_2 = bus_8131_1+1;
                 }
@@ -155,7 +155,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
                         bus_ck804b_5 = bus_ck804b_4+1;
                         bus_isa = bus_ck804b_5+1;
                 }
Index: src/mainboard/tyan/s2912_fam10/romstage.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/romstage.c	(revision 5263)
+++ src/mainboard/tyan/s2912_fam10/romstage.c	(working copy)
@@ -198,7 +198,7 @@
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
@@ -209,10 +209,10 @@
 #endif
 
 	val = cpuid_eax(1);
-	printk_debug("BSP Family_Model: %08x\n", val);
-	printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
-	printk_debug("bsp_apicid = %02x\n", bsp_apicid);
-	printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+	printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08x\n", cpu_init_detectedx);
 
 	/* Setup sysinfo defaults */
 	set_sysinfo_in_ram(0);
@@ -243,7 +243,7 @@
 
 #if CONFIG_LOGICAL_CPUS==1
 	/* Core0 on each node is configured. Now setup any additional cores. */
-	printk_debug("start_other_cores()\n");
+	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
 	post_code(0x37);
 	wait_all_other_cores_started(bsp_apicid);
@@ -253,7 +253,7 @@
 
 #if FAM10_SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
-	printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
 	/* FIXME: The sb fid change may survive the warm reset and only
 	 * need to be done once.*/
@@ -271,7 +271,7 @@
 
 	/* show final fid and vid */
 	msr=rdmsr(0xc0010071);
-	printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
 	wants_reset = mcp55_early_setup_x();
@@ -284,27 +284,27 @@
 	}
 
 	if (wants_reset)
-		printk_debug("mcp55_early_setup_x wanted additional reset!\n");
+		printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 
 	post_code(0x3B);
 
 	/* It's the time to set ctrl in sysinfo now; */
-	printk_debug("fill_mem_ctrl()\n");
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	post_code(0x3D);
 
-	printk_debug("enable_smbus()\n");
+	printk(BIOS_DEBUG, "enable_smbus()\n");
 	enable_smbus();
 	post_code(0x3E);
 
 	memreset_setup();
 	post_code(0x40);
 
-	printk_debug("raminit_amdmct()\n");
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
 	post_code(0x41);
 
-	printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
Index: src/mainboard/tyan/s2912_fam10/mptable.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/mptable.c	(revision 5263)
+++ src/mainboard/tyan/s2912_fam10/mptable.c	(working copy)
@@ -147,7 +147,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/tyan/s2912_fam10/irq_tables.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/irq_tables.c	(revision 5263)
+++ src/mainboard/tyan/s2912_fam10/irq_tables.c	(working copy)
@@ -76,7 +76,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -131,7 +131,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/tyan/s2912_fam10/get_bus_conf.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/get_bus_conf.c	(revision 5263)
+++ src/mainboard/tyan/s2912_fam10/get_bus_conf.c	(working copy)
@@ -101,7 +101,7 @@
 			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
 		for(i=2; i<8;i++) {
@@ -110,7 +110,7 @@
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			}
 			else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
 			}
 		}
 
@@ -123,7 +123,7 @@
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max)
 			m->bus_isa = busn_max + 1;
-		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+		printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
 	}
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
Index: src/mainboard/pcengines/alix1c/mainboard.c
===================================================================
--- src/mainboard/pcengines/alix1c/mainboard.c	(revision 5263)
+++ src/mainboard/pcengines/alix1c/mainboard.c	(working copy)
@@ -23,8 +23,8 @@
 
 static void init(struct device *dev)
 {
-	printk_debug("ALIX1.C ENTER %s\n", __func__);
-	printk_debug("ALIX1.C EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "ALIX1.C ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "ALIX1.C EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/artecgroup/dbe61/realmode/vgabios.c
===================================================================
--- src/mainboard/artecgroup/dbe61/realmode/vgabios.c	(revision 5263)
+++ src/mainboard/artecgroup/dbe61/realmode/vgabios.c	(working copy)
@@ -248,16 +248,16 @@
 	}
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
 	//pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
-	printk_debug("rom base, size: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
 
 	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -269,13 +269,13 @@
 		buf = (unsigned char *) 0xc0000;
 		if (buf[0]==0x55 && buf[1]==0xAA) {
 			busdevfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 		    	real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else 
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -579,28 +579,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 	
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
 		      eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *) esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *) esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -619,7 +619,7 @@
 				&ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", 
 			    intnumber);
 		break;
 	}
@@ -697,7 +697,7 @@
 			// devfn is an int, so we mask it off. 
 			busdevfn = (dev->bus->secondary << 8)
 				| (dev->path.pci.devfn & 0xff);
-			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			*pebx = busdevfn;
 			retval = 0;
 		} else {
@@ -723,7 +723,7 @@
 		reg = *pedi;
 		dev = dev_find_slot(bus, devfn);
 		if (! dev) {
-			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
 			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 			*peax = PCIBIOS_BADREG;
 			retval = -1;
@@ -757,14 +757,14 @@
 		
 		if (retval) 
 			retval = PCIBIOS_BADREG;
-		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+		printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 		*peax = 0;
 		retval = 0;
 	}
 	break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
 		break;
 	}
 	
@@ -891,9 +891,9 @@
 	pci_dev_init(dev);
 
 	// code to make vga init run in real mode - does work but against the current coreboot philosophy 
-    printk_debug("INSTALL REAL-MODE IDT\n");
+    printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
     setup_realmode_idt();
-    printk_debug("DO THE VGA BIOS\n");
+    printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
     do_vgabios(dev);
 
     vga_enable_console();
@@ -918,7 +918,7 @@
  * */
 
 void vga_configure_pci(device_t dev){
-	printk_debug("Setting VGA callback\n");
+	printk(BIOS_DEBUG, "Setting VGA callback\n");
 	dev->ops = &drivers_pci_realmode_dev_ops;
 }
 
Index: src/mainboard/artecgroup/dbe61/mainboard.c
===================================================================
--- src/mainboard/artecgroup/dbe61/mainboard.c	(revision 5263)
+++ src/mainboard/artecgroup/dbe61/mainboard.c	(working copy)
@@ -31,20 +31,20 @@
 static void init_gpio()
 {
 	msr_t msr;
-	printk_debug("Checking GPIO module...\n");
+	printk(BIOS_DEBUG, "Checking GPIO module...\n");
 
 	msr = rdmsr(MDD_LBAR_GPIO);
-	printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
 }
 
 static void init(struct device *dev)
 {
 	// BOARD-SPECIFIC INIT
-	printk_debug("ARTECGROUP DBE61 ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "ARTECGROUP DBE61 ENTER %s\n", __func__);
 
 	init_gpio();
 
-	printk_debug("ARTECGROUP DBE61 EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "ARTECGROUP DBE61 EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/lippert/roadrunner-lx/mainboard.c
===================================================================
--- src/mainboard/lippert/roadrunner-lx/mainboard.c	(revision 5263)
+++ src/mainboard/lippert/roadrunner-lx/mainboard.c	(working copy)
@@ -42,7 +42,7 @@
 {
 	struct mainboard_config *mb = dev->chip_info;
 	unsigned int gpio_base, i;
-	printk_debug("LiPPERT RoadRunner-LX ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX ENTER %s\n", __func__);
 
 	/* Init CS5536 GPIOs. */
 	gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
@@ -62,7 +62,7 @@
 	}
 
 	outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */
-	printk_debug("LiPPERT RoadRunner-LX EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/lippert/spacerunner-lx/mainboard.c
===================================================================
--- src/mainboard/lippert/spacerunner-lx/mainboard.c	(revision 5263)
+++ src/mainboard/lippert/spacerunner-lx/mainboard.c	(working copy)
@@ -43,7 +43,7 @@
 {
 	struct mainboard_config *mb = dev->chip_info;
 	unsigned int gpio_base, i;
-	printk_debug("LiPPERT SpaceRunner-LX ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__);
 
 	/* Init CS5536 GPIOs */
 	gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
@@ -66,7 +66,7 @@
 	}
 
 	outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */
-	printk_debug("LiPPERT SpaceRunner-LX EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/via/epia-m700/acpi_tables.c
===================================================================
--- src/mainboard/via/epia-m700/acpi_tables.c	(revision 5263)
+++ src/mainboard/via/epia-m700/acpi_tables.c	(working copy)
@@ -135,7 +135,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
@@ -150,22 +150,22 @@
 	acpi_write_rsdt(rsdt);
 
 	/* We explicitly add these tables later on: */
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	current = ALIGN(current, 64);
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	printk_debug("ACPI:     * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:     * DSDT\n");
 	dsdt = (acpi_header_t *) current;
 	current += ((acpi_header_t *) AmlCode_dsdt)->length;
 	memcpy((void *)dsdt, (void *)AmlCode_dsdt,
 	       ((acpi_header_t *) AmlCode_dsdt)->length);
 	dsdt->checksum = 0; /* Don't trust iasl to get this right. */
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -173,7 +173,7 @@
 	acpi_add_table(rsdp, fadt);
 
 	/* If we want to use HPET timers Linux wants it in MADT. */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -181,24 +181,24 @@
 
 	/* NO MCFG in VX855, no PCI-E. */
 
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_mcfg_t *) current;
 	acpi_create_hpet(hpet);
 	current += hpet->header.length;
 	acpi_add_table(rsdp, hpet);
 
 #if 0
-	printk_debug("ACPI:     * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *) current;
 	current += ((acpi_header_t *)AmlCode_ssdt)->length;
 	memcpy((void *)ssdt,(void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
 	ssdt->checksum = 0; /* Don't trust iasl to get this right. */
 	ssdt->checksum = acpi_checksum(ssdt, ssdt->length);
 	acpi_add_table(rsdp, ssdt);
-	printk_debug("ACPI:     * SSDT @ %08x Length %x\n", ssdt, ssdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * SSDT @ %08x Length %x\n", ssdt, ssdt->length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/via/epia-m700/romstage.c
===================================================================
--- src/mainboard/via/epia-m700/romstage.c	(revision 5263)
+++ src/mainboard/via/epia-m700/romstage.c	(working copy)
@@ -729,7 +729,7 @@
 		unsigned v_esp;
 		__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
 #if CONFIG_USE_INIT
-		printk_debug("v_esp=%08x\r\n", v_esp);
+		printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
 #else
 		print_debug("v_esp=");
 		print_debug_hex32(v_esp);
@@ -748,7 +748,7 @@
 	cpu_reset = 0;
 
 #if CONFIG_USE_INIT
-	printk_debug("cpu_reset = %08x\r\n", cpu_reset);
+	printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
 #else
 	print_debug("cpu_reset = ");
 	print_debug_hex32(cpu_reset);
@@ -798,7 +798,7 @@
 			print_debug("Use Ram as Stack now - \r\n");
 
 #if CONFIG_USE_INIT
-		printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+		printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
 #else
 		print_debug("new_cpu_reset = ");
 		print_debug_hex32(new_cpu_reset);
Index: src/mainboard/via/epia-m700/wakeup.c
===================================================================
--- src/mainboard/via/epia-m700/wakeup.c	(revision 5263)
+++ src/mainboard/via/epia-m700/wakeup.c	(working copy)
@@ -116,13 +116,13 @@
 	u8 Data;
 	struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
 
-	printk_debug("IN ACPI JUMP WAKE TO %x\n", vector);
+	printk(BIOS_DEBUG, "IN ACPI JUMP WAKE TO %x\n", vector);
 	if (enable_a20())
 		die("failed to enable A20\n");
-	printk_debug("IN ACPI JUMP WAKE TO 3 %x\n", vector);
+	printk(BIOS_DEBUG, "IN ACPI JUMP WAKE TO 3 %x\n", vector);
 
 	*((u16 *) (jump_to_wakeup + 3)) = (u16) (vector >> 4);
-	printk_debug("%x %x %x %x %x\n", jump_to_wakeup[0], jump_to_wakeup[1],
+	printk(BIOS_DEBUG, "%x %x %x %x %x\n", jump_to_wakeup[0], jump_to_wakeup[1],
 		     jump_to_wakeup[2], jump_to_wakeup[3], jump_to_wakeup[4]);
 
 	memcpy((void *)(WAKE_THUNK16_ADDR - sizeof(real_mode_switch) - 100),
@@ -131,7 +131,7 @@
 	       sizeof(jump_to_wakeup));
 
 	//jason_tsc_count();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 	//jason_tsc_count_end();
 
 	unsigned long long *real_mode_gdt_entries_at_eseg;
Index: src/mainboard/via/vt8454c/mptable.c
===================================================================
--- src/mainboard/via/vt8454c/mptable.c	(revision 5263)
+++ src/mainboard/via/vt8454c/mptable.c	(working copy)
@@ -92,7 +92,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
 
Index: src/mainboard/via/vt8454c/acpi_tables.c
===================================================================
--- src/mainboard/via/vt8454c/acpi_tables.c	(revision 5263)
+++ src/mainboard/via/vt8454c/acpi_tables.c	(working copy)
@@ -135,7 +135,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -153,7 +153,7 @@
 	 * We explicitly add these tables later on:
 	 */
 
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
@@ -161,20 +161,20 @@
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
@@ -187,9 +187,9 @@
 	dsdt->checksum = 0;	// don't trust intel iasl compiler to get this right
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
 #endif
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
@@ -197,9 +197,9 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_debug("ACPI:     * DMI (Linux workaround)\n");
+	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
 	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/via/epia-m/acpi_tables.c
===================================================================
--- src/mainboard/via/epia-m/acpi_tables.c	(revision 5263)
+++ src/mainboard/via/epia-m/acpi_tables.c	(working copy)
@@ -52,7 +52,7 @@
 	start   = ( start + 0x0f ) & -0x10;
 	current = start;
 	
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -69,7 +69,7 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
@@ -79,8 +79,8 @@
 	memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
 	dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
 	dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
@@ -88,7 +88,7 @@
 	acpi_create_fadt(fadt,facs,dsdt);
 	acpi_add_table(rsdp,fadt);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/via/epia-m/vgabios.c
===================================================================
--- src/mainboard/via/epia-m/vgabios.c	(revision 5263)
+++ src/mainboard/via/epia-m/vgabios.c	(working copy)
@@ -349,17 +349,17 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
 	rom = (unsigned int)cbfs_load_optionrom(dev->vendor, dev->device, 0); 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
-	printk_debug("rom base, size: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
 
 	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -371,13 +371,13 @@
 		buf = (unsigned char *) 0xc0000;
 		if (buf[0]==0x55 && buf[1]==0xAA) {
 			busdevfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 		    	real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else 
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -562,28 +562,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 	
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
 		      eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *) esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *) esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -602,7 +602,7 @@
 				&ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", 
 			    intnumber);
 		break;
 	}
@@ -728,7 +728,7 @@
 			// devfn is an int, so we mask it off. 
 			busdevfn = (dev->bus->secondary << 8)
 				| (dev->path.pci.devfn & 0xff);
-			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			*pebx = busdevfn;
 			retval = 0;
 		} else {
@@ -754,7 +754,7 @@
 		reg = *pedi;
 		dev = dev_find_slot(bus, devfn);
 		if (! dev) {
-			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
 			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 			*peax = PCIBIOS_BADREG;
 			retval = -1;
@@ -788,14 +788,14 @@
 		
 		if (retval) 
 			retval = PCIBIOS_BADREG;
-		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+		printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 		*peax = 0;
 		retval = 0;
 	}
 	break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
 		break;
 	}
 	
Index: src/mainboard/via/epia-m/mainboard.c
===================================================================
--- src/mainboard/via/epia-m/mainboard.c	(revision 5263)
+++ src/mainboard/via/epia-m/mainboard.c	(working copy)
@@ -16,9 +16,9 @@
         //   that
         // - we need page 0 below for coreboot tables.
 
-        printk_debug("INSTALL REAL-MODE IDT\n");
+        printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
         setup_realmode_idt();
-        printk_debug("DO THE VGA BIOS\n");
+        printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
         do_vgabios();
         post_code(0x93);
 	vga_enable_console();
@@ -30,7 +30,7 @@
 {
  	device_t dev;
  
- 	printk_info("write_protect_vgabios\n");
+ 	printk(BIOS_INFO, "write_protect_vgabios\n");
 	/* there are two possible devices. Just do both. */
  	dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
  	if(dev)
Index: src/mainboard/via/epia-n/mptable.c
===================================================================
--- src/mainboard/via/epia-n/mptable.c	(revision 5263)
+++ src/mainboard/via/epia-n/mptable.c	(working copy)
@@ -102,7 +102,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/via/epia-n/acpi_tables.c
===================================================================
--- src/mainboard/via/epia-n/acpi_tables.c	(revision 5263)
+++ src/mainboard/via/epia-n/acpi_tables.c	(working copy)
@@ -136,7 +136,7 @@
 	start   = ( start + 0x0f ) & -0x10;
 	current = start;
 	
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -153,20 +153,20 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	current = ALIGN(current, 64);
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	printk_debug("ACPI:     * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:     * DSDT\n");
 	dsdt = (acpi_header_t *)current;
 	current += ((acpi_header_t *)AmlCode)->length;
 	memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
 	dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
 	dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
@@ -175,13 +175,13 @@
 	acpi_add_table(rsdp,fadt);
 
 	/* If we want IOAPIC Support Linux wants it in MADT. */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/via/pc2500e/mptable.c
===================================================================
--- src/mainboard/via/pc2500e/mptable.c	(revision 5263)
+++ src/mainboard/via/pc2500e/mptable.c	(working copy)
@@ -146,7 +146,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/dell/s1850/mptable.c
===================================================================
--- src/mainboard/dell/s1850/mptable.c	(revision 5263)
+++ src/mainboard/dell/s1850/mptable.c	(working copy)
@@ -48,7 +48,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 
 			bus_ich5r_1 = 7;
 			bus_isa = 8;
@@ -60,7 +60,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
 
 			bus_pxhd_1 = 2;
 		}
@@ -71,7 +71,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.2, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
 
 			bus_pxhd_2 = 3;
 		}
@@ -83,7 +83,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:04.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
 
 			bus_pxhd_3 = 5;
 		}
@@ -94,7 +94,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:06.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
 
 			bus_pxhd_4 = 6;
 		}
@@ -122,7 +122,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 		}
 		/* pxhd apic 4 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
@@ -133,7 +133,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 		}
 	}	
 	/* ISA backward compatibility interrupts  */
@@ -205,7 +205,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/roda/rk886ex/mainboard_smi.c
===================================================================
--- src/mainboard/roda/rk886ex/mainboard_smi.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/mainboard_smi.c	(working copy)
@@ -33,7 +33,7 @@
 {
 	switch (smif) {
 	case 0x99:
-		printk_debug("Sample\n");
+		printk(BIOS_DEBUG, "Sample\n");
 		//gnvs->smif = 0;
 		break;
 	default:
Index: src/mainboard/roda/rk886ex/acpi_tables.c
===================================================================
--- src/mainboard/roda/rk886ex/acpi_tables.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/acpi_tables.c	(working copy)
@@ -219,7 +219,7 @@
 	/* Align ACPI tables to 16byte */
 	ALIGN_CURRENT;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -242,7 +242,7 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
@@ -251,7 +251,7 @@
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
@@ -259,14 +259,14 @@
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	ALIGN_CURRENT;
@@ -303,7 +303,7 @@
 	/* Pack GNVS into the ACPI table area */
 	for (i=0; i < dsdt->length; i++) {
 		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
 			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
 			break;
 		}
@@ -325,18 +325,18 @@
 	dsdt->checksum = 0;
 	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
 
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
 
 #if CONFIG_HAVE_ACPI_SLIC
-	printk_debug("ACPI:     * SLIC\n");
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
 	slic = (acpi_header_t *)current;
 	current += acpi_create_slic(current);
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, slic);
 #endif
 
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 	ALIGN_CURRENT;
@@ -344,16 +344,16 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_debug("ACPI:     * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 	acpi_create_ssdt_generator(ssdt, "COREBOOT");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 	ALIGN_CURRENT;
 
-	printk_debug("current = %lx\n", current);
+	printk(BIOS_DEBUG, "current = %lx\n", current);
 
-	printk_debug("ACPI:     * DMI (Linux workaround)\n");
+	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
 	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
@@ -361,10 +361,10 @@
 	ALIGN_CURRENT;
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 
 	/* Enable Dummy DCC ON# for DVI */
-	printk_debug("Laptop handling...\n");
+	printk(BIOS_DEBUG, "Laptop handling...\n");
 	outb(inb(0x60f) & ~(1 << 5), 0x60f);
 
 	return current;
Index: src/mainboard/roda/rk886ex/romstage.c
===================================================================
--- src/mainboard/roda/rk886ex/romstage.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/romstage.c	(working copy)
@@ -58,7 +58,7 @@
 #include "southbridge/intel/i82801gx/i82801gx.h"
 static void setup_ich7_gpios(void)
 {
-	printk_debug(" GPIOS...");
+	printk(BIOS_DEBUG, " GPIOS...");
 	/* General Registers */
 	outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
 	outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
@@ -304,7 +304,7 @@
 	report_bist_failure(bist);
 
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk_debug("soft reset detected.\n");
+		printk(BIOS_DEBUG, "soft reset detected.\n");
 		boot_mode = 1;
 	}
 
@@ -318,10 +318,10 @@
 
 	/* Read PM1_CNT */
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
-	printk_debug("PM1_CNT: %08x\n", reg32);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
 #if CONFIG_HAVE_ACPI_RESUME
-		printk_debug("Resume from S3 detected.\n");
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 		boot_mode = 2;
 		/* Clear SLP_TYPE. This will break stage2 but
 		 * we care for that when we get there.
@@ -329,7 +329,7 @@
 		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 
 #else
-		printk_debug("Resume from S3 detected, but disabled.\n");
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 #endif
 	}
 
@@ -365,7 +365,7 @@
 		/* This will not work if TSEG is in place! */
 		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 
-		printk_debug("TOM: 0x%08x\n", tom);
+		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
 		ram_check(0x00100000, tom);
 	}
Index: src/mainboard/roda/rk886ex/m3885.c
===================================================================
--- src/mainboard/roda/rk886ex/m3885.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/m3885.c	(working copy)
@@ -118,10 +118,10 @@
 	while ((inb(KBD_SC) & KBD_IBF) && --timeout) {
 		udelay(10);
 		if ((timeout & 0xff) == 0)
-			printk_spew(".");
+			printk(BIOS_SPEW, ".");
 	}
 	if (!timeout) {
-		printk_debug("Timeout while sending command 0x%02x to EC!\n", 
+		printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", 
 				command);
 		// return -1;
 	}
@@ -138,10 +138,10 @@
 	while ((inb(KBD_SC) & KBD_IBF) && --timeout) { // wait for IBF = 0
 		udelay(10);
 		if ((timeout & 0xff) == 0)
-			printk_spew(".");
+			printk(BIOS_SPEW, ".");
 	}
 	if (!timeout) {
-		printk_debug("Timeout while sending data 0x%02x to EC!\n",
+		printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n",
 				data);
 		// return -1;
 	}
@@ -164,10 +164,10 @@
 		}
 		udelay(10);
 		if ((timeout & 0xff) == 0)
-			printk_spew(".");
+			printk(BIOS_SPEW, ".");
 	}
 	if (!timeout) {
-		printk_debug("\nTimeout while receiving data from EC!\n");
+		printk(BIOS_DEBUG, "\nTimeout while receiving data from EC!\n");
 		// return -1;
 	}
 
@@ -186,13 +186,13 @@
 	send_kbd_command(0xbc);
 	send_kbd_command(0xff);
 	ret = recv_kbd_data();
-	printk_spew("m3885: get variable %02x = %02x\n", index, ret);
+	printk(BIOS_SPEW, "m3885: get variable %02x = %02x\n", index, ret);
 	return ret;
 }
 
 static void m3885_set_variable(u8 index, u8 data)
 {
-	printk_spew("m3885: set variable %02x = %02x\n", index, data);
+	printk(BIOS_SPEW, "m3885: set variable %02x = %02x\n", index, data);
 	send_kbd_command(0xb8);
 	send_kbd_data(index);
 	send_kbd_command(0xbd);
@@ -201,7 +201,7 @@
 
 static void m3885_set_proc_ram(u8 index, u8 data)
 {
-	printk_spew("m3885: set procram %02x = %02x\n", index, data);
+	printk(BIOS_SPEW, "m3885: set procram %02x = %02x\n", index, data);
 	send_kbd_command(0xb8);
 	send_kbd_data(index);
 	send_kbd_command(0xbb);
@@ -217,7 +217,7 @@
 	send_kbd_command(0xba);
 	// send_kbd_command(0xff);
 	ret = recv_kbd_data();
-	printk_spew("m3885: get procram %02x = %02x\n", index, ret);
+	printk(BIOS_SPEW, "m3885: get procram %02x = %02x\n", index, ret);
 	return ret;
 }
 
@@ -255,25 +255,25 @@
 
 	/* Get the number of variables */
 	maxvars = m3885_get_variable(0x00);
-	printk_debug("M388x has %d variables in bank 2.\n", maxvars);
+	printk(BIOS_DEBUG, "M388x has %d variables in bank 2.\n", maxvars);
 	if (maxvars >= 35) {
 		offs = m3885_get_variable(0x23);
 		if ((offs > 0xc0) || (offs < 0x80)) {
-			printk_debug("M388x does not have a valid ram offset (0x%x)\n", offs);
+			printk(BIOS_DEBUG, "M388x does not have a valid ram offset (0x%x)\n", offs);
 		} else {
-			printk_debug("Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
+			printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
 			for (i=0; i < ARRAY_SIZE(function_ram); i++) {
 				m3885_set_proc_ram(i + offs, function_ram[i]);
 			}
 		}
 	} else {
-		printk_debug("Could not load Function-RAM (%d).\n", maxvars);
+		printk(BIOS_DEBUG, "Could not load Function-RAM (%d).\n", maxvars);
 	}
 
 	// restore original bank
 	m3885_set_variable(0x0c, kstate5_flags);
 	maxvars = m3885_get_variable(0x00);
-	printk_debug("M388x has %d variables in original bank.\n", maxvars);
+	printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars);
 	for (i=0; i<ARRAY_SIZE(variables); i+=3) {
 		u8 reg8;
 		if(variables[i + 0] > maxvars)
@@ -402,10 +402,10 @@
 	timeout = 0xf;
 	while (ec_read(M3885_CMCMD) && --timeout) {
 		udelay(10);
-		printk_debug(".");
+		printk(BIOS_DEBUG, ".");
 	}
 	if (!timeout) {
-		printk_debug("\nTimeout while waiting for M3885 command!\n");
+		printk(BIOS_DEBUG, "\nTimeout while waiting for M3885 command!\n");
 	}
 
 	/* If it was a read function: Pin state */
Index: src/mainboard/roda/rk886ex/mptable.c
===================================================================
--- src/mainboard/roda/rk886ex/mptable.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/mptable.c	(working copy)
@@ -118,7 +118,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 
-	printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
 
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/roda/rk886ex/ec.c
===================================================================
--- src/mainboard/roda/rk886ex/ec.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/ec.c	(working copy)
@@ -32,10 +32,10 @@
 	while ((inb(EC_SC) & EC_IBF) && --timeout) {
 		udelay(10);
 		if ((timeout & 0xff) == 0)
-			printk_spew(".");
+			printk(BIOS_SPEW, ".");
 	}
 	if (!timeout) {
-		printk_debug("Timeout while sending command 0x%02x to EC!\n", 
+		printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", 
 				command);
 		// return -1;
 	}
@@ -52,10 +52,10 @@
 	while ((inb(EC_SC) & EC_IBF) && --timeout) { // wait for IBF = 0
 		udelay(10);
 		if ((timeout & 0xff) == 0)
-			printk_spew(".");
+			printk(BIOS_SPEW, ".");
 	}
 	if (!timeout) {
-		printk_debug("Timeout while sending data 0x%02x to EC!\n",
+		printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n",
 				data);
 		// return -1;
 	}
@@ -84,15 +84,15 @@
 		}
 		udelay(10);
 		if ((timeout & 0xff) == 0)
-			printk_spew(".");
+			printk(BIOS_SPEW, ".");
 	}
 	if (!timeout) {
-		printk_debug("\nTimeout while receiving data from EC!\n");
+		printk(BIOS_DEBUG, "\nTimeout while receiving data from EC!\n");
 		// return -1;
 	}
 
 	data = inb(EC_DATA);
-	printk_debug("recv_ec_data: 0x%02x\n", data);
+	printk(BIOS_DEBUG, "recv_ec_data: 0x%02x\n", data);
 
 	return data;
 }
Index: src/mainboard/roda/rk886ex/rtl8168.c
===================================================================
--- src/mainboard/roda/rk886ex/rtl8168.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/rtl8168.c	(working copy)
@@ -27,7 +27,7 @@
 
 static void nic_init(struct device *dev)
 {
-	printk_debug("Initializing RTL8168 Gigabit Ethernet\n");
+	printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
 	// Nothing to do yet, but this has to be here to keep 
 	// coreboot from trying to execute an option ROM.
 }
Index: src/mainboard/roda/rk886ex/mainboard.c
===================================================================
--- src/mainboard/roda/rk886ex/mainboard.c	(revision 5263)
+++ src/mainboard/roda/rk886ex/mainboard.c	(working copy)
@@ -48,7 +48,7 @@
 		m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56);
 	}
 #endif
-	printk_debug("Display I/O: 0x%02x\n", inb(0x60f));
+	printk(BIOS_DEBUG, "Display I/O: 0x%02x\n", inb(0x60f));
 }
 
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -65,7 +65,7 @@
 #define BOOT_DISPLAY_EFP2	(1 << 6)
 #define BOOT_DISPLAY_LCD2	(1 << 7)
 
-	printk_debug("%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
 			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
 
 	switch (M.x86.R_AX) {
@@ -103,13 +103,13 @@
 {
 	int i;
 
-	printk_debug("SuperIO runtime register block:\n");
+	printk(BIOS_DEBUG, "SuperIO runtime register block:\n");
 	for (i=0; i<0x10; i++)
-		printk_debug("%02x ", i);
-	printk_debug("\n");
+		printk(BIOS_DEBUG, "%02x ", i);
+	printk(BIOS_DEBUG, "\n");
 	for (i=0; i<0x10; i++)
-		printk_debug("%02x ", inb(0x600 +i));
-	printk_debug("\n");
+		printk(BIOS_DEBUG, "%02x ", inb(0x600 +i));
+	printk(BIOS_DEBUG, "\n");
 }
 #endif
 
Index: src/mainboard/msi/ms7135/mptable.c
===================================================================
--- src/mainboard/msi/ms7135/mptable.c	(revision 5263)
+++ src/mainboard/msi/ms7135/mptable.c	(working copy)
@@ -212,7 +212,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/msi/ms7135/irq_tables.c
===================================================================
--- src/mainboard/msi/ms7135/irq_tables.c	(revision 5263)
+++ src/mainboard/msi/ms7135/irq_tables.c	(working copy)
@@ -91,7 +91,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *) (addr);
@@ -200,7 +200,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 #if 0
 	unsigned char irq[4];
Index: src/mainboard/msi/ms7135/get_bus_conf.c
===================================================================
--- src/mainboard/msi/ms7135/get_bus_conf.c	(revision 5263)
+++ src/mainboard/msi/ms7135/get_bus_conf.c	(working copy)
@@ -111,8 +111,8 @@
 			for (j = bus_ck804[i]; j < bus_isa; j++)
 				bus_type[j] = 1;
 		} else {
-			printk_debug
-			    ("ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+			printk
+			    (BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
 			     bus_ck804[0], sbdn + dn);
 			bus_isa = bus_ck804[i - 1] + 1;
 		}
Index: src/mainboard/msi/ms9282/mptable.c
===================================================================
--- src/mainboard/msi/ms9282/mptable.c	(revision 5263)
+++ src/mainboard/msi/ms9282/mptable.c	(working copy)
@@ -160,7 +160,7 @@
        /* Compute the checksums */
        mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
        mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk_debug("Wrote the mp table end at: %p - %p\n",
+       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
                mc, smp_next_mpe_entry(mc));
        return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/msi/ms9282/irq_tables.c
===================================================================
--- src/mainboard/msi/ms9282/irq_tables.c	(revision 5263)
+++ src/mainboard/msi/ms9282/irq_tables.c	(working copy)
@@ -79,7 +79,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
        pirq = (void *)(addr);
        v = (uint8_t *)(addr);
@@ -125,7 +125,7 @@
                 pirq->checksum = sum;
         }
 
-       printk_info("done.\n");
+       printk(BIOS_INFO, "done.\n");
 
        return  (unsigned long) pirq_info;
 
Index: src/mainboard/msi/ms9282/get_bus_conf.c
===================================================================
--- src/mainboard/msi/ms9282/get_bus_conf.c	(revision 5263)
+++ src/mainboard/msi/ms9282/get_bus_conf.c	(working copy)
@@ -131,7 +131,7 @@
                         m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
                 }
 
                for(i=2; i<8;i++) {
@@ -140,7 +140,7 @@
                                m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
                        }
                        else {
-                               printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+                               printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
                        }
                }
 
@@ -153,7 +153,7 @@
                        m->bus_type[j] = 1;
                if(m->bus_isa <= busn_max)
                        m->bus_isa = busn_max + 1;
-               printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+               printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
        }
 
 
Index: src/mainboard/msi/ms9185/mptable.c
===================================================================
--- src/mainboard/msi/ms9185/mptable.c	(revision 5263)
+++ src/mainboard/msi/ms9185/mptable.c	(working copy)
@@ -192,7 +192,7 @@
        /* Compute the checksums */
        mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
        mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk_debug("Wrote the mp table end at: %p - %p\n",
+       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
                mc, smp_next_mpe_entry(mc));
        return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/msi/ms9185/irq_tables.c
===================================================================
--- src/mainboard/msi/ms9185/irq_tables.c	(revision 5263)
+++ src/mainboard/msi/ms9185/irq_tables.c	(working copy)
@@ -82,7 +82,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
        pirq = (void *)(addr);
        v = (uint8_t *)(addr);
@@ -119,7 +119,7 @@
                 pirq->checksum = sum;
         }
 
-       printk_info("done.\n");
+       printk(BIOS_INFO, "done.\n");
 
        return  (unsigned long) pirq_info;
 
Index: src/mainboard/msi/ms9185/get_bus_conf.c
===================================================================
--- src/mainboard/msi/ms9185/get_bus_conf.c	(revision 5263)
+++ src/mainboard/msi/ms9185/get_bus_conf.c	(working copy)
@@ -108,12 +108,12 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                        m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                        m->bus_isa++;
-                       printk_debug("bus_isa=%d\n",m->bus_isa);
+                       printk(BIOS_DEBUG, "bus_isa=%d\n",m->bus_isa);
 #endif
                }
         }
        else {
-                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
+                printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
         }
 
                /* bcm5780 */
@@ -124,12 +124,12 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                         m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                         m->bus_isa++;
-                      printk_debug("bus_isa=%d\n",m->bus_isa);
+                      printk(BIOS_DEBUG, "bus_isa=%d\n",m->bus_isa);
 #endif
 
                }
                else {
-                       printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
+                       printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
                }
        }
 
Index: src/mainboard/msi/ms9652_fam10/romstage.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/romstage.c	(revision 5263)
+++ src/mainboard/msi/ms9652_fam10/romstage.c	(working copy)
@@ -200,7 +200,7 @@
 	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
@@ -211,10 +211,10 @@
 #endif
 
 	val = cpuid_eax(1);
-	printk_debug("BSP Family_Model: %08x\n", val);
-	printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
-	printk_debug("bsp_apicid = %02x\n", bsp_apicid);
-	printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+	printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08x\n", cpu_init_detectedx);
 
 	/* Setup sysinfo defaults */
 	set_sysinfo_in_ram(0);
@@ -230,12 +230,12 @@
 
 	/* Setup nodes PCI space and start core 0 AP init. */
 	finalize_node_setup(sysinfo);
-	printk_debug("finalize_node_setup done\n");
+	printk(BIOS_DEBUG, "finalize_node_setup done\n");
 
 	/* Setup any mainboard PCI settings etc. */
-	printk_debug("setup_mb_resource_map begin\n");
+	printk(BIOS_DEBUG, "setup_mb_resource_map begin\n");
 	setup_mb_resource_map();
-	printk_debug("setup_mb_resource_map end\n");
+	printk(BIOS_DEBUG, "setup_mb_resource_map end\n");
 	post_code(0x36);
 
 	/* wait for all the APs core0 started by finalize_node_setup. */
@@ -248,10 +248,10 @@
 
 #if CONFIG_LOGICAL_CPUS==1
 	/* Core0 on each node is configured. Now setup any additional cores. */
-	printk_debug("start_other_cores()\n");
+	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
 	post_code(0x37);
-	printk_debug("wait_all_other_cores_started()\n");
+	printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
 	wait_all_other_cores_started(bsp_apicid);
 #endif
 
@@ -259,7 +259,7 @@
 
 #if FAM10_SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
-	printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
 	/* FIXME: The sb fid change may survive the warm reset and only
 	 * need to be done once.*/
@@ -277,7 +277,7 @@
 
 	/* show final fid and vid */
 	msr=rdmsr(0xc0010071);
-	printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
 	wants_reset = mcp55_early_setup_x();
@@ -290,27 +290,27 @@
 	}
 
 	if (wants_reset)
-		printk_debug("mcp55_early_setup_x wanted additional reset!\n");
+		printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 
 	post_code(0x3B);
 
 	/* It's the time to set ctrl in sysinfo now; */
-	printk_debug("fill_mem_ctrl()\n");
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	post_code(0x3D);
 
-	printk_debug("enable_smbus()\n");
+	printk(BIOS_DEBUG, "enable_smbus()\n");
 	enable_smbus();
 	post_code(0x3E);
 
 	memreset_setup();
 	post_code(0x40);
 
-	printk_debug("raminit_amdmct()\n");
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
 	post_code(0x41);
 
-	printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
Index: src/mainboard/msi/ms9652_fam10/mptable.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/mptable.c	(revision 5263)
+++ src/mainboard/msi/ms9652_fam10/mptable.c	(working copy)
@@ -149,7 +149,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/msi/ms9652_fam10/irq_tables.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/irq_tables.c	(revision 5263)
+++ src/mainboard/msi/ms9652_fam10/irq_tables.c	(working copy)
@@ -76,7 +76,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -131,7 +131,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/msi/ms9652_fam10/acpi_tables.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/acpi_tables.c	(revision 5263)
+++ src/mainboard/msi/ms9652_fam10/acpi_tables.c	(working copy)
@@ -123,7 +123,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
@@ -138,7 +138,7 @@
 	acpi_write_rsdt(rsdt);
 
 	/* We explicitly add these tables later on: */
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 
 	/* we should align FACS to 64B as per ACPI specs */
 	current = ALIGN(current, 64);
@@ -152,9 +152,9 @@
 	       ((acpi_header_t *) AmlCode)->length);
 	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
@@ -162,46 +162,46 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET timers Linux wants an MADT. */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current+=slit->header.length;
 	acpi_add_table(rsdp, slit);
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/msi/ms9652_fam10/get_bus_conf.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/get_bus_conf.c	(revision 5263)
+++ src/mainboard/msi/ms9652_fam10/get_bus_conf.c	(working copy)
@@ -74,7 +74,7 @@
 	device_t dev;
 	int i, j;
 
-	printk_spew("get_bus_conf()\n");
+	printk(BIOS_SPEW, "get_bus_conf()\n");
 
 	if(get_bus_conf_done==1) return; //do it only once
 
@@ -103,7 +103,7 @@
 			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
 		}
 
 		for(i=2; i<8;i++) {
@@ -112,7 +112,7 @@
 				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			}
 			else {
-				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
 			}
 		}
 
@@ -125,16 +125,16 @@
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max)
 			m->bus_isa = busn_max + 1;
-		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+		printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
 	}
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
-	printk_spew("CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n");
+	printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n");
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-	printk_spew("CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n");
+	printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n");
 #endif
 	m->apicid_mcp55 = apicid_base+0;
 }
Index: src/mainboard/msi/ms7260/mptable.c
===================================================================
--- src/mainboard/msi/ms7260/mptable.c	(revision 5263)
+++ src/mainboard/msi/ms7260/mptable.c	(working copy)
@@ -139,7 +139,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/msi/ms7260/irq_tables.c
===================================================================
--- src/mainboard/msi/ms7260/irq_tables.c	(revision 5263)
+++ src/mainboard/msi/ms7260/irq_tables.c	(working copy)
@@ -71,7 +71,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 and 0x100000. */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -106,7 +106,7 @@
 	if (sum != pirq->checksum)
 		pirq->checksum = sum;
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/msi/ms7260/get_bus_conf.c
===================================================================
--- src/mainboard/msi/ms7260/get_bus_conf.c	(revision 5263)
+++ src/mainboard/msi/ms7260/get_bus_conf.c	(working copy)
@@ -114,8 +114,8 @@
 		for (j = bus_mcp55[1]; j < bus_mcp55[2]; j++)
 			bus_type[j] = 1;
 	} else {
-		printk_debug
-		    ("ERROR - could not find PCI 1:%02x.0, using defaults\n",
+		printk
+		    (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
 		     sbdn + 0x06);
 
 		bus_mcp55[1] = 2;
@@ -132,8 +132,8 @@
 			for (j = bus_mcp55[i]; j < bus_isa; j++)
 				bus_type[j] = 1;
 		} else {
-			printk_debug
-			    ("ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+			printk
+			    (BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
 			     bus_mcp55[0], sbdn + 0x0a + i - 2);
 			bus_isa = bus_mcp55[i - 1] + 1;
 		}
Index: src/mainboard/arima/hdama/mptable.c
===================================================================
--- src/mainboard/arima/hdama/mptable.c	(revision 5263)
+++ src/mainboard/arima/hdama/mptable.c	(working copy)
@@ -80,7 +80,7 @@
 		dst_link = (config_map >> 8) & 3;
 		bus_base = (config_map >> 16) & 0xff;
 #if 0				
-		printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+		printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
 			dst_node, dst_link, bus_base,
 			reg, config_map);
 #endif
@@ -153,7 +153,7 @@
 		/* HT chain 0 */
 		bus_chain_0 = node_link_to_bus(0, 0);
 		if (bus_chain_0 == 0xff) {
-			printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
 			bus_chain_0 = 0;
 		}
 
@@ -165,7 +165,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
 
 			bus_8111_1 = 4;
 			bus_isa = 5;
@@ -177,7 +177,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
 
 			bus_8131_1 = 2;
 		}
@@ -188,7 +188,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
+			printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
 
 			bus_8131_2 = 3;
 		}
@@ -313,7 +313,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
@@ -329,26 +329,26 @@
 	unsigned bus_chain_0 = node_link_to_bus(0, 0);
 
 	reset = 0;
-	printk_debug("Looking for bad PCIX MHz input\n");
+	printk(BIOS_DEBUG, "Looking for bad PCIX MHz input\n");
 	dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
 	if (!dev)
-		printk_debug("Couldn't find %02x:02.0 \n", bus_chain_0);
+		printk(BIOS_DEBUG, "Couldn't find %02x:02.0 \n", bus_chain_0);
 	else {
 		data = pci_read_config32(dev, 0xa0);
 		if(!(((data>>16)&0x03)==0x03)) {
 			reset=1;
-			printk_debug("Bad PCIX MHz - Reset\n");
+			printk(BIOS_DEBUG, "Bad PCIX MHz - Reset\n");
 		}
 	}
-	printk_debug("Looking for bad Hot Swap Enable\n");
+	printk(BIOS_DEBUG, "Looking for bad Hot Swap Enable\n");
 	dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
 	if (!dev)
-		printk_debug("Couldn't find %02x:01.0 \n", bus_chain_0);
+		printk(BIOS_DEBUG, "Couldn't find %02x:01.0 \n", bus_chain_0);
 	else {
 		data = pci_read_config32(dev, 0x48);
 		if(data & 0x0c) {
 			reset=1;
-			printk_debug("Bad Hot Swap start - Reset\n");
+			printk(BIOS_DEBUG, "Bad Hot Swap start - Reset\n");
 		}
 	}
 	if(reset) {
@@ -363,7 +363,7 @@
 		outb(0x0e, 0x0cf9);
 	}
 	else {
-		printk_debug("OK 133MHz & Hot Swap is off\n");
+		printk(BIOS_DEBUG, "OK 133MHz & Hot Swap is off\n");
 	}
 }
 
Index: src/mainboard/sunw/ultra40/mptable.c
===================================================================
--- src/mainboard/sunw/ultra40/mptable.c	(revision 5263)
+++ src/mainboard/sunw/ultra40/mptable.c	(working copy)
@@ -226,7 +226,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/sunw/ultra40/irq_tables.c
===================================================================
--- src/mainboard/sunw/ultra40/irq_tables.c	(revision 5263)
+++ src/mainboard/sunw/ultra40/irq_tables.c	(working copy)
@@ -71,7 +71,7 @@
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -173,7 +173,7 @@
                 pirq->checksum = sum;
         }
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/sunw/ultra40/get_bus_conf.c
===================================================================
--- src/mainboard/sunw/ultra40/get_bus_conf.c	(revision 5263)
+++ src/mainboard/sunw/ultra40/get_bus_conf.c	(working copy)
@@ -102,7 +102,7 @@
 #endif
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
 
                         bus_ck804_1 = 2;
 #if 0
@@ -120,7 +120,7 @@
                         bus_ck804_3++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
 
                         bus_ck804_3 = bus_ck804_2+1;
                 }
@@ -132,7 +132,7 @@
                         bus_ck804_4++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
 
                         bus_ck804_4 = bus_ck804_3+1;
                 }
@@ -145,7 +145,7 @@
                         bus_ck804_5++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
 
                         bus_ck804_5 = bus_ck804_4+1;
                 }
@@ -156,7 +156,7 @@
                         bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
                 }
 
 		bus_8131_0 = (pci1234[1] >> 16) & 0xff;
@@ -168,7 +168,7 @@
                         bus_8131_2++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
 
                         bus_8131_1 = bus_8131_0+1;
                         bus_8131_2 = bus_8131_0+2;
@@ -181,7 +181,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
 
                         bus_8131_2 = bus_8131_1+1;
                 }
@@ -198,7 +198,7 @@
                         bus_ck804b_2++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
 
                         bus_ck804b_1 = bus_ck804b_0+1;
                         bus_ck804b_2 = bus_ck804b_0+2;
@@ -211,7 +211,7 @@
                         bus_ck804b_3++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
 
                         bus_ck804b_2 = bus_ck804b_0+1;
                         bus_ck804b_3 = bus_ck804b_0+2;
@@ -224,7 +224,7 @@
                         bus_ck804b_4++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
 
                         bus_ck804b_4 = bus_ck804b_3+1;
                 }
@@ -235,7 +235,7 @@
                         bus_ck804b_5++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
 
                         bus_ck804b_5 = bus_ck804b_4+1;
                 }
@@ -248,7 +248,7 @@
                         bus_isa++;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
+                        printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
 #if 1
                         bus_ck804b_5 = bus_ck804b_4+1;
 #endif
Index: src/mainboard/newisys/khepri/mptable.c
===================================================================
--- src/mainboard/newisys/khepri/mptable.c	(revision 5263)
+++ src/mainboard/newisys/khepri/mptable.c	(working copy)
@@ -46,7 +46,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 
 			bus_8111_1 = 4;
 			bus_isa = 5;
@@ -58,7 +58,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 
 			bus_8131_1 = 2;
 		}
@@ -69,7 +69,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_8131_2 = 3;
 		}
@@ -219,7 +219,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/technexion/tim8690/fadt.c
===================================================================
--- src/mainboard/technexion/tim8690/fadt.c	(revision 5263)
+++ src/mainboard/technexion/tim8690/fadt.c	(working copy)
@@ -46,7 +46,7 @@
 	acpi_header_t *header = &(fadt->header);
 
 	pm_base &= 0xFFFF;
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/mainboard/technexion/tim8690/romstage.c
===================================================================
--- src/mainboard/technexion/tim8690/romstage.c	(revision 5263)
+++ src/mainboard/technexion/tim8690/romstage.c	(working copy)
@@ -136,7 +136,7 @@
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
-	printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 
 	setup_tim8690_resource_map();
 
@@ -162,7 +162,7 @@
 
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
-		printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
 		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -170,16 +170,16 @@
 
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
-		printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 	} else {
-		printk_debug("Changing FIDVID not supported\n");
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs690_htinit();
-	printk_debug("needs_reset=0x%x\n", needs_reset);
+	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 
 	if (needs_reset) {
@@ -190,7 +190,7 @@
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now; */
-	printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
+	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
Index: src/mainboard/technexion/tim8690/mptable.c
===================================================================
--- src/mainboard/technexion/tim8690/mptable.c	(revision 5263)
+++ src/mainboard/technexion/tim8690/mptable.c	(working copy)
@@ -199,7 +199,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/technexion/tim8690/irq_tables.c
===================================================================
--- src/mainboard/technexion/tim8690/irq_tables.c	(revision 5263)
+++ src/mainboard/technexion/tim8690/irq_tables.c	(working copy)
@@ -73,7 +73,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *) (addr);
@@ -113,7 +113,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/technexion/tim8690/acpi_tables.c
===================================================================
--- src/mainboard/technexion/tim8690/acpi_tables.c	(revision 5263)
+++ src/mainboard/technexion/tim8690/acpi_tables.c	(working copy)
@@ -49,9 +49,9 @@
 	print_debug("dump_mem:");
 	for (i = start; i < end; i++) {
 		if ((i & 0xf) == 0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
@@ -147,7 +147,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -165,13 +165,13 @@
 	 * We explicitly add these tables later on:
 	 */
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -179,14 +179,14 @@
 
 #if 0
 	/* SRAT */
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current += slit->header.length;
@@ -194,7 +194,7 @@
 #endif
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -214,7 +214,7 @@
 		} else {
 			c = (uint8_t) ('A' + i - 1 - 6);
 		}
-		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
 		current = (current + 0x07) & -0x08;
 		ssdtx = (acpi_header_t *) current;
 		switch (sysconf.hcid[i]) {
@@ -243,20 +243,20 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *) current;
 	memcpy((void *)dsdt, (void *)AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
 	current += dsdt->length;
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 	/* FADT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -264,28 +264,28 @@
 	acpi_add_table(rsdp, fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/technexion/tim8690/mainboard.c
===================================================================
--- src/mainboard/technexion/tim8690/mainboard.c	(revision 5263)
+++ src/mainboard/technexion/tim8690/mainboard.c	(working copy)
@@ -60,7 +60,7 @@
 	u8 byte;
 	device_t sm_dev;
 
-	printk_info("enable_onboard_nic.\n");
+	printk(BIOS_INFO, "enable_onboard_nic.\n");
 
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
@@ -97,7 +97,7 @@
 
 	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
 	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
-	printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
+	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
 
 	/* sb600 settings for thermal config */
 	/* set SB600 GPIO 64 to GPIO with pull-up */
@@ -150,19 +150,19 @@
 	struct mainboard_config *mainboard =
 	    (struct mainboard_config *)dev->chip_info;
 
-	printk_info("Mainboard tim8690 Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
 		    __func__, msr2.lo, msr2.hi);
 
 	switch (msr.lo) {
@@ -184,7 +184,7 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
@@ -203,7 +203,7 @@
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
-	printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
+	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
Index: src/mainboard/technexion/tim5690/acpi_tables.c
===================================================================
--- src/mainboard/technexion/tim5690/acpi_tables.c	(revision 5263)
+++ src/mainboard/technexion/tim5690/acpi_tables.c	(working copy)
@@ -49,9 +49,9 @@
 	print_debug("dump_mem:");
 	for (i = start; i < end; i++) {
 		if ((i & 0xf) == 0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
@@ -147,7 +147,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -165,13 +165,13 @@
 	 * We explicitly add these tables later on:
 	 */
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -179,14 +179,14 @@
 
 #if 0
 	/* SRAT */
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-	printk_debug("ACPI:    * SLIT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
 	slit = (acpi_slit_t *) current;
 	acpi_create_slit(slit);
 	current += slit->header.length;
@@ -194,7 +194,7 @@
 #endif
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
@@ -214,7 +214,7 @@
 		} else {
 			c = (uint8_t) ('A' + i - 1 - 6);
 		}
-		printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
 		current = (current + 0x07) & -0x08;
 		ssdtx = (acpi_header_t *) current;
 		switch (sysconf.hcid[i]) {
@@ -243,20 +243,20 @@
 #endif
 
 	/* FACS */
-	printk_debug("ACPI:    * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* DSDT */
-	printk_debug("ACPI:    * DSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *) current;
 	memcpy((void *)dsdt, (void *)AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
 	current += dsdt->length;
-	printk_debug("ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 	/* FADT */
-	printk_debug("ACPI:    * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -264,28 +264,28 @@
 	acpi_add_table(rsdp, fadt);
 
 #if DUMP_ACPI_TABLES == 1
-	printk_debug("rsdp\n");
+	printk(BIOS_DEBUG, "rsdp\n");
 	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-	printk_debug("rsdt\n");
+	printk(BIOS_DEBUG, "rsdt\n");
 	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-	printk_debug("madt\n");
+	printk(BIOS_DEBUG, "madt\n");
 	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-	printk_debug("srat\n");
+	printk(BIOS_DEBUG, "srat\n");
 	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-	printk_debug("slit\n");
+	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-	printk_debug("ssdt\n");
+	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-	printk_debug("fadt\n");
+	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/technexion/tim5690/fadt.c
===================================================================
--- src/mainboard/technexion/tim5690/fadt.c	(revision 5263)
+++ src/mainboard/technexion/tim5690/fadt.c	(working copy)
@@ -46,7 +46,7 @@
 	acpi_header_t *header = &(fadt->header);
 
 	pm_base &= 0xFFFF;
-	printk_debug("pm_base: 0x%04x\n", pm_base);
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
 
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
Index: src/mainboard/technexion/tim5690/romstage.c
===================================================================
--- src/mainboard/technexion/tim5690/romstage.c	(revision 5263)
+++ src/mainboard/technexion/tim5690/romstage.c	(working copy)
@@ -141,7 +141,7 @@
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
-	printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 
 	setup_tim5690_resource_map();
 
@@ -167,7 +167,7 @@
 
 		/* Read FIDVID_STATUS */
 		msr=rdmsr(0xc0010042);
-		printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
 		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -175,16 +175,16 @@
 
 		/* show final fid and vid */
 		msr=rdmsr(0xc0010042);
-		printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 	} else {
-		printk_debug("Changing FIDVID not supported\n");
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 	}
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs690_htinit();
-	printk_debug("needs_reset=0x%x\n", needs_reset);
+	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
 
 	if (needs_reset) {
@@ -198,7 +198,7 @@
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now; */
-	printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
+	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
Index: src/mainboard/technexion/tim5690/mptable.c
===================================================================
--- src/mainboard/technexion/tim5690/mptable.c	(revision 5263)
+++ src/mainboard/technexion/tim5690/mptable.c	(working copy)
@@ -199,7 +199,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/technexion/tim5690/irq_tables.c
===================================================================
--- src/mainboard/technexion/tim5690/irq_tables.c	(revision 5263)
+++ src/mainboard/technexion/tim5690/irq_tables.c	(working copy)
@@ -73,7 +73,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (u8 *) (addr);
@@ -113,7 +113,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/technexion/tim5690/mainboard.c
===================================================================
--- src/mainboard/technexion/tim5690/mainboard.c	(revision 5263)
+++ src/mainboard/technexion/tim5690/mainboard.c	(working copy)
@@ -146,7 +146,7 @@
 
 	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
 	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
-	printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
+	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
 
 	/* sb600 settings for thermal config */
 	/* set SB600 GPIO 64 to GPIO with pull-up */
@@ -245,7 +245,7 @@
 	u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
 	u8 port2;
 
-	printk_info("Mainboard tim5690 Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev);
 
 	mb_gpio_init(&gpio_base);
 
@@ -261,12 +261,12 @@
 
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
-	printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
 		    __func__, msr2.lo, msr2.hi);
 
 	switch (msr.lo) {
@@ -288,7 +288,7 @@
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
@@ -306,7 +306,7 @@
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
 #if (CONFIG_GFXUMA == 1)
-	printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
+	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
Index: src/mainboard/winent/pl6064/mainboard.c
===================================================================
--- src/mainboard/winent/pl6064/mainboard.c	(revision 5263)
+++ src/mainboard/winent/pl6064/mainboard.c	(working copy)
@@ -23,8 +23,8 @@
 
 static void init(struct device *dev)
 {
-	printk_debug("Win Enterprises PL-6064/65 ENTER %s\n", __func__);
-	printk_debug("Win Enterprises PL-6064/65 EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
Index: src/mainboard/ibm/e326/mptable.c
===================================================================
--- src/mainboard/ibm/e326/mptable.c	(revision 5263)
+++ src/mainboard/ibm/e326/mptable.c	(working copy)
@@ -48,7 +48,7 @@
 			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			bus_isa++;
 		} else {
-			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 			bus_8111_1 = 4;
 			bus_isa = 5;
 		}
@@ -59,7 +59,7 @@
 			bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
 		} else {
-			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 			bus_8131_1 = 2;
 		}
 
@@ -68,7 +68,7 @@
 		if (dev) {
 			bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		} else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 			bus_8131_2 = 3;
 		}
 	}
@@ -161,7 +161,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/ibm/e325/mptable.c
===================================================================
--- src/mainboard/ibm/e325/mptable.c	(revision 5263)
+++ src/mainboard/ibm/e325/mptable.c	(working copy)
@@ -48,7 +48,7 @@
 			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			bus_isa++;
 		} else {
-			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
 			bus_8111_1 = 4;
 			bus_isa = 5;
 		}
@@ -59,7 +59,7 @@
 			bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
 		} else {
-			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
 			bus_8131_1 = 2;
 		}
 
@@ -68,7 +68,7 @@
 		if (dev) {
 			bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		} else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 			bus_8131_2 = 3;
 		}
 	}
@@ -161,7 +161,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/nvidia/l1_2pvv/mptable.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/mptable.c	(revision 5263)
+++ src/mainboard/nvidia/l1_2pvv/mptable.c	(working copy)
@@ -207,7 +207,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/nvidia/l1_2pvv/irq_tables.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/irq_tables.c	(revision 5263)
+++ src/mainboard/nvidia/l1_2pvv/irq_tables.c	(working copy)
@@ -76,7 +76,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -122,7 +122,7 @@
 		pirq->checksum = sum;
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return	(unsigned long) pirq_info;
 
Index: src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	(revision 5263)
+++ src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	(working copy)
@@ -137,7 +137,7 @@
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max)
 			m->bus_isa = busn_max + 1;
-		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn_min, busn_max, m->bus_isa);
+		printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn_min, busn_max, m->bus_isa);
 	}
 
 		/* MCP55b */
Index: src/mainboard/intel/xe7501devkit/mptable.c
===================================================================
--- src/mainboard/intel/xe7501devkit/mptable.c	(revision 5263)
+++ src/mainboard/intel/xe7501devkit/mptable.c	(working copy)
@@ -167,7 +167,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
 
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/intel/xe7501devkit/acpi_tables.c
===================================================================
--- src/mainboard/intel/xe7501devkit/acpi_tables.c	(revision 5263)
+++ src/mainboard/intel/xe7501devkit/acpi_tables.c	(working copy)
@@ -105,7 +105,7 @@
 	start   = ( start + 0x0f ) & -0x10;
 	current = start;
 	
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -123,14 +123,14 @@
 	 * We explicitly add these tables later on:
 	 */
 	/* QNX wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current+=madt->header.length;
 	acpi_add_table(rsdp,madt);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
 
Index: src/mainboard/intel/d945gclf/mainboard_smi.c
===================================================================
--- src/mainboard/intel/d945gclf/mainboard_smi.c	(revision 5263)
+++ src/mainboard/intel/d945gclf/mainboard_smi.c	(working copy)
@@ -31,7 +31,7 @@
 {
 	switch (smif) {
 	case 0x99:
-		printk_debug("Sample\n");
+		printk(BIOS_DEBUG, "Sample\n");
 		gnvs->smif = 0;
 		break;
 	default:
Index: src/mainboard/intel/d945gclf/acpi_tables.c
===================================================================
--- src/mainboard/intel/d945gclf/acpi_tables.c	(revision 5263)
+++ src/mainboard/intel/d945gclf/acpi_tables.c	(working copy)
@@ -221,7 +221,7 @@
 	/* Align ACPI tables to 16byte */
 	ALIGN_CURRENT;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -240,7 +240,7 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
@@ -249,7 +249,7 @@
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
@@ -257,7 +257,7 @@
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
@@ -265,7 +265,7 @@
 	acpi_add_table(rsdp, mcfg);
 
 #if OLD_ACPI
-	printk_debug("ACPI:    * OEMB\n");
+	printk(BIOS_DEBUG, "ACPI:    * OEMB\n");
 	oemb=(acpi_oemb_t *)current;
 	current += sizeof(acpi_oemb_t);
 	ALIGN_CURRENT;
@@ -273,7 +273,7 @@
 	acpi_add_table(rsdp, oemb);
 #endif
 
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	ALIGN_CURRENT;
@@ -287,7 +287,7 @@
 #if OLD_ACPI
 	for (i=0; i < dsdt->length; i++) {
 		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBEEF) {
-			printk_debug("ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb);
+			printk(BIOS_DEBUG, "ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb);
 			*(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb;
 			break;
 		}
@@ -299,7 +299,7 @@
 	/* Pack GNVS into the ACPI table area */
 	for (i=0; i < dsdt->length; i++) {
 		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
 			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
 			break;
 		}
@@ -320,18 +320,18 @@
 	dsdt->checksum = 0;
 	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
 
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
 
 #if CONFIG_HAVE_ACPI_SLIC
-	printk_debug("ACPI:     * SLIC\n");
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
 	slic = (acpi_header_t *)current;
 	current += acpi_create_slic(current);
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, slic);
 #endif
 
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 	ALIGN_CURRENT;
@@ -339,15 +339,15 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_debug("ACPI:     * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
-	printk_debug("current = %lx\n", current);
+	printk(BIOS_DEBUG, "current = %lx\n", current);
 
-	printk_debug("ACPI:     * DMI (Linux workaround)\n");
+	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
 	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
@@ -355,6 +355,6 @@
 	ALIGN_CURRENT;
 #endif
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/intel/d945gclf/romstage.c
===================================================================
--- src/mainboard/intel/d945gclf/romstage.c	(revision 5263)
+++ src/mainboard/intel/d945gclf/romstage.c	(working copy)
@@ -60,7 +60,7 @@
 static void setup_ich7_gpios(void)
 {
 	/* TODO: This is highly board specific and should be moved */
-	printk_debug(" GPIOS...");
+	printk(BIOS_DEBUG, " GPIOS...");
 	/* General Registers */
 	outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
 	outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
@@ -254,7 +254,7 @@
 	report_bist_failure(bist);
 
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk_debug("soft reset detected.\n");
+		printk(BIOS_DEBUG, "soft reset detected.\n");
 		boot_mode = 1;
 	}
 
@@ -265,17 +265,17 @@
 
         /* Read PM1_CNT */
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
-	printk_debug("PM1_CNT: %08x\n", reg32);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
 #if CONFIG_HAVE_ACPI_RESUME
-		printk_debug("Resume from S3 detected.\n");
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 		boot_mode = 2;
 		/* Clear SLP_TYPE. This will break stage2 but
 		 * we care for that when we get there.
 		 */
 		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 #else
-		printk_debug("Resume from S3 detected, but disabled.\n");
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 #endif
 	}
 
@@ -312,7 +312,7 @@
 		/* This will not work if TSEG is in place! */
 		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 
-		printk_debug("TOM: 0x%08x\n", tom);
+		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
 		//ram_check(0x00100000, tom);
 	}
Index: src/mainboard/intel/d945gclf/mptable.c
===================================================================
--- src/mainboard/intel/d945gclf/mptable.c	(revision 5263)
+++ src/mainboard/intel/d945gclf/mptable.c	(working copy)
@@ -122,7 +122,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 
-	printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
 
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/intel/d945gclf/rtl8168.c
===================================================================
--- src/mainboard/intel/d945gclf/rtl8168.c	(revision 5263)
+++ src/mainboard/intel/d945gclf/rtl8168.c	(working copy)
@@ -27,7 +27,7 @@
 
 static void nic_init(struct device *dev)
 {
-	printk_debug("Initializing RTL8168 Gigabit Ethernet\n");
+	printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
 	// Nothing to do yet, but this has to be here to keep 
 	// coreboot from trying to execute an option ROM.
 }
Index: src/mainboard/intel/truxton/mptable.c
===================================================================
--- src/mainboard/intel/truxton/mptable.c	(revision 5263)
+++ src/mainboard/intel/truxton/mptable.c	(working copy)
@@ -65,7 +65,7 @@
 		bus_isa++;
 	}
 	else {
-		printk_debug("ERROR - could not find PCI 0:04.0\n");
+		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
 		bus_aioc = 0;
 		bus_isa = 9;
 	}
@@ -75,7 +75,7 @@
 		bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	}
 	else {
-		printk_debug("ERROR - could not find PCI 0:02.0\n");
+		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
 		bus_pea0 = 0;
 	}
 	/* PCIe A1 */
@@ -84,7 +84,7 @@
 		bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	}
 	else {
-		printk_debug("ERROR - could not find PCI 0:03.0\n");
+		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
 		bus_pea1 = 0;
 	}
 
@@ -183,7 +183,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/intel/mtarvon/mptable.c
===================================================================
--- src/mainboard/intel/mtarvon/mptable.c	(revision 5263)
+++ src/mainboard/intel/mtarvon/mptable.c	(working copy)
@@ -150,7 +150,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/intel/eagleheights/mptable.c
===================================================================
--- src/mainboard/intel/eagleheights/mptable.c	(revision 5263)
+++ src/mainboard/intel/eagleheights/mptable.c	(working copy)
@@ -108,7 +108,7 @@
 	  bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 	  bus_isa++;
 	} else {
-	  printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+	  printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 	  bus_pci = 6;
 	  bus_isa = 7;
 	}
@@ -117,7 +117,7 @@
 	if(dev) {
 	  bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	} else {
-	  printk_debug("ERROR - could not find PCIe Port A  0:2.0, using defaults\n");
+	  printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A  0:2.0, using defaults\n");
 	  bus_pcie_a = 1;
 	}
 
@@ -125,7 +125,7 @@
 	if(dev) {
 	  bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	} else {
-	  printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+	  printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
 	  bus_pcie_a1 = 2;
 	}
 
@@ -133,7 +133,7 @@
 	if(dev) {
 	  bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	} else {
-	  printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+	  printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
 	  bus_pcie_b = 3;
 	}
 
@@ -310,7 +310,7 @@
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/intel/eagleheights/acpi_tables.c
===================================================================
--- src/mainboard/intel/eagleheights/acpi_tables.c	(revision 5263)
+++ src/mainboard/intel/eagleheights/acpi_tables.c	(working copy)
@@ -111,7 +111,7 @@
 		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 		bus_isa++;
 	} else {
-		printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 		bus_isa = 7;
 	}
 
@@ -156,7 +156,7 @@
 	/* Align ACPI tables to 16byte */
 	ALIGN_CURRENT;
 
-	printk_info("ACPI: Writing ACPI tables at %lx.\n", current);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", current);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
@@ -175,7 +175,7 @@
 	/*
 	 * We explicitly add these tables later on:
 	 */
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
@@ -184,7 +184,7 @@
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
@@ -192,14 +192,14 @@
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	ALIGN_CURRENT;
@@ -211,10 +211,10 @@
 	memcpy((void *) dsdt, (void *) AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
 
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
 
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 	ALIGN_CURRENT;
@@ -222,6 +222,6 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/intel/jarrell/mptable.c
===================================================================
--- src/mainboard/intel/jarrell/mptable.c	(revision 5263)
+++ src/mainboard/intel/jarrell/mptable.c	(working copy)
@@ -50,7 +50,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:1f.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
 
 			bus_ich5r_1 = 4;
 			bus_isa = 5;
@@ -62,7 +62,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
 
 			bus_pxhd_1 = 2;
 		}
@@ -73,7 +73,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_pxhd_2 = 3;
 		}
@@ -124,7 +124,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 		}
 		/* pxhd apic 4 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
@@ -135,7 +135,7 @@
 			}
 		}
 		else {
-			printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
+			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 		}
 		/* pxhd apic 5 */
 		if(bus_pxhd_3) { /* Active riser pxhd */
@@ -147,7 +147,7 @@
 				}
 			}
 			else {
-				printk_debug("ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
+				printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
 			}
 		}
 		/* pxhd apic 6 */
@@ -160,7 +160,7 @@
 				}
 			}
 			else {
-				printk_debug("ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
+				printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
 			}
 		}
 	}
@@ -279,7 +279,7 @@
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/asus/p2b-d/mptable.c
===================================================================
--- src/mainboard/asus/p2b-d/mptable.c	(revision 5263)
+++ src/mainboard/asus/p2b-d/mptable.c	(working copy)
@@ -144,7 +144,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/asus/a8v-e_se/acpi_tables.c
===================================================================
--- src/mainboard/asus/a8v-e_se/acpi_tables.c	(revision 5263)
+++ src/mainboard/asus/a8v-e_se/acpi_tables.c	(working copy)
@@ -97,7 +97,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
@@ -112,7 +112,7 @@
 	acpi_write_rsdt(rsdt);
 
 	/* We explicitly add these tables later on: */
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
@@ -123,9 +123,9 @@
 	       ((acpi_header_t *) AmlCode)->length);
 	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
@@ -134,23 +134,23 @@
 	acpi_add_table(rsdp, fadt);
 
 	/* If we want to use HPET timers Linux wants it in MADT. */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/mainboard/asus/p2b-ds/mptable.c
===================================================================
--- src/mainboard/asus/p2b-ds/mptable.c	(revision 5263)
+++ src/mainboard/asus/p2b-ds/mptable.c	(working copy)
@@ -146,7 +146,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/asus/a8n_e/mptable.c
===================================================================
--- src/mainboard/asus/a8n_e/mptable.c	(revision 5263)
+++ src/mainboard/asus/a8n_e/mptable.c	(working copy)
@@ -184,7 +184,7 @@
 	mc->mpe_checksum =
 	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
Index: src/mainboard/asus/a8n_e/irq_tables.c
===================================================================
--- src/mainboard/asus/a8n_e/irq_tables.c	(revision 5263)
+++ src/mainboard/asus/a8n_e/irq_tables.c	(working copy)
@@ -78,7 +78,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000. */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -191,7 +191,7 @@
 	if (sum != pirq->checksum)
 		pirq->checksum = sum;
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 
 	return (unsigned long)pirq_info;
 }
Index: src/mainboard/asus/a8n_e/get_bus_conf.c
===================================================================
--- src/mainboard/asus/a8n_e/get_bus_conf.c	(revision 5263)
+++ src/mainboard/asus/a8n_e/get_bus_conf.c	(working copy)
@@ -107,8 +107,8 @@
 		bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 		bus_ck804[2]++;
 	} else {
-		printk_debug
-		    ("ERROR - could not find PCI 1:%02x.0, using defaults\n",
+		printk
+		    (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
 		     sbdn + 0x09);
 		bus_ck804[1] = 2;
 		bus_ck804[2] = 3;
@@ -124,7 +124,7 @@
 			for (j = bus_ck804[i]; j < bus_isa; j++)
 				bus_type[j] = 1;
 		} else {
-			printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n",
+			printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
 			     bus_ck804[0], sbdn + 0x0b + i - 2);
 			bus_isa = bus_ck804[i - 1] + 1;
 		}
Index: src/mainboard/asus/m2v-mx_se/acpi_tables.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/acpi_tables.c	(revision 5263)
+++ src/mainboard/asus/m2v-mx_se/acpi_tables.c	(working copy)
@@ -108,7 +108,7 @@
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
-	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
@@ -123,7 +123,7 @@
 	acpi_write_rsdt(rsdt);
 
 	/* We explicitly add these tables later on: */
-	printk_debug("ACPI:     * FACS\n");
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
 
 	/* we should align FACS to 64B as per ACPI specs */
 
@@ -138,9 +138,9 @@
 	       ((acpi_header_t *) AmlCode)->length);
 	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
-	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
 		     dsdt->length);
-	printk_debug("ACPI:     * FADT\n");
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
@@ -148,46 +148,46 @@
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	printk_debug("ACPI:    * HPET\n");
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET timers Linux wants an MADT. */
-	printk_debug("ACPI:    * MADT\n");
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
-	printk_debug("ACPI:    * MCFG\n");
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
 	acpi_add_table(rsdp, mcfg);
 
-	printk_debug("ACPI:    * SRAT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
 	current += srat->header.length;
 	acpi_add_table(rsdp, srat);
 
 	/* SLIT */
-        printk_debug("ACPI:    * SLIT\n");
+        printk(BIOS_DEBUG, "ACPI:    * SLIT\n");
         slit = (acpi_slit_t *) current;
         acpi_create_slit(slit);
         current+=slit->header.length;
         acpi_add_table(rsdp,slit);
 
 	/* SSDT */
-	printk_debug("ACPI:    * SSDT\n");
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 
 	acpi_create_ssdt_generator(ssdt, "DYNADATA");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
 
-	printk_info("ACPI: done.\n");
+	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
Index: src/console/console.c
===================================================================
--- src/console/console.c	(revision 5263)
+++ src/console/console.c	(working copy)
@@ -76,7 +76,7 @@
 {
 #if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
 #if CONFIG_SERIAL_POST==1
-	printk_emerg("POST: 0x%02x\n", value);
+	printk(BIOS_EMERG, "POST: 0x%02x\n", value);
 #endif
 	outb(value, 0x80);
 #endif
@@ -85,7 +85,7 @@
 /* Report a fatal error */
 void __attribute__((noreturn)) die(const char *msg)
 {
-	printk_emerg("%s", msg);
+	printk(BIOS_EMERG, "%s", msg);
 	post_code(0xff);
 	while (1);		/* Halt */
 }
Index: src/boot/selfboot.c
===================================================================
--- src/boot/selfboot.c	(revision 5263)
+++ src/boot/selfboot.c	(working copy)
@@ -80,10 +80,10 @@
 	payload = (struct cbfs_payload *)cbfs_find_file(name, CBFS_TYPE_PAYLOAD);
 	if (payload == NULL)
 		return (void *) -1;
-	printk_debug("Got a payload\n");
+	printk(BIOS_DEBUG, "Got a payload\n");
 
 	selfboot(lb_mem, payload);
-	printk_emerg("SELFBOOT RETURNED!\n");
+	printk(BIOS_EMERG, "SELFBOOT RETURNED!\n");
 
 	return (void *) -1;
 }
@@ -175,21 +175,21 @@
 			break;
 		}
 		if ((mtype == LB_MEM_TABLE) && (start < mend) && (end > mstart)) {
-			printk_err("Payload is overwriting Coreboot tables.\n");
+			printk(BIOS_ERR, "Payload is overwriting Coreboot tables.\n");
 			break;
 		}
 	}
 	if (i == mem_entries) {
-		printk_err("No matching ram area found for range:\n");
-		printk_err("  [0x%016lx, 0x%016lx)\n", start, end);
-		printk_err("Ram areas\n");
+		printk(BIOS_ERR, "No matching ram area found for range:\n");
+		printk(BIOS_ERR, "  [0x%016lx, 0x%016lx)\n", start, end);
+		printk(BIOS_ERR, "Ram areas\n");
 		for(i = 0; i < mem_entries; i++) {
 			uint64_t mstart, mend;
 			uint32_t mtype;
 			mtype = mem->map[i].type;
 			mstart = unpack_lb64(mem->map[i].start);
 			mend = mstart + unpack_lb64(mem->map[i].size);
-			printk_err("  [0x%016lx, 0x%016lx) %s\n",
+			printk(BIOS_ERR, "  [0x%016lx, 0x%016lx) %s\n",
 				(unsigned long)mstart,
 				(unsigned long)mend,
 				(mtype == LB_MEM_RAM)?"RAM":"Reserved");
@@ -220,7 +220,7 @@
 	 *       0 : A new segment is inserted after the seg, or no new one. */
 	unsigned long start, middle, end, ret = 0;
 
-	printk_spew("lb: [0x%016lx, 0x%016lx)\n",
+	printk(BIOS_SPEW, "lb: [0x%016lx, 0x%016lx)\n",
 		lb_start, lb_end);
 
 	/* I don't conflict with coreboot so get out of here */
@@ -231,7 +231,7 @@
 	middle = start + seg->s_filesz;
 	end = start + seg->s_memsz;
 
-	printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n",
+	printk(BIOS_SPEW, "segment: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 		start, middle, end);
 
 	if (seg->compression == CBFS_COMPRESS_NONE) {
@@ -268,7 +268,7 @@
 			/* compute the new value of start */
 			start = seg->s_dstaddr;
 
-			printk_spew("   early: [0x%016lx, 0x%016lx, 0x%016lx)\n",
+			printk(BIOS_SPEW, "   early: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 				new->s_dstaddr,
 				new->s_dstaddr + new->s_filesz,
 				new->s_dstaddr + new->s_memsz);
@@ -305,7 +305,7 @@
 			seg->phdr_next->phdr_prev = new;
 			seg->phdr_next = new;
 
-			printk_spew("   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
+			printk(BIOS_SPEW, "   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 				new->s_dstaddr,
 				new->s_dstaddr + new->s_filesz,
 				new->s_dstaddr + new->s_memsz);
@@ -319,7 +319,7 @@
 	 */
 	seg->s_dstaddr = buffer + (seg->s_dstaddr - lb_start);
 
-	printk_spew(" bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n",
+	printk(BIOS_SPEW, " bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 		seg->s_dstaddr,
 		seg->s_dstaddr + seg->s_filesz,
 		seg->s_dstaddr + seg->s_memsz);
@@ -342,16 +342,16 @@
 	first_segment = segment = &payload->segments;
 
 	while(1) {
-		printk_debug("Loading segment from rom address 0x%p\n", segment);
+		printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment);
 		switch(segment->type) {
 		case PAYLOAD_SEGMENT_PARAMS:
-			printk_debug("  parameter section (skipped)\n");
+			printk(BIOS_DEBUG, "  parameter section (skipped)\n");
 			segment++;
 			continue;
 
 		case PAYLOAD_SEGMENT_CODE:
 		case PAYLOAD_SEGMENT_DATA:
-			printk_debug("  %s (compression=%x)\n",
+			printk(BIOS_DEBUG, "  %s (compression=%x)\n",
 					segment->type == PAYLOAD_SEGMENT_CODE ?  "code" : "data",
 					ntohl(segment->compression));
 			new = malloc(sizeof(*new));
@@ -361,18 +361,18 @@
 
 			new->s_srcaddr = (u32) ((unsigned char *) first_segment) + ntohl(segment->offset);
 			new->s_filesz = ntohl(segment->len);
-			printk_debug("  New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n",
+			printk(BIOS_DEBUG, "  New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n",
 				new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz);
 			/* Clean up the values */
 			if (new->s_filesz > new->s_memsz)  {
 				new->s_filesz = new->s_memsz;
 			}
-			printk_debug("  (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n",
+			printk(BIOS_DEBUG, "  (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n",
 				new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz);
 			break;
 
 		case PAYLOAD_SEGMENT_BSS:
-			printk_debug("  BSS 0x%p (%d byte)\n", (void *) ntohl((u32) segment->load_addr),
+			printk(BIOS_DEBUG, "  BSS 0x%p (%d byte)\n", (void *) ntohl((u32) segment->load_addr),
 				 ntohl(segment->mem_len));
 			new = malloc(sizeof(*new));
 			new->s_filesz = 0;
@@ -381,7 +381,7 @@
 			break;
 
 		case PAYLOAD_SEGMENT_ENTRY:
-			printk_debug("  Entry Point 0x%p\n", (void *) ntohl((u32) segment->load_addr));
+			printk(BIOS_DEBUG, "  Entry Point 0x%p\n", (void *) ntohl((u32) segment->load_addr));
 			*entry =  ntohl((u32) segment->load_addr);
 			/* Per definition, a payload always has the entry point
 			 * as last segment. Thus, we use the occurence of the
@@ -394,7 +394,7 @@
 			/* We found something that we don't know about. Throw
 			 * hands into the sky and run away!
 			 */
-			printk_emerg("Bad segment type %x\n", segment->type);
+			printk(BIOS_EMERG, "Bad segment type %x\n", segment->type);
 			return -1;
 		}
 
@@ -437,7 +437,7 @@
 	}
 	get_bounce_buffer(mem, bounce_high - lb_start);
 	if (!bounce_buffer) {
-		printk_err("Could not find a bounce buffer...\n");
+		printk(BIOS_ERR, "Could not find a bounce buffer...\n");
 		return 0;
 	}
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
@@ -447,7 +447,7 @@
 	}
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
 		unsigned char *dest, *src;
-		printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
+		printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
 			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
 
 		/* Modify the segment to load onto the bounce_buffer if necessary.
@@ -457,7 +457,7 @@
 			continue;
 		}
 
-		printk_debug("Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
+		printk(BIOS_DEBUG, "Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
 			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
 
 		/* Compute the boundaries of the segment */
@@ -471,13 +471,13 @@
 			len = ptr->s_filesz;
 			switch(ptr->compression) {
 				case CBFS_COMPRESS_LZMA: {
-					printk_debug("using LZMA\n");
+					printk(BIOS_DEBUG, "using LZMA\n");
 					len = ulzma(src, dest);
 					break;
 				}
 #if CONFIG_COMPRESSED_PAYLOAD_NRV2B==1
 				case CBFS_COMPRESS_NRV2B: {
-					printk_debug("using NRV2B\n");
+					printk(BIOS_DEBUG, "using NRV2B\n");
 					unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p);
 					unsigned long tmp;
 					len = unrv2b(src, dest, &tmp);
@@ -485,17 +485,17 @@
 				}
 #endif
 				case CBFS_COMPRESS_NONE: {
-					printk_debug("it's not compressed!\n");
+					printk(BIOS_DEBUG, "it's not compressed!\n");
 					memcpy(dest, src, len);
 					break;
 				}
 				default:
-					printk_info( "CBFS:  Unknown compression type %d\n", ptr->compression);
+					printk(BIOS_INFO,  "CBFS:  Unknown compression type %d\n", ptr->compression);
 					return -1;
 			}
 			end = dest + ptr->s_memsz;
 			middle = dest + len;
-			printk_spew("[ 0x%016lx, %016lx, 0x%016lx) <- %016lx\n",
+			printk(BIOS_SPEW, "[ 0x%016lx, %016lx, 0x%016lx) <- %016lx\n",
 				(unsigned long)dest,
 				(unsigned long)middle,
 				(unsigned long)end,
@@ -503,27 +503,27 @@
 
 			/* Zero the extra bytes between middle & end */
 			if (middle < end) {
-				printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n",
+				printk(BIOS_DEBUG, "Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n",
 					(unsigned long)middle, (unsigned long)(end - middle));
 
 				/* Zero the extra bytes */
 				memset(middle, 0, end - middle);
 			}
 			/* Copy the data that's outside the area that shadows coreboot_ram */
-			printk_debug("dest %p, end %p, bouncebuffer %lx\n", dest, end, bounce_buffer);
+			printk(BIOS_DEBUG, "dest %p, end %p, bouncebuffer %lx\n", dest, end, bounce_buffer);
 			if ((unsigned long)end > bounce_buffer) {
 				if ((unsigned long)dest < bounce_buffer) {
 					unsigned char *from = dest;
 					unsigned char *to = (unsigned char*)(lb_start-(bounce_buffer-(unsigned long)dest));
 					unsigned long amount = bounce_buffer-(unsigned long)dest;
-					printk_debug("move prefix around: from %p, to %p, amount: %lx\n", from, to, amount);
+					printk(BIOS_DEBUG, "move prefix around: from %p, to %p, amount: %lx\n", from, to, amount);
 					memcpy(to, from, amount);
 				}
 				if ((unsigned long)end > bounce_buffer + (lb_end - lb_start)) {
 					unsigned long from = bounce_buffer + (lb_end - lb_start);
 					unsigned long to = lb_end;
 					unsigned long amount = (unsigned long)end - from;
-					printk_debug("move suffix around: from %lx, to %lx, amount: %lx\n", from, to, amount);
+					printk(BIOS_DEBUG, "move suffix around: from %lx, to %lx, amount: %lx\n", from, to, amount);
 					memcpy((char*)to, (char*)from, amount);
 				}
 			}
@@ -545,12 +545,12 @@
 	if (!load_self_segments(&head, mem, payload))
 		goto out;
 
-	printk_spew("Loaded segments\n");
+	printk(BIOS_SPEW, "Loaded segments\n");
 
 	/* Reset to booting from this image as late as possible */
 	boot_successful();
 
-	printk_debug("Jumping to boot code at %x\n", entry);
+	printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry);
 	post_code(0xfe);
 
 	/* Jump to kernel */
Index: src/lib/generic_sdram.c
===================================================================
--- src/lib/generic_sdram.c	(revision 5263)
+++ src/lib/generic_sdram.c	(working copy)
@@ -7,7 +7,7 @@
 static inline void print_debug_sdram_8(const char *strval, uint32_t val)
 {
 #if CONFIG_USE_INIT
-        printk_debug("%s%02x\r\n", strval, val);
+        printk(BIOS_DEBUG, "%s%02x\r\n", strval, val);
 #else
         print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
 #endif
Index: src/lib/lzma.c
===================================================================
--- src/lib/lzma.c	(revision 5263)
+++ src/lib/lzma.c	(working copy)
@@ -29,19 +29,19 @@
 	memcpy(properties, src, LZMA_PROPERTIES_SIZE);
 	outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
 	if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
-		printk_warning("lzma: Incorrect stream properties.\n");
+		printk(BIOS_WARNING, "lzma: Incorrect stream properties.\n");
 		return 0;
 	}
 	mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
 	if (mallocneeds > 15980) {
-		printk_warning("lzma: Decoder scratchpad too small!\n");
+		printk(BIOS_WARNING, "lzma: Decoder scratchpad too small!\n");
 		return 0;
 	}
 	state.Probs = (CProb *)scratchpad;
 	res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed,
 		dst, outSize, &outProcessed);
 	if (res != 0) {
-		printk_warning("lzma: Decoding error = %d\n", res);
+		printk(BIOS_WARNING, "lzma: Decoding error = %d\n", res);
 		return 0;
 	}
 	return outSize;
Index: src/lib/clog2.c
===================================================================
--- src/lib/clog2.c	(revision 5263)
+++ src/lib/clog2.c	(working copy)
@@ -17,7 +17,7 @@
 
         if (! x) {
 #ifdef DEBUG_LOG2
-                printk_warning("%s called with invalid parameter of 0\n",
+                printk(BIOS_WARNING, "%s called with invalid parameter of 0\n",
 			__func__);
 #endif
                 return -1;
Index: src/lib/malloc.c
===================================================================
--- src/lib/malloc.c	(revision 5263)
+++ src/lib/malloc.c	(working copy)
@@ -4,7 +4,7 @@
 #if 0
 #define MALLOCDBG(x)
 #else
-#define MALLOCDBG(x...) printk_spew(x)
+#define MALLOCDBG(x...) printk(BIOS_SPEW, x)
 #endif
 extern unsigned char _heap, _eheap;
 static void *free_mem_ptr = &_heap;		/* Start of heap */
Index: src/lib/generic_dump_spd.c
===================================================================
--- src/lib/generic_dump_spd.c	(revision 5263)
+++ src/lib/generic_dump_spd.c	(working copy)
@@ -69,25 +69,25 @@
 {
 	unsigned device;
 	device = SMBUS_MEM_DEVICE_START;
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	while(device <= SMBUS_MEM_DEVICE_END) {
 		int status = 0;
 		int i;
-		printk_debug("dimm %02x", device);
+		printk(BIOS_DEBUG, "dimm %02x", device);
 		for(i = 0; (i < 256) && (status == 0); i++) {
 			unsigned char byte;
 			if ((i % 20) == 0) {
-				printk_debug("\n%3d: ", i);
+				printk(BIOS_DEBUG, "\n%3d: ", i);
 			}
 			status = smbus_read_byte(device, i, &byte);
 			if (status != 0) {
-				printk_debug("bad device\n");
+				printk(BIOS_DEBUG, "bad device\n");
 				continue;
 			}
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 #endif
Index: src/lib/cbfs.c
===================================================================
--- src/lib/cbfs.c	(revision 5263)
+++ src/lib/cbfs.c	(working copy)
@@ -42,13 +42,13 @@
 
 	case CBFS_COMPRESS_LZMA:
 		if (!ulzma(src, dst)) {
-			printk_err("CBFS: LZMA decompression failed!\n");
+			printk(BIOS_ERR, "CBFS: LZMA decompression failed!\n");
 			return -1;
 		}
 		return 0;
 
 	default:
-		printk_info( "CBFS:  Unknown compression type %d\n", algo);
+		printk(BIOS_INFO,  "CBFS:  Unknown compression type %d\n", algo);
 		return -1;
 	}
 }
@@ -63,20 +63,20 @@
 	struct cbfs_header *header;
 
 	void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR);
-	printk_spew("Check CBFS header at %p\n", ptr);
+	printk(BIOS_SPEW, "Check CBFS header at %p\n", ptr);
 	header = (struct cbfs_header *) ptr;
 
-	printk_spew("magic is %08x\n", ntohl(header->magic));
+	printk(BIOS_SPEW, "magic is %08x\n", ntohl(header->magic));
 	if (ntohl(header->magic) != CBFS_HEADER_MAGIC) {
-		printk_err("ERROR: No valid CBFS header found!\n");
+		printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n");
 		if (header->magic == 0xffffffff) {
-			printk_err("Maybe the ROM isn't entirely mapped yet?\n"
+			printk(BIOS_ERR, "Maybe the ROM isn't entirely mapped yet?\n"
 				"See (and report to) http://www.coreboot.org/Infrastructure_Projects#CBFS\n");
 		}
 		return NULL;
 	}
 
-	printk_spew("Found CBFS header at %p\n", ptr);
+	printk(BIOS_SPEW, "Found CBFS header at %p\n", ptr);
 	return header;
 }
 
@@ -94,17 +94,17 @@
 	while(1) {
 		struct cbfs_file *file = (struct cbfs_file *) offset;
 		if (!cbfs_check_magic(file)) return NULL;
-		printk_spew("Check %s\n", CBFS_NAME(file));
+		printk(BIOS_SPEW, "Check %s\n", CBFS_NAME(file));
 		if (!strcmp(CBFS_NAME(file), name))
 			return file;
 
 		int flen = ntohl(file->len);
 		int foffset = ntohl(file->offset);
-		printk_spew("CBFS: follow chain: %p + %x + %x + align -> ", (void *)offset, foffset, flen);
+		printk(BIOS_SPEW, "CBFS: follow chain: %p + %x + %x + align -> ", (void *)offset, foffset, flen);
 
 		unsigned long oldoffset = offset;
 		offset = ALIGN(offset + foffset + flen, align);
-		printk_spew("%p\n", (void *)offset);
+		printk(BIOS_SPEW, "%p\n", (void *)offset);
 		if (offset <= oldoffset) return NULL;
 
 		if (offset < 0xFFFFFFFF - ntohl(header->romsize))
@@ -117,13 +117,13 @@
 	struct cbfs_file *file = cbfs_find(name);
 
 	if (file == NULL) {
-		printk_info( "CBFS:  Could not find file %s\n",
+		printk(BIOS_INFO,  "CBFS:  Could not find file %s\n",
 		       name);
 		return NULL;
 	}
 
 	if (ntohl(file->type) != type) {
-		printk_info( "CBFS:  File %s is of type %x instead of"
+		printk(BIOS_INFO,  "CBFS:  File %s is of type %x instead of"
 		       "type %x\n", name, file->type, type);
 
 		return NULL;
@@ -193,7 +193,7 @@
 	if (stage == NULL)
 		return (void *) -1;
 
-	printk_info("Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n", 
+	printk(BIOS_INFO, "Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n", 
 			name,
 			(u32) stage->load, stage->memlen, 
 			stage->entry);
@@ -206,7 +206,7 @@
 			     stage->len))
 		return (void *) -1;
 
-	printk_debug("Stage: done loading.\n");
+	printk(BIOS_DEBUG, "Stage: done loading.\n");
 
 	entry = stage->entry;
 	// entry = ntohl((u32) stage->entry);
@@ -223,13 +223,13 @@
 		return 1;
 
 	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
-		printk_info( "CBFS:  Unable to run %s:  Compressed file"
+		printk(BIOS_INFO,  "CBFS:  Unable to run %s:  Compressed file"
 		       "Not supported for in-place execution\n", name);
 		return 1;
 	}
 
 	/* FIXME: This isn't right */
-	printk_info( "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
+	printk(BIOS_INFO,  "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
 	return run_address((void *) ntohl((u32) stage->entry));
 }
 
Index: src/lib/ramtest.c
===================================================================
--- src/lib/ramtest.c	(revision 5263)
+++ src/lib/ramtest.c	(working copy)
@@ -34,7 +34,7 @@
 	 * Fill.
 	 */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop);
+	printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop);
 #else
 	print_debug("DRAM fill: ");
 	print_debug_hex32(start);
@@ -46,7 +46,7 @@
 		/* Display address being filled */
 		if (!(addr & 0xfffff)) {
 #if CONFIG_USE_PRINTK_IN_CAR
-			printk_debug("%08lx \r", addr);
+			printk(BIOS_DEBUG, "%08lx \r", addr);
 #else
 			print_debug_hex32(addr);
 			print_debug(" \r");
@@ -60,7 +60,7 @@
 #endif
 	/* Display final address */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%08lx\r\nDRAM filled\r\n", addr);
+	printk(BIOS_DEBUG, "%08lx\r\nDRAM filled\r\n", addr);
 #else
 	print_debug_hex32(addr);
 	print_debug("\r\nDRAM filled\r\n");
@@ -75,7 +75,7 @@
 	 * Verify.
 	 */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop);
+	printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop);
 #else
 	print_debug("DRAM verify: ");
 	print_debug_hex32(start);
@@ -88,7 +88,7 @@
 		/* Display address being tested */
 		if (!(addr & 0xfffff)) {
 #if CONFIG_USE_PRINTK_IN_CAR
-			printk_debug("%08lx \r", addr);
+			printk(BIOS_DEBUG, "%08lx \r", addr);
 #else
 			print_debug_hex32(addr);
 			print_debug(" \r");
@@ -98,7 +98,7 @@
 		if (value != addr) {
 			/* Display address with error */
 #if CONFIG_USE_PRINTK_IN_CAR
-			printk_err("Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value);
+			printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value);
 #else
 			print_err("Fail: @0x");
 			print_err_hex32(addr);
@@ -109,7 +109,7 @@
 			i++;
 			if(i>256) {
 #if CONFIG_USE_PRINTK_IN_CAR
-				printk_debug("Aborting.\n\r");
+				printk(BIOS_DEBUG, "Aborting.\n\r");
 #else
 				print_debug("Aborting.\n\r");
 #endif
@@ -119,14 +119,14 @@
 	}
 	/* Display final address */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%08lx", addr);
+	printk(BIOS_DEBUG, "%08lx", addr);
 #else
 	print_debug_hex32(addr);
 #endif
 
 	if (i) {
 #if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("\r\nDRAM did _NOT_ verify!\r\n");
+		printk(BIOS_DEBUG, "\r\nDRAM did _NOT_ verify!\r\n");
 #else
 		print_debug("\r\nDRAM did _NOT_ verify!\r\n");
 #endif
@@ -134,7 +134,7 @@
 	}
 	else {
 #if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("\r\nDRAM range verified.\r\n");
+		printk(BIOS_DEBUG, "\r\nDRAM range verified.\r\n");
 #else
 		print_debug("\r\nDRAM range verified.\r\n");
 #endif
@@ -150,7 +150,7 @@
 	 * are tested.   -Tyson
 	 */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("Testing DRAM : %08lx - %08lx\r\n", start, stop);
+	printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\r\n", start, stop);
 #else
 	print_debug("Testing DRAM : ");
 	print_debug_hex32(start);
@@ -161,7 +161,7 @@
 	ram_fill(start, stop);
 	ram_verify(start, stop);
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("Done.\r\n");
+	printk(BIOS_DEBUG, "Done.\r\n");
 #else
 	print_debug("Done.\r\n");
 #endif
Index: src/lib/cbmem.c
===================================================================
--- src/lib/cbmem.c	(revision 5263)
+++ src/lib/cbmem.c	(working copy)
@@ -23,7 +23,7 @@
 #include <console/console.h>
 
 #if 1
-#define debug(x...) printk_debug(x)
+#define debug(x...) printk(BIOS_DEBUG, x)
 #else
 #define debug(x...)
 #endif
@@ -110,13 +110,13 @@
 	}
 
 	if (cbmem_toc[0].magic != CBMEM_MAGIC) {
-		printk_err("ERROR: CBMEM was not initialized yet.\n");
+		printk(BIOS_ERR, "ERROR: CBMEM was not initialized yet.\n");
 		return NULL;
 	}
 
 	/* Will the entry fit at all? */
 	if (size > cbmem_toc[0].size) {
-		printk_err("ERROR: Not enough memory for table %x\n", id);
+		printk(BIOS_ERR, "ERROR: Not enough memory for table %x\n", id);
 		return NULL;
 	}
 
@@ -132,7 +132,7 @@
 	}
 
 	if (i >= MAX_CBMEM_ENTRIES) {
-		printk_err("ERROR: No more CBMEM entries available.\n");
+		printk(BIOS_ERR, "ERROR: No more CBMEM entries available.\n");
 		return NULL;
 	}
 
@@ -214,19 +214,19 @@
 
 		if (cbmem_toc[i].magic != CBMEM_MAGIC)
 			continue;
-		printk_debug("%2d. ", i);
+		printk(BIOS_DEBUG, "%2d. ", i);
 		switch (cbmem_toc[i].id) {
-		case CBMEM_ID_FREESPACE: printk_debug("FREE SPACE "); break;
-		case CBMEM_ID_GDT:	 printk_debug("GDT        "); break;
-		case CBMEM_ID_ACPI:	 printk_debug("ACPI       "); break;
-		case CBMEM_ID_CBTABLE:	 printk_debug("COREBOOT   "); break;
-		case CBMEM_ID_PIRQ:	 printk_debug("IRQ TABLE  "); break;
-		case CBMEM_ID_MPTABLE:	 printk_debug("SMP TABLE  "); break;
-		case CBMEM_ID_RESUME:	 printk_debug("ACPI RESUME"); break;
-		default: printk_debug("%08x ", cbmem_toc[i].id);
+		case CBMEM_ID_FREESPACE: printk(BIOS_DEBUG, "FREE SPACE "); break;
+		case CBMEM_ID_GDT:	 printk(BIOS_DEBUG, "GDT        "); break;
+		case CBMEM_ID_ACPI:	 printk(BIOS_DEBUG, "ACPI       "); break;
+		case CBMEM_ID_CBTABLE:	 printk(BIOS_DEBUG, "COREBOOT   "); break;
+		case CBMEM_ID_PIRQ:	 printk(BIOS_DEBUG, "IRQ TABLE  "); break;
+		case CBMEM_ID_MPTABLE:	 printk(BIOS_DEBUG, "SMP TABLE  "); break;
+		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
+		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
-		printk_debug("%08llx ", cbmem_toc[i].base);
-		printk_debug("%08llx\n", cbmem_toc[i].size);
+		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);
+		printk(BIOS_DEBUG, "%08llx\n", cbmem_toc[i].size);
 	}
 }
 #endif
Index: src/lib/usbdebug_direct.c
===================================================================
--- src/lib/usbdebug_direct.c	(revision 5263)
+++ src/lib/usbdebug_direct.c	(working copy)
@@ -23,7 +23,7 @@
 #include <console/console.h>
 #else
 #if CONFIG_USE_PRINTK_IN_CAR==0
-#define printk_debug(fmt, arg...)   do {} while(0)
+#define printk(BIOS_DEBUG, fmt, arg...)   do {} while(0)
 #endif
 #endif
 
@@ -304,7 +304,7 @@
 				delay_time += delay;
 			} while ((portsc & PORT_RESET) && (--loop > 0));
 			if (!loop) {
-				printk_debug("ehci_reset_port forced done");
+				printk(BIOS_DEBUG, "ehci_reset_port forced done");
 			}
 		}
 
@@ -342,7 +342,7 @@
 
 #define DBGP_DEBUG 1
 #if DBGP_DEBUG
-# define dbgp_printk printk_debug
+# define dbgp_printk(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
 #define dbgp_printk(fmt, arg...)   do {} while(0)
 #endif
Index: src/northbridge/via/cx700/cx700_vga.c
===================================================================
--- src/northbridge/via/cx700/cx700_vga.c	(revision 5263)
+++ src/northbridge/via/cx700/cx700_vga.c	(working copy)
@@ -49,7 +49,7 @@
 {
 	device_t dev;
 
-	printk_debug("write_protect_vgabios\n");
+	printk(BIOS_DEBUG, "write_protect_vgabios\n");
 
 	dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
 	if (dev)
@@ -64,7 +64,7 @@
 {
 	u8 reg8;
 
-	printk_debug("Initializing VGA...\n");
+	printk(BIOS_DEBUG, "Initializing VGA...\n");
 
 	//*
 	pci_write_config8(dev, 0x04, 0x07);
@@ -75,10 +75,10 @@
 	pci_write_config8(dev, 0x3c, 0x0b);
 	//*/
 
-	printk_debug("Executing VGA option rom in real mode\n");
+	printk(BIOS_DEBUG, "Executing VGA option rom in real mode\n");
 	setup_realmode_idt();
 	do_vgabios();
-	printk_debug("Enable VGA console\n");
+	printk(BIOS_DEBUG, "Enable VGA console\n");
 	vga_enable_console();
 
 	/* It's not clear if these need to be programmed before or after
Index: src/northbridge/via/cx700/cx700_lpc.c
===================================================================
--- src/northbridge/via/cx700/cx700_lpc.c	(revision 5263)
+++ src/northbridge/via/cx700/cx700_lpc.c	(working copy)
@@ -56,7 +56,7 @@
 
 static void pci_routing_fixup(struct device *dev)
 {
-	printk_debug("%s: device is %p\n", __FUNCTION__, dev);
+	printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
 
 	/* set up PCI IRQ routing */
 	pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
@@ -64,17 +64,17 @@
 	pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
 
 	/* Assigning IRQs */
-	printk_debug("Setting up USB interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
 	pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
 
-	printk_debug("Setting up VGA interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
 	pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
 
-	printk_debug("Setting up PCI slot interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
 	pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
 	// more?
 
-	printk_debug("Setting up AC97 interrupts.\n");
+	printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
 	pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
 }
 
@@ -169,7 +169,7 @@
 {
 	unsigned char enables;
 
-	printk_debug("VIA CX700 LPC bridge init\n");
+	printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
 
 	// enable the internal I/O decode
 	enables = pci_read_config8(dev, 0x6C);
Index: src/northbridge/via/cx700/raminit.c
===================================================================
--- src/northbridge/via/cx700/raminit.c	(revision 5263)
+++ src/northbridge/via/cx700/raminit.c	(working copy)
@@ -26,7 +26,7 @@
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINTK_DEBUG(x...)      printk_debug(x)
+#define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
 #else
 #define PRINTK_DEBUG(x...)
 #endif
@@ -105,9 +105,9 @@
 #define REGISTERPRESET(bus,dev,fun,bdfspec) \
 	{ u8 i, reg; \
 		for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \
-			printk_debug("Writing bus " #bus " dev " #dev " fun " #fun " register "); \
-			printk_debug("%02x", (bdfspec)[i].reg); \
-			printk_debug("\n"); \
+			printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \
+			printk(BIOS_DEBUG, "%02x", (bdfspec)[i].reg); \
+			printk(BIOS_DEBUG, "\n"); \
 			reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \
 			reg &= (bdfspec)[i].mask; \
 			reg |= (bdfspec)[i].val; \
@@ -184,7 +184,7 @@
 
 	regs = pci_read_config8(MEMCTRL, 0x6c);
 	if (regs & (1 << 6))
-		printk_debug("DDR2 Detected.\n");
+		printk(BIOS_DEBUG, "DDR2 Detected.\n");
 	else
 		die("ERROR: DDR1 memory detected but not supported by coreboot.\n");
 
@@ -201,25 +201,25 @@
 	/* SPD 9 SDRAM Cycle Time */
 	GET_SPD(dimm, spds, regs, 9);
 
-	printk_debug("\nDDRII ");
+	printk(BIOS_DEBUG, "\nDDRII ");
 	if (spds <= 0x3d) {
-		printk_debug("533");
+		printk(BIOS_DEBUG, "533");
 		val = DDRII_533;
 		t = 38;
 	} else if (spds <= 0x50) {
-		printk_debug("400");
+		printk(BIOS_DEBUG, "400");
 		val = DDRII_400;
 		t = 50;
 	} else if (spds <= 0x60) {
-		printk_debug("333");
+		printk(BIOS_DEBUG, "333");
 		val = DDRII_333;
 		t = 60;
 	} else if (spds <= 0x75) {
-		printk_debug("266");
+		printk(BIOS_DEBUG, "266");
 		val = DDRII_266;
 		t = 75;
 	} else {
-		printk_debug("200");
+		printk(BIOS_DEBUG, "200");
 		val = DDRII_200;
 		t = 100;
 	}
@@ -259,45 +259,45 @@
 	/* SPD 9 18 23 25 CAS Latency NB3DRAM_REG62[2:0] */
 	/* Read SPD byte 18 CAS Latency */
 	GET_SPD(dimm, spds, regs, SPD_CAS_LAT);
-	printk_debug("\nCAS Supported ");
+	printk(BIOS_DEBUG, "\nCAS Supported ");
 	if (spds & SPD_CAS_LAT_2)
-		printk_debug("2 ");
+		printk(BIOS_DEBUG, "2 ");
 	if (spds & SPD_CAS_LAT_3)
-		printk_debug("3 ");
+		printk(BIOS_DEBUG, "3 ");
 	if (spds & SPD_CAS_LAT_4)
-		printk_debug("4 ");
+		printk(BIOS_DEBUG, "4 ");
 	if (spds & SPD_CAS_LAT_5)
-		printk_debug("5 ");
+		printk(BIOS_DEBUG, "5 ");
 	if (spds & SPD_CAS_LAT_6)
-		printk_debug("6");
+		printk(BIOS_DEBUG, "6");
 
 	/* We don't consider CAS = 6, because CX700 doesn't support it */
-	printk_debug("\n CAS:");
+	printk(BIOS_DEBUG, "\n CAS:");
 	if (spds & SPD_CAS_LAT_5) {
-		printk_debug("Starting at CL5");
+		printk(BIOS_DEBUG, "Starting at CL5");
 		val = 0x3;
 		/* See whether we can improve it */
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 		if ((spds & SPD_CAS_LAT_4) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL4");
+			printk(BIOS_DEBUG, "\n... going to CL4");
 			val = 0x2;
 		}
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 		if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL3");
+			printk(BIOS_DEBUG, "\n... going to CL3");
 			val = 0x1;
 		}
 	} else {
-		printk_debug("Starting at CL4");
+		printk(BIOS_DEBUG, "Starting at CL4");
 		val = 0x2;
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 		if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL3");
+			printk(BIOS_DEBUG, "\n... going to CL3");
 			val = 0x1;
 		}
 		GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 		if ((spds & SPD_CAS_LAT_2) && (tmp < 0x50)) {
-			printk_debug("\n... going to CL2");
+			printk(BIOS_DEBUG, "\n... going to CL2");
 			val = 0x0;
 		}
 	}
@@ -308,7 +308,7 @@
 
 	/* SPD 27 Trp NB3DRAM_REG64[3:2] */
 	GET_SPD(dimm, spds, regs, SPD_TRP);
-	printk_debug("\nTrp %d", spds);
+	printk(BIOS_DEBUG, "\nTrp %d", spds);
 	spds >>= 2;
 	for (val = 2; val <= 5; val++) {
 		if (spds <= (val * t / 10)) {
@@ -324,7 +324,7 @@
 
 	/* SPD 29 Trcd NB3DRAM_REG64[7:6] */
 	GET_SPD(dimm, spds, regs, SPD_TRCD);
-	printk_debug("\nTrcd %d", spds);
+	printk(BIOS_DEBUG, "\nTrcd %d", spds);
 	spds >>= 2;
 	for (val = 2; val <= 5; val++) {
 		if (spds <= (val * t / 10)) {
@@ -340,7 +340,7 @@
 
 	/* SPD 30 Tras NB3DRAM_REG62[7:4] */
 	GET_SPD(dimm, spds, regs, SPD_TRAS);
-	printk_debug("\nTras %d", spds);
+	printk(BIOS_DEBUG, "\nTras %d", spds);
 	for (val = 5; val <= 20; val++) {
 		if (spds <= (val * t / 10)) {
 			val = val - 5;
@@ -355,7 +355,7 @@
 
 	/* SPD 42 SPD 40 Trfc NB3DRAM_REG61[5:0] */
 	GET_SPD(dimm, spds, regs, SPD_TRFC);
-	printk_debug("\nTrfc %d", spds);
+	printk(BIOS_DEBUG, "\nTrfc %d", spds);
 	tmp = spds;
 	GET_SPD(dimm, spds, regs, SPD_EX_TRC_TRFC);
 	if (spds & 0x1)
@@ -382,7 +382,7 @@
 		}
 	}
 	val <<= 6;
-	printk_debug("\nTrrd val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTrrd val = 0x%x", val);
 	regs = pci_read_config8(MEMCTRL, 0x63);
 	regs &= ~0xc0;
 	regs |= val;
@@ -397,7 +397,7 @@
 		}
 	}
 	val <<= 6;
-	printk_debug("\nTwr val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTwr val = 0x%x", val);
 
 	regs = pci_read_config8(MEMCTRL, 0x61);
 	regs &= ~0xc0;
@@ -407,13 +407,13 @@
 	/* SPD 37 Twtr NB3DRAM_REG63[1] */
 	GET_SPD(dimm, spds, regs, SPD_TWTR);
 	spds >>= 2;
-	printk_debug("\nTwtr 0x%x", spds);
+	printk(BIOS_DEBUG, "\nTwtr 0x%x", spds);
 	if (spds <= (t * 2 / 10))
 		val = 0;
 	else
 		val = 1;
 	val <<= 1;
-	printk_debug("\nTwtr val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTwtr val = 0x%x", val);
 
 	regs = pci_read_config8(MEMCTRL, 0x63);
 	regs &= ~0x2;
@@ -423,13 +423,13 @@
 	/* SPD 38 Trtp NB3DRAM_REG63[3] */
 	GET_SPD(dimm, spds, regs, SPD_TRTP);
 	spds >>= 2;
-	printk_debug("\nTrtp 0x%x", spds);
+	printk(BIOS_DEBUG, "\nTrtp 0x%x", spds);
 	if (spds <= (t * 2 / 10))
 		val = 0;
 	else
 		val = 1;
 	val <<= 3;
-	printk_debug("\nTrtp val = 0x%x", val);
+	printk(BIOS_DEBUG, "\nTrtp val = 0x%x", val);
 
 	regs = pci_read_config8(MEMCTRL, 0x63);
 	regs &= ~0x8;
@@ -534,7 +534,7 @@
 			val += spds;
 		}
 	}
-	printk_debug("\nchip #%d", val);
+	printk(BIOS_DEBUG, "\nchip #%d", val);
 	if (val > 18)
 		regs = 0xdb;
 	else
@@ -852,7 +852,7 @@
 	i |= DDR2_Twr_table[val];
 	read32(i);
 
-	printk_debug("MRS = %08x\n", i);
+	printk(BIOS_DEBUG, "MRS = %08x\n", i);
 
 	udelay(15);
 
@@ -1073,7 +1073,7 @@
 		else
 			sdram_clear_vr_addr(ctrl, i);
 	}
-	printk_debug("\nDQSI Low %08x", dl);
+	printk(BIOS_DEBUG, "\nDQSI Low %08x", dl);
 	for (dh = dl; dh < 0x3f; dh += 2) {
 		reg8 = dh & 0x3f;
 		reg8 |= 0x80;	/* Set Manual Mode */
@@ -1106,7 +1106,7 @@
 			break;
 		}
 	}
-	printk_debug("\nDQSI High %02x", dh);
+	printk(BIOS_DEBUG, "\nDQSI High %02x", dh);
 	pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_LOW_REG, dl);
 	pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_HIGH_REG, dh);
 	reg8 = pci_read_config8(MEMCTRL, 0X90) & 0X7;
Index: src/northbridge/via/cx700/northbridge.c
===================================================================
--- src/northbridge/via/cx700/northbridge.c	(revision 5263)
+++ src/northbridge/via/cx700/northbridge.c	(working copy)
@@ -119,7 +119,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 	high_tables_size = HIGH_TABLES_SIZE* 1024;
-	printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+	printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 	/* Report the memory regions */
Index: src/northbridge/via/cx700/cx700_sata.c
===================================================================
--- src/northbridge/via/cx700/cx700_sata.c	(revision 5263)
+++ src/northbridge/via/cx700/cx700_sata.c	(working copy)
@@ -46,7 +46,7 @@
 {
 	u8 reg8;
 
-	printk_debug("Configuring VIA SATA & EIDE Controller\n");
+	printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n");
 
 	/* Class IDE Disk, instead of RAID controller */
 	reg8 = pci_read_config8(dev, 0x45);
@@ -57,7 +57,7 @@
 	pci_write_config8(dev, 0x45, reg8);
 
 #if defined(DISABLE_SATA) && (DISABLE_SATA == 1)
-	printk_info("Disabling SATA (Primary Channel)\n");
+	printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n");
 	/* Disable SATA channels */
 	pci_write_config8(dev, 0x40, 0x00);
 #else
@@ -132,12 +132,12 @@
 	reg8 &= ~0xa0;
 	pci_write_config8(dev, 0x42, reg8);
 	reg8 = pci_read_config8(dev, 0x42);
-	printk_debug("Reg 0x42 read back as 0x%x\n", reg8);
+	printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
 
 	/* Support Staggered Spin-Up */
 	reg8 = pci_read_config8(dev, 0xb9);
 	if ((reg8 & 0x8) == 0) {
-		printk_debug("start OOB sequence on both drives\n");
+		printk(BIOS_DEBUG, "start OOB sequence on both drives\n");
 		reg8 |= 0x30;
 		pci_write_config8(dev, 0xb9, reg8);
 	}
Index: src/northbridge/via/cx700/cx700_usb.c
===================================================================
--- src/northbridge/via/cx700/cx700_usb.c	(revision 5263)
+++ src/northbridge/via/cx700/cx700_usb.c	(working copy)
@@ -28,7 +28,7 @@
 	u8 reg8;
 
 	/* USB Specification says the device must be Bus Master */
-	printk_debug("UHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
@@ -37,7 +37,7 @@
 	reg8 |= (1 << 0);
 	pci_write_config8(dev, 0xca, reg8);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static struct device_operations usb_ops = {
Index: src/northbridge/via/cx700/vgabios.c
===================================================================
--- src/northbridge/via/cx700/vgabios.c	(revision 5263)
+++ src/northbridge/via/cx700/vgabios.c	(working copy)
@@ -315,10 +315,10 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
@@ -326,7 +326,7 @@
 #warning ROM address hardcoded to 512K
 	rom = (unsigned int)cbfs_load_optionrom(dev->vendor, dev->device, 0); 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
-	printk_debug("rom base, size: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
 
 	buf = (unsigned char *)rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -339,13 +339,13 @@
 		if (buf[0] == 0x55 && buf[1] == 0xAA) {
 			busdevfn =
 			    (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 			real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -512,28 +512,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
 		     eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *)esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *)esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -552,7 +552,7 @@
 				  &ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", intnumber);
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", intnumber);
 		break;
 	}
 	if (ret)
@@ -669,7 +669,7 @@
 				// devfn is an int, so we mask it off. 
 				busdevfn = (dev->bus->secondary << 8)
 				    | (dev->path.pci.devfn & 0xff);
-				printk_debug("0x%x: return 0x%x\n", func,
+				printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
 					     busdevfn);
 				*pebx = busdevfn;
 				retval = 0;
@@ -696,8 +696,7 @@
 			reg = *pedi;
 			dev = dev_find_slot(bus, devfn);
 			if (!dev) {
-				printk_debug
-				    ("0x%x: BAD DEVICE bus %d devfn 0x%x\n",
+				printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n",
 				     func, bus, devfn);
 				// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 				*peax = PCIBIOS_BADREG;
@@ -732,15 +731,14 @@
 
 			if (retval)
 				retval = PCIBIOS_BADREG;
-			printk_debug
-			    ("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+			printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 			*peax = 0;
 			retval = 0;
 		}
 		break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
 		break;
 	}
 
Index: src/northbridge/via/cn400/vlink.c
===================================================================
--- src/northbridge/via/cn400/vlink.c	(revision 5263)
+++ src/northbridge/via/cn400/vlink.c	(working copy)
@@ -43,7 +43,7 @@
 	u8 reg, reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
 	/* Disconnect the VLink Before Changing Settings */
 	reg = pci_read_config8(dev, 0x47);
@@ -107,17 +107,17 @@
 	reg &= ~0x04;
 	pci_write_config8(dev, 0x47, reg);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
 }
@@ -141,19 +141,19 @@
 	u8 reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
@@ -178,19 +178,19 @@
 	u8 reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
@@ -214,19 +214,19 @@
 	u8 reg8;
 	int i, j;
 
-	printk_spew("Entering CN400 %s\n", __func__);
+	printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
Index: src/northbridge/via/cn400/agp.c
===================================================================
--- src/northbridge/via/cn400/agp.c	(revision 5263)
+++ src/northbridge/via/cn400/agp.c	(working copy)
@@ -36,7 +36,7 @@
 	int i, j;
 
 	/* Some of this may not be necessary (should be handled by the OS). */
-	printk_debug("Enabling AGP.\n");
+	printk(BIOS_DEBUG, "Enabling AGP.\n");
 
 	/* Allow R/W access to AGP registers. */
 	pci_write_config8(dev, 0x4d, 0x05);
@@ -113,17 +113,17 @@
 	pci_write_config8(dev, 0xc1, 0x02);
 
 #ifdef DEBUG_CN400
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
 }
@@ -170,7 +170,7 @@
 	u8 reg8;
 	int i, j;
 
-	printk_debug("Entering %s\n", __func__);
+	printk(BIOS_DEBUG, "Entering %s\n", __func__);
 
 	pci_write_config16(dev, 0x4, 0x0107);
 
@@ -208,17 +208,17 @@
 	pci_write_config8(dev, 0x44, 0x34);
 	pci_write_config8(dev, 0x45, 0x72);
 
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 
 }
Index: src/northbridge/via/cn400/northbridge.c
===================================================================
--- src/northbridge/via/cn400/northbridge.c	(revision 5263)
+++ src/northbridge/via/cn400/northbridge.c	(working copy)
@@ -41,7 +41,7 @@
 	u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8;
 	int i, j;
 
-	printk_spew("Entering cn400 memctrl_init.\n");
+	printk(BIOS_SPEW, "Entering cn400 memctrl_init.\n");
 	/* vlink mirror */
 	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
@@ -53,7 +53,7 @@
 	reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0;
 
 	pci_write_config16(dev, 0x84, reg16);
-	printk_spew("Low Top Address = 0x%04X\n", reg16);
+	printk(BIOS_SPEW, "Low Top Address = 0x%04X\n", reg16);
 
 	/* Set up the VGA framebuffer size and Base Address   */
 	/* Note dependencies between agp.c and vga.c and here */
@@ -110,20 +110,20 @@
 	pci_write_config8(dev, 0xA0, reg8);
 
 #ifdef DEBUG_CN400
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
-	printk_spew("Leaving cn400 %s.\n", __func__);
+	printk(BIOS_SPEW, "Leaving cn400 %s.\n", __func__);
 }
 
 static const struct device_operations memctrl_operations = {
@@ -144,7 +144,7 @@
 {
 	struct resource *resource;
 
-	printk_spew("Entering %s.\n", __func__);
+	printk(BIOS_SPEW, "Entering %s.\n", __func__);
 
 	/* Initialize the system wide I/O space constraints. */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
@@ -158,7 +158,7 @@
 	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 	    IORESOURCE_ASSIGNED;
 
-	printk_spew("Leaving %s.\n", __func__);
+	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
 static void ram_resource(device_t dev, unsigned long index,
@@ -180,7 +180,7 @@
 {
 	struct resource *res;
 
-	printk_spew("Configuring Via C3 LAPIC Fixed Resource\n");
+	printk(BIOS_SPEW, "Configuring Via C3 LAPIC Fixed Resource\n");
 	/* Fixed LAPIC resource */
 	res = new_resource(dev, 1);
 	res->base = (resource_t) base;
@@ -205,7 +205,7 @@
 	struct resource *min = NULL;
 	u32 tolm;
 
-	printk_spew("Entering CN400 find_pci_tolm\n");
+	printk(BIOS_SPEW, "Entering CN400 find_pci_tolm\n");
 
 	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
 			     tolm_test, &min);
@@ -213,7 +213,7 @@
 	if (min && tolm > min->base)
 		tolm = min->base;
 
-	printk_spew("Leaving CN400 find_pci_tolm\n");
+	printk(BIOS_SPEW, "Leaving CN400 find_pci_tolm\n");
 
 	return tolm;
 }
@@ -229,7 +229,7 @@
 	device_t mc_dev;
 	u32 pci_tolm;
 
-	printk_spew("Entering %s.\n", __func__);
+	printk(BIOS_SPEW, "Entering %s.\n", __func__);
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -244,7 +244,7 @@
 		tomk = rambits * 32 * 1024;
 		/* Compute the Top Of Low Memory (TOLM), in Kb. */
 		tolmk = pci_tolm >> 10;
-		printk_spew("tomk is 0x%x, tolmk is 0x%08X\n", tomk, tolmk);
+		printk(BIOS_SPEW, "tomk is 0x%x, tolmk is 0x%08X\n", tomk, tolmk);
 		if (tolmk >= tomk) {
 			/* The PCI hole does does not overlap the memory. */
 			tolmk = tomk;
@@ -254,7 +254,7 @@
 		/* Locate the High Tables at the Top of Low Memory below the Video RAM */
 		high_tables_base = (uint64_t) (tolmk - (CONFIG_VIDEO_MB *1024) - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = (uint64_t) HIGH_TABLES_SIZE* 1024;
-		printk_spew("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions. */
@@ -267,12 +267,12 @@
 	}
 	assign_resources(&dev->link[0]);
 	
-	printk_spew("Leaving %s.\n", __func__);
+	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
 static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
 {
-	printk_debug("Entering %s.\n", __func__);
+	printk(BIOS_DEBUG, "Entering %s.\n", __func__);
 
 	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 	return max;
@@ -305,7 +305,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In cn400 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In cn400 enable_dev for device %s.\n", dev_path(dev));
 
 	/* Set the operations if it is a special bus type. */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
Index: src/northbridge/via/cn400/vgabios.c
===================================================================
--- src/northbridge/via/cn400/vgabios.c	(revision 5263)
+++ src/northbridge/via/cn400/vgabios.c	(working copy)
@@ -349,17 +349,17 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
         rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
-	printk_debug("VGA BIOS ROM base address: %x\n", rom);
+	printk(BIOS_DEBUG, "VGA BIOS ROM base address: %x\n", rom);
 
 	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -371,13 +371,13 @@
 		buf = (unsigned char *) 0xc0000;
 		if (buf[0]==0x55 && buf[1]==0xAA) {
 			busdevfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 		    	real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else 
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -562,28 +562,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 	
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
 		      eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *) esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *) esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -602,7 +602,7 @@
 				&ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", 
 			    intnumber);
 		break;
 	}
@@ -728,7 +728,7 @@
 			// devfn is an int, so we mask it off. 
 			busdevfn = (dev->bus->secondary << 8)
 				| (dev->path.pci.devfn & 0xff);
-			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			*pebx = busdevfn;
 			retval = 0;
 		} else {
@@ -754,7 +754,7 @@
 		reg = *pedi;
 		dev = dev_find_slot(bus, devfn);
 		if (! dev) {
-			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
 			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 			*peax = PCIBIOS_BADREG;
 			retval = -1;
@@ -788,14 +788,14 @@
 		
 		if (retval) 
 			retval = PCIBIOS_BADREG;
-		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+		printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 		*peax = 0;
 		retval = 0;
 	}
 	break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
 		break;
 	}
 	
Index: src/northbridge/via/cn400/vga.c
===================================================================
--- src/northbridge/via/cn400/vga.c	(revision 5263)
+++ src/northbridge/via/cn400/vga.c	(working copy)
@@ -52,14 +52,14 @@
 #endif
 
 	temp = (0xffffffff - CONFIG_FALLBACK_SIZE - 0xffff);
-	printk_debug("Copying BOCHS BIOS from 0x%08X	to 0xf000\n", temp);
+	printk(BIOS_DEBUG, "Copying BOCHS BIOS from 0x%08X	to 0xf000\n", temp);
 	/*
 	 * Copy BOCHS BIOS from 4G-CONFIG_FALLBACK_SIZE-64k (in flash) to 0xf0000 (in RAM)
 	 * This is for compatibility with the VGA ROM's BIOS callbacks.
 	 */
 	//memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
 	memcpy(0xf0000, temp, 0x10000);
-	printk_debug("Initializing VGA\n");
+	printk(BIOS_DEBUG, "Initializing VGA\n");
 
 	/* Set memory rate to 200 MHz. */
 	outb(0x3d, CRTM_INDEX);
@@ -79,12 +79,12 @@
 	pci_write_config32(dev, 0x10, 0xf0000008);
 	pci_write_config32(dev, 0x14, 0xf4000000);
 
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
 	setup_realmode_idt();
-	printk_debug("DO THE VGA BIOS\n");
+	printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
 	do_vgabios();
 	/* VGA seems to work without this, but crash & burn with it. */
-	// printk_debug("Enable VGA console\n");
+	// printk(BIOS_DEBUG, "Enable VGA console\n");
 	// vga_enable_console();
 
 	/* It's not clear if these need to be programmed before or after
@@ -106,17 +106,17 @@
 	memset(0xf0000, 0, 0x10000);
 
 #ifdef DEBUG_CN400
-	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
+	printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
 	{
-		printk_spew("%02X: ", i*16);
+		printk(BIOS_SPEW, "%02X: ", i*16);
 		for (j = 0; j < 16; j++)
 		{
 			reg8 = pci_read_config8(dev, j+(i*16));
-			printk_spew("%02X ", reg8);
+			printk(BIOS_SPEW, "%02X ", reg8);
 		}
-		printk_spew("\n");
+		printk(BIOS_SPEW, "\n");
 	}
 #endif
 }
Index: src/northbridge/via/vx800/vx800_ide.c
===================================================================
--- src/northbridge/via/vx800/vx800_ide.c	(revision 5263)
+++ src/northbridge/via/vx800/vx800_ide.c	(working copy)
@@ -169,7 +169,7 @@
 	uint8_t enables, Rx89, RxC0;
 	u8 i, data;
 	struct ATA_REG_INIT_TABLE *pEntry;
-	printk_info("ide_init\n");
+	printk(BIOS_INFO, "ide_init\n");
 
 #if 1
 	/*these 3 lines help to keep interl back door for DID VID SUBID untouched */
@@ -207,14 +207,14 @@
 	enables |= 0x02;
 	pci_write_config8(dev, IDE_CS, enables);
 	enables = pci_read_config8(dev, IDE_CS);
-	printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
 
 	/* Enable only compatibility mode. */
 	enables = pci_read_config8(dev, IDE_CONF_II);
 	enables &= ~0xc0;
 	pci_write_config8(dev, IDE_CONF_II, enables);
 	enables = pci_read_config8(dev, IDE_CONF_II);
-	printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
+	printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
 
 	/* Enable prefetch buffers. */
 	enables = pci_read_config8(dev, IDE_CONF_I);
Index: src/northbridge/via/vx800/northbridge.c
===================================================================
--- src/northbridge/via/vx800/northbridge.c	(revision 5263)
+++ src/northbridge/via/vx800/northbridge.c	(working copy)
@@ -126,7 +126,7 @@
 	u32 pci_tolm;
 	u8 reg;
 
-	printk_spew("Entering vx800 pci_domain_set_resources.\n");
+	printk(BIOS_SPEW, "Entering vx800 pci_domain_set_resources.\n");
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -162,7 +162,7 @@
 			    (((rambits << 6) - (4 << reg) -
 			      VIACONFIG_TOP_SM_SIZE_MB) * 1024);
 
-		printk_spew("tomk is 0x%x\n", tomk);
+		printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
 		/* Compute the Top Of Low Memory, in Kb */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {
@@ -206,7 +206,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In VX800 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In VX800 enable_dev for device %s.\n", dev_path(dev));
 
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
Index: src/northbridge/via/vx800/vx800_lpc.c
===================================================================
--- src/northbridge/via/vx800/vx800_lpc.c	(revision 5263)
+++ src/northbridge/via/vx800/vx800_lpc.c	(working copy)
@@ -58,7 +58,7 @@
 
 static void pci_routing_fixup(struct device *dev)
 {
-	printk_info("%s: dev is %p\n", __FUNCTION__, dev);
+	printk(BIOS_INFO, "%s: dev is %p\n", __FUNCTION__, dev);
 
 	/* set up PCI IRQ routing */
 	pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
@@ -66,42 +66,42 @@
 	pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
 
 	/* VGA */
-	printk_info("setting vga\n");
+	printk(BIOS_INFO, "setting vga\n");
 	pci_assign_irqs(0, 0x1, pin_to_irq(vgaPins));
 
 	/* PCI slot */
-	printk_info("setting pci slot\n");
+	printk(BIOS_INFO, "setting pci slot\n");
 	pci_assign_irqs(0, 0x08, pin_to_irq(slotPins));
 
 	/* PCI slot */
-	printk_info("setting USB Device Controller\n");
+	printk(BIOS_INFO, "setting USB Device Controller\n");
 	pci_assign_irqs(0, 0x0b, pin_to_irq(usbdevicePins));
 
 	/* PCI slot */
-	printk_info("setting SDIO Controller\n");
+	printk(BIOS_INFO, "setting SDIO Controller\n");
 	pci_assign_irqs(0, 0x0c, pin_to_irq(sdioPins));
 
 	/* PCI slot */
-	printk_info("setting SD $ MS Controller\n");
+	printk(BIOS_INFO, "setting SD $ MS Controller\n");
 	pci_assign_irqs(0, 0x0d, pin_to_irq(sd_ms_ctrl_Pins));
 
 	/* PCI slot */
-	printk_info("setting CE-ATA NF Controller(Card Boot)\n");
+	printk(BIOS_INFO, "setting CE-ATA NF Controller(Card Boot)\n");
 	pci_assign_irqs(0, 0x0e, pin_to_irq(ce_ata_nf_ctrl_Pins));
 
 	/* PCI slot */
-	printk_info("setting ide\n");
+	printk(BIOS_INFO, "setting ide\n");
 	//pci_assign_irqs(0, 0x0f, pin_to_irq(idePins));
 
 	/* Standard usb components */
-	printk_info("setting usb1-2\n");
+	printk(BIOS_INFO, "setting usb1-2\n");
 //      pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
 
 	/* sound hardware */
-	printk_info("setting hdac audio\n");
+	printk(BIOS_INFO, "setting hdac audio\n");
 	pci_assign_irqs(0, 0x14, pin_to_irq(hdacaudioPins));
 
-	printk_spew("%s: DONE\n", __FUNCTION__);
+	printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__);
 }
 
 void setup_pm(device_t dev)
@@ -335,7 +335,7 @@
 
 static void southbridge_init(struct device *dev)
 {
-	printk_debug("vx800 sb init\n");
+	printk(BIOS_DEBUG, "vx800 sb init\n");
 	vx800_sb_init(dev);
 	pci_routing_fixup(dev);
 
@@ -343,8 +343,7 @@
 
 	/* turn on keyboard and RTC, no need to visit this reg twice */
 	pc_keyboard_init(0);
-	printk_debug
-	    ("ps2 usb lid, you  set who can wakeup system from s3 sleep\n");
+	printk(BIOS_DEBUG, "ps2 usb lid, you  set who can wakeup system from s3 sleep\n");
 	S3_ps2_kb_ms_wakeup(dev);
 	S3_usb_wakeup(dev);
 
Index: src/northbridge/via/vx800/vga.c
===================================================================
--- src/northbridge/via/vx800/vga.c	(revision 5263)
+++ src/northbridge/via/vx800/vga.c	(working copy)
@@ -53,7 +53,7 @@
 {
 	device_t dev;
 
-	printk_info("write_protect_vgabios\n");
+	printk(BIOS_INFO, "write_protect_vgabios\n");
 	/* there are two possible devices. Just do both. */
 	dev = dev_find_device(PCI_VENDOR_ID_VIA,
 			      PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
@@ -85,16 +85,16 @@
 	pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14);
 	pci_write_config8(dev, 0x3c, 0x0a);	//same with vx855_lpc.c
 	//*/
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 #if 1
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
 	setup_realmode_idt();
-	printk_debug("DO THE VGA BIOS\n");
+	printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
 
 	do_vgabios();
 	if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
-		printk_debug("Enable VGA console\n");
+		printk(BIOS_DEBUG, "Enable VGA console\n");
 		// remove this function since in cn700 it is said "VGA seems to work without this, but crash & burn with it"
 		//but the existense of  vga_enable_console()  seems do not hurt my coreboot. XP+ubuntu s3 can resume with and without this function.
 		//and remove it also do not help my s3 problem: desktop screen have some thin black line, after resuming back to win.
@@ -102,7 +102,7 @@
 	}
 #else
 /* Attempt to manually force the rom to load */
-	printk_debug("Forcing rom load\r\n");
+	printk(BIOS_DEBUG, "Forcing rom load\r\n");
 	pci_rom_load(dev, 0xfff80000);
 	run_bios(dev, 0xc0000);
 #endif
@@ -122,7 +122,7 @@
 		   outb(0x39, SR_INDEX);
 		   outb(reg8, SR_DATA); */
 	}
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 }
 
Index: src/northbridge/via/vx800/vgabios.c
===================================================================
--- src/northbridge/via/vx800/vgabios.c	(revision 5263)
+++ src/northbridge/via/vx800/vgabios.c	(working copy)
@@ -302,7 +302,7 @@
 	u16 tmp;
 	u8 tmp8;
 
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	/* clear vga bios data area */
 	for (i = 0x400; i < 0x500; i++) {
@@ -312,24 +312,24 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
         rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
-	printk_debug("rom base: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base: %x\n", rom);
 	buf = (unsigned char *)rom;
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
 		memcpy((void *)0xc0000, buf, size);
 
-		printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+		printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 		write_protect_vgabios();	// in northbridge
 
@@ -338,14 +338,14 @@
 		if (buf[0] == 0x55 && buf[1] == 0xAA) {
 			busdevfn =
 			    (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 			real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -513,12 +513,12 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
 		     eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
@@ -527,16 +527,16 @@
 	case 6: case 7: case 8: case 9: case 10:
 	case 11: case 12: case 13: case 14: case 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *)esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *)esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/)	// add this to keep same with kevin's seabios patch in 2008-9-8
 			vga_exit();
@@ -556,7 +556,7 @@
 				  &ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", intnumber);
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", intnumber);
 		break;
 	}
 	if (ret)
@@ -686,7 +686,7 @@
 				// devfn is an int, so we mask it off. 
 				busdevfn = (dev->bus->secondary << 8)
 				    | (dev->path.pci.devfn & 0xff);
-				printk_debug("0x%x: return 0x%x\n", func,
+				printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
 					     busdevfn);
 				*pebx = busdevfn;
 				retval = 0;
@@ -713,8 +713,7 @@
 			reg = *pedi;
 			dev = dev_find_slot(bus, devfn);
 			if (!dev) {
-				printk_debug
-				    ("0x%x: BAD DEVICE bus %d devfn 0x%x\n",
+				printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n",
 				     func, bus, devfn);
 				// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 				*peax = PCIBIOS_BADREG;
@@ -749,15 +748,14 @@
 
 			if (retval)
 				retval = PCIBIOS_BADREG;
-			printk_debug
-			    ("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+			printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 			*peax = 0;
 			retval = 0;
 		}
 		break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
 		break;
 	}
 
Index: src/northbridge/via/vx800/examples/romstage.c
===================================================================
--- src/northbridge/via/vx800/examples/romstage.c	(revision 5263)
+++ src/northbridge/via/vx800/examples/romstage.c	(working copy)
@@ -574,7 +574,7 @@
 		__asm__ volatile ("movl   %%esp, %0\n\t":"=a" (v_esp)
 		    );
 #if CONFIG_USE_INIT
-		printk_debug("v_esp=%08x\r\n", v_esp);
+		printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
 #else
 		print_debug("v_esp=");
 		print_debug_hex32(v_esp);
@@ -590,7 +590,7 @@
 //stack
 	cpu_reset = 0;
 #if CONFIG_USE_INIT
-	printk_debug("cpu_reset = %08x\r\n", cpu_reset);
+	printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
 #else
 	print_debug("cpu_reset = ");
 	print_debug_hex32(cpu_reset);
@@ -642,7 +642,7 @@
 			print_debug("Use Ram as Stack now - \r\n");
 		}
 #if CONFIG_USE_INIT
-		printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+		printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
 #else
 		print_debug("new_cpu_reset = ");
 		print_debug_hex32(new_cpu_reset);
Index: src/northbridge/via/vx800/examples/chipset_init.c
===================================================================
--- src/northbridge/via/vx800/examples/chipset_init.c	(revision 5263)
+++ src/northbridge/via/vx800/examples/chipset_init.c	(working copy)
@@ -261,7 +261,7 @@
 
 	// Get SB Revision
 	sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
-	printk_debug("SB chip revision =%x\n", sbchiprev);
+	printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev);
 
 	// Fill Register Table
 	via_pci_inittable(sbchiprev, mSbStage1InitTbl);
@@ -279,7 +279,7 @@
 	u32 subid = 0;
 	rawdevice = PCI_RAWDEV(0, 0, 4);
 	nbchiprev = pci_rawread_config8(rawdevice, 0xf6);
-	printk_debug("NB chip revision =%x\n", nbchiprev);
+	printk(BIOS_DEBUG, "NB chip revision =%x\n", nbchiprev);
 
 	via_pci_inittable(nbchiprev, mNbStage2InitTable);
 
@@ -414,7 +414,7 @@
 		// Get Chipset Revision
 		EHCIRevision =
 		    pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6);
-		printk_debug("EHCI Revision =%x\n", EHCIRevision);
+		printk(BIOS_DEBUG, "EHCI Revision =%x\n", EHCIRevision);
 		via_pci_inittable(EHCIRevision, mEHCIInitTable);
 	}
 }
@@ -567,7 +567,7 @@
 
 	rawdevice = PCI_RAWDEV(0, 11, 0);
 	sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
-	printk_debug("SB chip revision =%x\n", sbchiprev);
+	printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev);
 
 	//SBBasicInit
 	via_pci_inittable(sbchiprev, mBusControllerInitTable);
@@ -592,7 +592,7 @@
 
 void init_VIA_chipset(void)
 {
-	printk_debug("In: init_VIA_chipset\n");
+	printk(BIOS_DEBUG, "In: init_VIA_chipset\n");
 	//1.nbstage1 is done in raminit.
 	//2.sbstage1
 	AcpiInit();
@@ -604,7 +604,7 @@
 
 	//5.open hdac
 	pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04);
-	printk_debug("End: init_VIA_chipset\n");
+	printk(BIOS_DEBUG, "End: init_VIA_chipset\n");
 }
 
 /**
@@ -630,7 +630,7 @@
 
 	u8 y, x;
 	init_VIA_chipset();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 #if 0
 
@@ -653,90 +653,90 @@
 	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
 	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
 
-	printk_info("=================SB 50h=%02x \n",
+	printk(BIOS_INFO, "=================SB 50h=%02x \n",
 		    pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
 
 
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
 	post_code(0x66);
 	/* Now compute and assign the bus resources. */
 	dev_configure();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
 	post_code(0x88);
 	/* Now actually enable devices on the bus */
 	dev_enable();
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 	/* And of course initialize devices on the bus */
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
 	dev_initialize();
 	post_code(0x89);
-	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+	printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
 
 
 //          pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
 
 #if 0
 	x = y = 0;
-	printk_info("dump ehci3 \n");
+	printk(BIOS_INFO, "dump ehci3 \n");
 	for (; x < 16; x++) {
 		y = 0;
 		for (; y < 16; y++) {
-			printk_info("%02x ",
+			printk(BIOS_INFO, "%02x ",
 				    pci_rawread_config8(PCI_RAWDEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
@@ -1265,25 +1265,25 @@
 
 #if 1
 	struct device *dev;
-	printk_info("=========zjldump all  devices...\n");
+	printk(BIOS_INFO, "=========zjldump all  devices...\n");
 	for (dev = all_devices; dev; dev = dev->next) {
 		if (dev->path.type == DEVICE_PATH_PCI) {
-			printk_debug("%s dump\n", dev_path(dev));
+			printk(BIOS_DEBUG, "%s dump\n", dev_path(dev));
 			x = y = 0;
 			for (; x < 16; x++) {
 				y = 0;
 				for (; y < 16; y++) {
-					printk_info("%02x ",
+					printk(BIOS_INFO, "%02x ",
 						    pci_read_config8(dev,
 								     x *
 								     16 +
 								     y));
 				}
-				printk_info("\n");
+				printk(BIOS_INFO, "\n");
 			}
 
 		}
-		printk_info("\n");
+		printk(BIOS_INFO, "\n");
 	}
 #endif
 
Index: src/northbridge/via/cn700/agp.c
===================================================================
--- src/northbridge/via/cn700/agp.c	(revision 5263)
+++ src/northbridge/via/cn700/agp.c	(working copy)
@@ -34,7 +34,7 @@
 	u32 reg32;
 
 	/* Some of this may not be necessary (should be handled by the OS). */
-	printk_debug("Enabling AGP.\n");
+	printk(BIOS_DEBUG, "Enabling AGP.\n");
 
 	/* Allow R/W access to AGP registers. */
 	pci_write_config8(dev, 0x4d, 0x15);
@@ -124,7 +124,7 @@
  */
 static void agp_bridge_init(device_t dev)
 {
-	printk_debug("Setting up AGP bridge device\n");
+	printk(BIOS_DEBUG, "Setting up AGP bridge device\n");
 
 	pci_write_config16(dev, 0x4, 0x0007);
 
Index: src/northbridge/via/cn700/northbridge.c
===================================================================
--- src/northbridge/via/cn700/northbridge.c	(revision 5263)
+++ src/northbridge/via/cn700/northbridge.c	(working copy)
@@ -155,7 +155,7 @@
 	device_t mc_dev;
 	u32 pci_tolm;
 
-	printk_spew("Entering cn700 pci_domain_set_resources.\n");
+	printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
 
 	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -177,7 +177,7 @@
 		}
 
 		tomk = rambits * 64 * 1024;
-		printk_spew("tomk is 0x%x\n", tomk);
+		printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
 		/* Compute the Top Of Low Memory (TOLM), in Kb. */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {
@@ -188,7 +188,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 		high_tables_base = (tolmk - CONFIG_VIDEO_MB * 1024 - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = HIGH_TABLES_SIZE * 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions. */
@@ -229,7 +229,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In cn700 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In cn700 enable_dev for device %s.\n", dev_path(dev));
 
 	/* Set the operations if it is a special bus type. */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
Index: src/northbridge/via/cn700/vgabios.c
===================================================================
--- src/northbridge/via/cn700/vgabios.c	(revision 5263)
+++ src/northbridge/via/cn700/vgabios.c	(working copy)
@@ -349,17 +349,17 @@
 	dev = dev_find_class(PCI_CLASS_DISPLAY_VGA<<8 , 0);
 
 	if (!dev) {
-		printk_debug("NO VGA FOUND\n");
+		printk(BIOS_DEBUG, "NO VGA FOUND\n");
 		return;
 	}
-	printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
+	printk(BIOS_DEBUG, "found VGA: vid=%x, did=%x\n", dev->vendor, dev->device);
 
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
 	rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
-	printk_debug("rom base, size: %x\n", rom);
+	printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
 
 	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -371,13 +371,13 @@
 		buf = (unsigned char *) 0xc0000;
 		if (buf[0]==0x55 && buf[1]==0xAA) {
 			busdevfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
-			printk_debug("bus/devfn = %#x\n", busdevfn);
+			printk(BIOS_DEBUG, "bus/devfn = %#x\n", busdevfn);
 
 		    	real_mode_switch_call_vga(busdevfn);
 		} else
-			printk_debug("Failed to copy VGA BIOS to 0xc0000\n");
+			printk(BIOS_DEBUG, "Failed to copy VGA BIOS to 0xc0000\n");
 	} else 
-		printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
+		printk(BIOS_DEBUG, "BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]);
 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, 0);
 }
@@ -562,28 +562,28 @@
 	cs = cs_ip >> 16;
 	flags = stackflags;
 	
-	printk_debug("biosint: INT# 0x%lx\n", intnumber);
-	printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
+	printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
+	printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", 
 		      eax, ebx, ecx, edx);
-	printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
+	printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
 		     ebp, esp, edi, esi);
-	printk_debug("biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
+	printk(BIOS_DEBUG, "biosint:  ip 0x%x   cs 0x%x  flags 0x%x\n",
 		     ip, cs, flags);
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
 	case 0 ... 15:
 		// These are not BIOS service, but the CPU-generated exceptions
-		printk_info("biosint: Oops, exception %u\n", intnumber);
+		printk(BIOS_INFO, "biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
-			printk_debug("Stack contents: ");
+			printk(BIOS_DEBUG, "Stack contents: ");
 			while (esp < 0x1000) {
-				printk_debug("0x%04x ", *(unsigned short *) esp);
+				printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *) esp);
 				esp += 2;
 			}
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
-		printk_debug("biosint: Bailing out\n");
+		printk(BIOS_DEBUG, "biosint: Bailing out\n");
 		// "longjmp"
 		vga_exit();
 		break;
@@ -602,7 +602,7 @@
 				&ebx, &edx, &ecx, &eax, &flags);
 		break;
 	default:
-		printk_info("BIOSINT: Unsupport int #0x%x\n", 
+		printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%x\n", 
 			    intnumber);
 		break;
 	}
@@ -728,7 +728,7 @@
 			// devfn is an int, so we mask it off. 
 			busdevfn = (dev->bus->secondary << 8)
 				| (dev->path.pci.devfn & 0xff);
-			printk_debug("0x%x: return 0x%x\n", func, busdevfn);
+			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			*pebx = busdevfn;
 			retval = 0;
 		} else {
@@ -754,7 +754,7 @@
 		reg = *pedi;
 		dev = dev_find_slot(bus, devfn);
 		if (! dev) {
-			printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
+			printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
 			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 			*peax = PCIBIOS_BADREG;
 			retval = -1;
@@ -788,14 +788,14 @@
 		
 		if (retval) 
 			retval = PCIBIOS_BADREG;
-		printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
+		printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
 			     func, bus, devfn, reg, *pecx);
 		*peax = 0;
 		retval = 0;
 	}
 	break;
 	default:
-		printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
 		break;
 	}
 	
Index: src/northbridge/via/cn700/vga.c
===================================================================
--- src/northbridge/via/cn700/vga.c	(revision 5263)
+++ src/northbridge/via/cn700/vga.c	(working copy)
@@ -54,7 +54,7 @@
 	 */
 	memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
 
-	printk_debug("Initializing VGA\n");
+	printk(BIOS_DEBUG, "Initializing VGA\n");
 
 	/* Set memory rate to 200 MHz. */
 	outb(0x3d, CRTM_INDEX);
@@ -74,12 +74,12 @@
 	pci_write_config32(dev, 0x10, 0xf4000008);
 	pci_write_config32(dev, 0x14, 0xfb000000);
 
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
 	setup_realmode_idt();
-	printk_debug("DO THE VGA BIOS\n");
+	printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
 	do_vgabios();
 	/* VGA seems to work without this, but crash & burn with it. */
-	// printk_debug("Enable VGA console\n");
+	// printk(BIOS_DEBUG, "Enable VGA console\n");
 	// vga_enable_console();
 
 	/* It's not clear if these need to be programmed before or after
Index: src/northbridge/via/vt8601/northbridge.c
===================================================================
--- src/northbridge/via/vt8601/northbridge.c	(revision 5263)
+++ src/northbridge/via/vt8601/northbridge.c	(working copy)
@@ -20,7 +20,7 @@
  */
 static void northbridge_init(device_t dev) 
 {
-	printk_spew("VT8601 random fixup ...\n");
+	printk(BIOS_SPEW, "VT8601 random fixup ...\n");
 	pci_write_config8(dev, 0x70, 0xc0);
 	pci_write_config8(dev, 0x71, 0x88);
 	pci_write_config8(dev, 0x72, 0xec);
@@ -117,10 +117,10 @@
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk_err("ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
 					ramregs[i]);
 		}
-		printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 		tomk = rambits*8*1024;
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -133,7 +133,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 		high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = HIGH_TABLES_SIZE* 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions */
Index: src/northbridge/via/vt8623/northbridge.c
===================================================================
--- src/northbridge/via/vt8623/northbridge.c	(revision 5263)
+++ src/northbridge/via/vt8623/northbridge.c	(working copy)
@@ -27,7 +27,7 @@
 	unsigned long fb;
 	unsigned char c;
 
-	printk_debug("VT8623 random fixup ...\n");
+	printk(BIOS_DEBUG, "VT8623 random fixup ...\n");
 	pci_write_config8(dev,  0x0d, 0x08);
 	pci_write_config8(dev,  0x70, 0x82);
 	pci_write_config8(dev,  0x71, 0xc8);
@@ -48,7 +48,7 @@
 		 */
 		//fb = pci_read_config32(dev, 0x10);       /* Base addres of framebuffer */
 		fb = 0xd0000000;
-		printk_debug("Frame buffer at %8x\n",fb);
+		printk(BIOS_DEBUG, "Frame buffer at %8x\n",fb);
 
 		c = pci_read_config8(dev, 0xe1) & 0xf0;  /* size of vga */
 		c |= fb>>28;  /* upper nibble of frame buffer address */
@@ -77,7 +77,7 @@
 
 static void agp_init(device_t dev)
 {
-	printk_debug("VT8623 AGP random fixup ...\n");
+	printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n");
 
 	pci_write_config8(dev, 0x3e, 0x0c);
 	pci_write_config8(dev, 0x40, 0x83);
@@ -107,7 +107,7 @@
 //	unsigned long fb;
 	msr_t clocks1,clocks2,instructions,setup;
 
-	printk_debug("VGA random fixup ...\n");
+	printk(BIOS_DEBUG, "VGA random fixup ...\n");
 	pci_write_config8(dev, 0x04, 0x07);
 	pci_write_config8(dev, 0x0d, 0x20);
 	pci_write_config32(dev,0x10,0xd8000008);
@@ -131,24 +131,24 @@
 	//clocks2 = rdmsr(0x10);
 	//instructions = rdmsr(0xc2);
 	
-	printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
-	printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
-	printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
+	printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
+	printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
+	printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 
 #else
 
 	/* code to make vga init run in real mode - does work but against the current coreboot philosophy */
-	printk_debug("INSTALL REAL-MODE IDT\n");
+	printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
         setup_realmode_idt();
-        printk_debug("DO THE VGA BIOS\n");
+        printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
         do_vgabios();
 
 	//clocks2 = rdmsr(0x10);
 	//instructions = rdmsr(0xc2);
 	
-	//printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
-	//printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
-	//printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
+	//printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
+	//printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
+	//printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 
         vga_enable_console();
 	
@@ -229,7 +229,7 @@
 	device_t mc_dev;
         uint32_t pci_tolm;
 
-	printk_spew("Entering vt8623 pci_domain_set_resources.\n");
+	printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
 
         pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev->link[0].children;
@@ -250,10 +250,10 @@
 			if (reg > rambits)
 				rambits = reg;
 			if (reg < rambits)
-				printk_err("ERROR! register 0x%x is not set!\n", 
+				printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
 					ramregs[i]);
 		}
-		printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
+		printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
 		tomk = rambits*16*1024 - 32768;
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -266,7 +266,7 @@
 #if CONFIG_WRITE_HIGH_TABLES == 1
 		high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 		high_tables_size = HIGH_TABLES_SIZE* 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions */
@@ -304,7 +304,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew("In vt8623 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "In vt8623 enable_dev for device %s.\n", dev_path(dev));
 
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
Index: src/northbridge/amd/gx1/northbridge.c
===================================================================
--- src/northbridge/amd/gx1/northbridge.c	(revision 5263)
+++ src/northbridge/amd/gx1/northbridge.c	(working copy)
@@ -42,11 +42,11 @@
 
 static void northbridge_init(device_t dev) 
 {
-	printk_debug("northbridge: %s()\n", __func__);
+	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
 	
 	optimize_xbus(dev);
 	enable_shadow(dev);
-	printk_spew("Calling enable_cache()\n");
+	printk(BIOS_SPEW, "Calling enable_cache()\n");
 	enable_cache();
 }
 
@@ -140,10 +140,10 @@
 		*bcdramtop = ((tomk << 10) - 1);
 		*mcgbaseadd = (tomk >> 9);
 
-		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
-		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+		printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 
-		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+		printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -176,7 +176,7 @@
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+	printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 	initialize_cpus(&dev->link[0]);
 }
 
@@ -194,18 +194,18 @@
 
 static void enable_dev(struct device *dev)
 {
-        printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+        printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
-        	printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
                 dev->ops = &pci_domain_ops;
 		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-        	printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         } else {
-        	printk_spew("device path type %d\n",dev->path.type);
+        	printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
 	}
 }
 
Index: src/northbridge/amd/gx2/chipsetinit.c
===================================================================
--- src/northbridge/amd/gx2/chipsetinit.c	(revision 5263)
+++ src/northbridge/amd/gx2/chipsetinit.c	(working copy)
@@ -87,7 +87,7 @@
 	msr_t msr;
 	msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
 	msr.lo >>= 20;
-	printk_debug("is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
+	printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
 	return ((msr.lo&0xf) == 5);
 }
 /* ***************************************************************************/
@@ -205,10 +205,10 @@
 	int i;
 	int numEnabled = 0;
 
-	printk_debug("ChipsetFlashSetup++\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup++\n");
 	for (i = 0; i < FlashInitTableLen; i++) {
 		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
-			printk_debug("Enable CS%d\n", i);
+			printk(BIOS_DEBUG, "Enable CS%d\n", i);
 			/* we need to configure the memory/IO mask */
 			msr = rdmsr(FlashPort[i]);
 			msr.hi = 0;	/* start with the "enabled" bit clear */
@@ -221,13 +221,13 @@
 			else
 				msr.hi &= ~0x00000004;
 			msr.hi |= FlashInitTable[i].fMask;
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
 			wrmsr(FlashPort[i], msr);
 
 			/* now write-enable the device */
 			msr = rdmsr(MDD_NORF_CNTRL);
 			msr.lo |= (1 << i);
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
 			wrmsr(MDD_NORF_CNTRL, msr);
 
 			/* update the number enabled */
@@ -239,10 +239,10 @@
 	if (0 != numEnabled) {
 		msr = rdmsr(MDD_PIN_OPT);
 		msr.lo &= ~1; /* PIN_OPT_IDE */
-		printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
 		wrmsr(MDD_PIN_OPT, msr);
 	}
-	printk_debug("ChipsetFlashSetup--\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup--\n");
 
 }
 
@@ -359,7 +359,7 @@
 
 
 	/*  Flash Setup*/
-	printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
+	printk(BIOS_ERR, "%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
 	if (nb->setupflash)
 		ChipsetFlashSetup();
 
Index: src/northbridge/amd/gx2/northbridge.c
===================================================================
--- src/northbridge/amd/gx2/northbridge.c	(revision 5263)
+++ src/northbridge/amd/gx2/northbridge.c	(working copy)
@@ -32,7 +32,7 @@
 	unsigned short dimm;
 
 	msr = rdmsr(0x20000018);
-	printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
 
 	/* dimm 0 */
 	dimm = msr.hi;
@@ -47,7 +47,7 @@
 	if ((dimm & 7) != 7)
 		sizem += (1 << ((dimm >> 12)-1)) * 8;
 
-	printk_debug("sizeram: sizem 0x%x\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem);
 	return sizem;
 }
 
@@ -127,7 +127,7 @@
 	/* Set up IRQ steering */
 	uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
 
-	printk_debug("%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
+	printk(BIOS_DEBUG, "%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
 
 	/* The IRQ steering values (in hex) are effectively dcba, where:
 	 *    <a> represents the IRQ for INTA, 
@@ -160,7 +160,7 @@
 	int sizekbytes, sizereg;
 
 	sizekbytes = sizeram() * 1024;
-	printk_debug("setup_gx2_cache: enable for %d KB\n", sizekbytes);
+	printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes);
 	/* build up the rconf word. */
 	/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
 	/* set romrp */
@@ -181,7 +181,7 @@
 	val |= RAM_PROPERTIES;
 	msr.lo = val;
 	msr.hi = (val >> 32);
-	printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
 	wrmsr(CPU_RCONF_DEFAULT, msr);
 
 	enable_cache();
@@ -214,7 +214,7 @@
 
 #if 0
 	/* This has already been done elsewhere */
-	printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
+	printk(BIOS_DEBUG, "size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
 	msr.hi = 0x20000000 | membytes>>24;
 	msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
 	wrmsr(0x10000028, msr);
@@ -224,9 +224,9 @@
 #endif
 #if 0
 	msr = rdmsr(0x10000028);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
 	msr = rdmsr(0x40000029);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
 #endif
 #if 1
 	/* fixme: SMM MSR 0x10000026 and 0x400000023 */
@@ -240,7 +240,7 @@
 	/* calculate the PBASE and PMASK fields */
 	tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20  == left 8 */
 	tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
 	msr.hi = tmp;
 	msr.lo = tmp2;
 	wrmsr(0x10000026, msr);
@@ -251,14 +251,14 @@
 	msr.lo = 0x400fffc0;
 	wrmsr(0x10000026, msr);
 	msr = rdmsr(0x10000026);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
 #endif
 #if 0
 	msr.hi = 0x22fffc02;
 	msr.lo = 0x10ffbf00;
 	wrmsr(0x1808, msr);
 	msr = rdmsr(0x1808);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
 #endif
 #if 0	// SDG - don't do this
 	/* now do the default MSR values */
@@ -266,7 +266,7 @@
 		msr_t msr;
 		wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);	// MSR - see table above
 		msr = rdmsr(msr_defaults[i].msr_no);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
 	}
 #endif
 }
@@ -281,7 +281,7 @@
 	unsigned long m;
 
 	struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
-	printk_debug("northbridge: %s()\n", __func__);
+	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
 	
 	enable_shadow(dev);
 	irq_init_steering(dev, nb->irqmap);
@@ -429,10 +429,10 @@
 		*bcdramtop = ((tomk << 10) - 1);
 		*mcgbaseadd = (tomk >> 9);
 
-		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
-		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+		printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 
-		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+		printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -483,7 +483,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_debug("gx2 north: enable_dev\n");
+	printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
 	void northbridgeinit(void);
 	void chipsetinit(struct northbridge_amd_gx2_config *nb);
 	void do_vsmbios(void);
@@ -492,7 +492,7 @@
 		struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
 		extern void cpubug(void);
 		u32 tomk;
-		printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
+		printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
 		/* cpubug MUST be called before setup_gx2(), so we force the issue here */
 		northbridgeinit();
 		cpubug();	
@@ -510,10 +510,10 @@
 #endif
 		ram_resource(dev, 0, 0, tomk);
         } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-		printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
+		printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         }
-	printk_debug("gx2 north: end enable_dev\n");
+	printk(BIOS_DEBUG, "gx2 north: end enable_dev\n");
 }
 
 struct chip_operations northbridge_amd_gx2_ops = {
Index: src/northbridge/amd/gx2/northbridgeinit.c
===================================================================
--- src/northbridge/amd/gx2/northbridgeinit.c	(revision 5263)
+++ src/northbridge/amd/gx2/northbridgeinit.c	(working copy)
@@ -112,10 +112,10 @@
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 	/* they do this, so we do this */
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void
@@ -147,7 +147,7 @@
 	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk_debug("%s: enable for %dm bytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= SMM_SIZE*1024 +1;
@@ -164,7 +164,7 @@
 	msr.lo = sizebytes;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, 
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, 
 				gl->desc_name, msr.hi, msr.lo);
 	
 }
@@ -177,11 +177,11 @@
 	if (! havedmi)
 		return;
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	sizebytes -= DMM_SIZE*1024;
 	offset = sizebytes - DMM_OFFSET;
-	printk_debug("%s: offset is 0x%08x\n", __func__, offset);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset);
 	offset >>= 12;
 	msr.hi = (gl->hi) | (offset << 8);
 	/* I don't think this is needed */
@@ -192,7 +192,7 @@
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 	
 }
 static void
@@ -202,7 +202,7 @@
 	if (! havedmi)
 		return;
 
-	printk_debug("%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__ );
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -210,12 +210,12 @@
 	msr.hi |= (DMM_OFFSET >> 24);
 	msr.lo = DMM_OFFSET << 8;
 	/* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
-	printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
+	printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
 	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 static void
 SMMGL0Init(struct gliutable *gl) {
@@ -228,10 +228,10 @@
 	if (havedmi)
 		sizebytes -= DMM_SIZE * 1024;
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	offset = sizebytes - SMM_OFFSET;
-	printk_debug("%s: offset is 0x%08x\n", __func__, offset);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset);
 	offset >>= 12;
 
 	msr.hi = offset << 8;
@@ -242,12 +242,12 @@
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 static void
 SMMGL1Init(struct gliutable *gl) {
 	msr_t msr;
-	printk_debug("%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__ );
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -258,7 +258,7 @@
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void
@@ -350,7 +350,7 @@
 		/* So we need a high page aligned addresss (pah) and low page aligned address (pal)
 		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
 		/* we have the page address. Now make it a page-aligned address */
 		pah <<= 12;
@@ -359,7 +359,7 @@
 		msr.hi =  pah;
 		msr.lo =  pal;
 		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
 	}
@@ -507,10 +507,10 @@
 
 	for(i = 0; gating->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(gating->msrnum);
-		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__, 
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__, 
 			gating->msrnum, msr.hi, msr.lo);
 		wrmsr(gating->msrnum, msr);	// MSR - See the table above
 		gating +=1;
@@ -526,11 +526,11 @@
 
 	for(i = 0; prio->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(prio->msrnum);
-		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, 
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, 
 			prio->msrnum, msr.hi, msr.lo);
 		wrmsr(prio->msrnum, msr);	// MSR - See the table above
 		prio +=1;
@@ -772,7 +772,7 @@
 {
 	msr_t msr;
 	int i;
-	printk_debug("Enter %s\n", __func__);
+	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for(i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
@@ -803,6 +803,6 @@
 	ClockGatingInit();
 	__asm__("FINIT\n");
 	/* CPUBugsFix -- called elsewhere */
-	printk_debug("Exit %s\n", __func__);
+	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }
 
Index: src/northbridge/amd/lx/grphinit.c
===================================================================
--- src/northbridge/amd/lx/grphinit.c	(revision 5263)
+++ src/northbridge/amd/lx/grphinit.c	(working copy)
@@ -70,7 +70,7 @@
 	uint16_t wClassIndex, wData, res;
 
 	/* SoftVG initialization */
-	printk_debug("Graphics init...\n");
+	printk(BIOS_DEBUG, "Graphics init...\n");
    
 	geodelx_vga_msr_init();
    
@@ -99,5 +99,5 @@
 	vrWrite(wClassIndex, wData);
 
 	res = vrRead(wClassIndex);
-	printk_debug("VRC_VG value: 0x%04x\n", res);
+	printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
 }
Index: src/northbridge/amd/lx/northbridge.c
===================================================================
--- src/northbridge/amd/lx/northbridge.c	(revision 5263)
+++ src/northbridge/amd/lx/northbridge.c	(working copy)
@@ -173,96 +173,96 @@
 		MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
 	};
 
-	printk_debug("---------- CPU ------------\n");
+	printk(BIOS_DEBUG, "---------- CPU ------------\n");
 
 	for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(cpu_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     cpu_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 0 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
 
 	for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu0_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu0_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 1 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
 
 	for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu1_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu1_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- RCONF ------------\n");
+	printk(BIOS_DEBUG, "---------- RCONF ------------\n");
 
 	for (i = 0; rconf_msr[i] != GL_END; i++) {
 		msr = rdmsr(rconf_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- VARIA ------------\n");
+	printk(BIOS_DEBUG, "---------- VARIA ------------\n");
 	msr = rdmsr(0x51300010);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
 		     msr.lo);
 
 	msr = rdmsr(0x51400015);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
 		     msr.lo);
 
-	printk_debug("---------- DIVIL IRQ ------------\n");
+	printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
 	msr = rdmsr(MDD_IRQM_YLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_YHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
 		     msr.hi, msr.lo);
 	msr = rdmsr(MDD_IRQM_ZLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_ZHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
 		     msr.hi, msr.lo);
 
-	printk_debug("---------- PCI ------------\n");
+	printk(BIOS_DEBUG, "---------- PCI ------------\n");
 
 	for (i = 0; pci_msr[i] != GL_END; i++) {
 		msr = rdmsr(pci_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- LPC/UART DMA ------------\n");
+	printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
 
 	for (i = 0; dma_msr[i] != GL_END; i++) {
 		msr = rdmsr(dma_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- CS5536 ------------\n");
+	printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
 
 	for (i = 0; cs5536_msr[i] != GL_END; i++) {
 		msr = rdmsr(cs5536_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
 			     msr.hi, msr.lo);
 	}
 
 	iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
 	iol = inl(GPIOL_EVENTS_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
 	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
 	iol = inl(GPIO_MAPPER_X);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
 		     iol);
 #endif				//CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
 }
@@ -278,7 +278,7 @@
 
 	/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
 	msr = rdmsr(MC_CF07_DATA);
-	printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
 
 	/* dimm 0 */
 	dimm = msr.hi;
@@ -294,7 +294,7 @@
 		sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
 	}
 
-	printk_debug("sizeram: sizem 0x%xMB\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
 	return sizem;
 }
 
@@ -306,7 +306,7 @@
 {
 	//msr_t msr;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	enable_shadow(dev);
 	/*
@@ -317,8 +317,8 @@
 	//msr.hi |= 0x3;
 	//msr.lo |= 0x30000;
 
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
 }
 
 void northbridge_set_resources(struct device *dev)
@@ -340,8 +340,7 @@
 		struct bus *bus;
 		bus = &dev->link[link];
 		if (bus->children) {
-			printk_debug
-			    ("my_dev_set_resources: assign_resources %d\n",
+			printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
 			     bus);
 			assign_resources(bus);
 		}
@@ -406,7 +405,7 @@
 	u32 tomk;
 	device_t mc_dev;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
@@ -430,7 +429,7 @@
 static void pci_domain_enable(device_t dev)
 {
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	// do this here for now -- this chip really breaks our device model
 	northbridge_init_early();
@@ -439,12 +438,12 @@
 
 	setup_realmode_idt();
 
-	printk_debug("Before VSA:\n");
+	printk(BIOS_DEBUG, "Before VSA:\n");
 	// print_conf();
 
 	do_vsmbios();		// do the magic stuff here, so prepare your tambourine ;)
 
-	printk_debug("After VSA:\n");
+	printk(BIOS_DEBUG, "After VSA:\n");
 	// print_conf();
 
 	graphics_init();
@@ -461,7 +460,7 @@
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	initialize_cpus(&dev->link[0]);
 }
@@ -480,7 +479,7 @@
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew(">> Entering northbridge.c: %s with path %d\n",
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
 		    __func__, dev->path.type);
 
 	/* Set the operations if it is a special bus type */
Index: src/northbridge/amd/lx/northbridgeinit.c
===================================================================
--- src/northbridge/amd/lx/northbridgeinit.c	(revision 5263)
+++ src/northbridge/amd/lx/northbridgeinit.c	(working copy)
@@ -107,7 +107,7 @@
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
 }
 
 static void ShadowInit(struct gliutable *gl)
@@ -131,11 +131,11 @@
 	 * system. We will adjust for SMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk_debug("%s: enable for %dMBytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= ((SMM_SIZE * 1024) + 1);
-	printk_debug("usable RAM: %d bytes\n", sizebytes);
+	printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);
 
 	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
 	   The top 8 bits go into 0-7 of msr.hi. */
@@ -147,7 +147,7 @@
 	msr.lo = sizebytes;
 
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -159,12 +159,12 @@
 
 	sizebytes -= (SMM_SIZE * 1024);
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	/* calculate the Two's complement offset */
 	offset = sizebytes - SMM_OFFSET;
 	offset = (offset >> 12) & 0x000fffff;
-	printk_debug("%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
 
 	msr.hi = offset << 8 | gl->hi;
 	msr.hi |= SMM_OFFSET >> 24;
@@ -173,14 +173,14 @@
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
 static void SMMGL1Init(struct gliutable *gl)
 {
 	msr_t msr;
-	printk_debug("%s:\n", __func__);
+	printk(BIOS_DEBUG, "%s:\n", __func__);
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -190,7 +190,7 @@
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -290,7 +290,7 @@
 		msr.lo |=
 		    GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
 		    GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
+		printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
 			     msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
@@ -304,7 +304,7 @@
 	      (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
 	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
-	printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
+	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
 		     msr.hi);
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
@@ -435,7 +435,7 @@
 		msr = rdmsr(gating->msrnum);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
 		   gating->msrnum, msr.hi, msr.lo); */// GX3
 		wrmsr(gating->msrnum, msr);	// MSR - See the table above
 		gating += 1;
@@ -454,7 +454,7 @@
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
 		   prio->msrnum, msr.hi, msr.lo);  */// GX3
 		wrmsr(prio->msrnum, msr);	// MSR - See the table above
 		prio += 1;
@@ -651,7 +651,7 @@
 
 	// now program RCONF_DEFAULT
 	wrmsr(CPU_RCONF_DEFAULT, msr);
-	printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
 		     msr.lo);
 
 	// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
@@ -663,7 +663,7 @@
 	    (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
 	wrmsr(CPU_RCONF_BYPASS, msr);
 
-	printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
 		     msr.lo);
 }
 
@@ -695,7 +695,7 @@
 	msr.lo = 0x0f;
 	wrmsr(CPU_BC_L2_CONF, msr);
 
-	printk_debug("L2 cache enabled\n");
+	printk(BIOS_DEBUG, "L2 cache enabled\n");
 }
 
 static void setup_lx_cache(void)
@@ -748,7 +748,7 @@
 void northbridge_init_early(void)
 {
 	int i;
-	printk_debug("Enter %s\n", __func__);
+	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
@@ -768,5 +768,5 @@
 	ClockGatingInit();
 
 	__asm__ __volatile__("FINIT\n");
-	printk_debug("Exit %s\n", __func__);
+	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }
Index: src/northbridge/amd/amdk8/get_sblk_pci1234.c
===================================================================
--- src/northbridge/amd/amdk8/get_sblk_pci1234.c	(revision 5263)
+++ src/northbridge/amd/amdk8/get_sblk_pci1234.c	(working copy)
@@ -55,7 +55,7 @@
 		dst_link = (config_map >> 8) & 3;
 		bus_base = (config_map >> 16) & 0xff;
 #if 0
-		printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+		printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
 			dst_node, dst_link, bus_base,
 			reg, config_map);
 #endif
Index: src/northbridge/amd/amdk8/amdk8_acpi.c
===================================================================
--- src/northbridge/amd/amdk8/amdk8_acpi.c	(revision 5263)
+++ src/northbridge/amd/amdk8/amdk8_acpi.c	(working copy)
@@ -81,7 +81,7 @@
 		if (!cpu->enabled) {
 			continue;
 		}
-		printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+		printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		cpu_index++;
 	}
@@ -110,7 +110,7 @@
 	basek = resk(res->base);
 	sizek = resk(res->size);
 
-	printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
+	printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
 		     dev_path(dev), res->index, basek, sizek);
 	/*
 	 * 0-640K must be on node 0
Index: src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/coherent_ht.c	(revision 5263)
+++ src/northbridge/amd/amdk8/coherent_ht.c	(working copy)
@@ -111,7 +111,7 @@
 
 static inline void print_linkn (const char *strval, uint8_t byteval)
 {
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
 }
 
 static void disable_probes(void)
@@ -1496,7 +1496,7 @@
 		nodes = setup_smp8();
 #endif
 
-	printk_debug("%02x nodes initialized.\r\n", nodes);
+	printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes);
 
 	return nodes;
 }
Index: src/northbridge/amd/amdk8/raminit.c
===================================================================
--- src/northbridge/amd/amdk8/raminit.c	(revision 5263)
+++ src/northbridge/amd/amdk8/raminit.c	(working copy)
@@ -25,7 +25,7 @@
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
-//	printk_debug("setting up resource map....");
+//	printk(BIOS_DEBUG, "setting up resource map....");
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
@@ -37,7 +37,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-//	printk_debug("done.\n");
+//	printk(BIOS_DEBUG, "done.\n");
 }
 
 static int controller_present(const struct mem_controller *ctrl)
@@ -524,10 +524,10 @@
 	int max;
 
 	if (!controller_present(ctrl)) {
-//		printk_debug("No memory controller present\n");
+//		printk(BIOS_DEBUG, "No memory controller present\n");
 		return;
 	}
-	printk_spew("setting up CPU%02x northbridge registers\n", ctrl->node_id);
+	printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id);
 	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
@@ -540,7 +540,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	printk_spew("done.\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
 static void hw_enable_ecc(const struct mem_controller *ctrl)
@@ -849,17 +849,17 @@
 	}
 
 	/* Report the amount of memory. */
-	printk_debug("RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
 
 	/* Now set top of memory */
 	msr_t msr;
 	if (tom_k > (4*1024*1024)) {
-		printk_spew("Handling memory mapped above 4 GB\n");
-		printk_spew("Upper RAM end at 0x%08x kB\n", tom_k);
+		printk(BIOS_SPEW, "Handling memory mapped above 4 GB\n");
+		printk(BIOS_SPEW, "Upper RAM end at 0x%08x kB\n", tom_k);
 		msr.lo = (tom_k & 0x003fffff) << 10;
 		msr.hi = (tom_k & 0xffc00000) >> 22;
 		wrmsr(TOP_MEM2, msr);
-		printk_spew("Correcting memory amount mapped below 4 GB\n");
+		printk(BIOS_SPEW, "Correcting memory amount mapped below 4 GB\n");
 	}
 
 	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
@@ -872,9 +872,9 @@
 		} else
 #endif
 		tom_k = 0x3f0000;
-		printk_spew("Adjusting lower RAM end\n");
+		printk(BIOS_SPEW, "Adjusting lower RAM end\n");
 	}
-	printk_spew("Lower RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_SPEW, "Lower RAM end at 0x%08x kB\n", tom_k);
 	msr.lo = (tom_k & 0x003fffff) << 10;
 	msr.hi = (tom_k & 0xffc00000) >> 22;
 	wrmsr(TOP_MEM, msr);
@@ -969,7 +969,7 @@
 		if (is_dual_channel(ctrl)) {
 		/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
 			if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-//     				printk_debug("8 4GB chip selects cannot be interleaved\n");
+//     				printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -979,7 +979,7 @@
 		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
 		if (is_dual_channel(ctrl)) {
 			if ( (bits==3) && (common_cs_mode > 8)) {
-//				printk_debug("8 cs_mode>8 chip selects cannot be interleaved\n");
+//				printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -1006,7 +1006,7 @@
 		csbase += csbase_inc;
 	}
 
-	printk_spew("Interleaved\n");
+	printk(BIOS_SPEW, "Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << (15 + bits);
@@ -1107,7 +1107,7 @@
 	    read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
-		printk_debug("Interleaving disabled\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
 
@@ -1124,7 +1124,7 @@
 
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
 {
-	printk_debug("disabling dimm %02x\n", index);
+	printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
 	dimm_mask &= ~(1 << index);
@@ -1183,9 +1183,9 @@
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
 	if (is_registered(ctrl)) {
-		printk_spew("Registered\n");
+		printk(BIOS_SPEW, "Registered\n");
 	} else {
-		printk_spew("Unbuffered\n");
+		printk(BIOS_SPEW, "Unbuffered\n");
 	}
 
 	return dimm_mask;
@@ -1280,7 +1280,7 @@
 			}
 		}
 	}
-	printk_spew("Enabling dual channel memory\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_32ByteEn;
@@ -1378,7 +1378,7 @@
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	printk_spew("%s\n", param->name);
+	printk(BIOS_SPEW, "%s\n", param->name);
 	return param;
 }
 
@@ -2073,7 +2073,7 @@
 	long dimm_mask;
 #if 1
 	if (!controller_present(ctrl)) {
-//		printk_debug("No memory controller present\n");
+//		printk(BIOS_DEBUG, "No memory controller present\n");
 		return;
 	}
 #endif
@@ -2081,7 +2081,7 @@
 	activate_spd_rom(ctrl);
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk_debug("No memory for this cpu\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
@@ -2105,7 +2105,7 @@
 	return;
  hw_spd_err:
 	/* Unrecoverable error reading SPD data */
-	printk_err("SPD error - reset\n");
+	printk(BIOS_ERR, "SPD error - reset\n");
 	hard_reset();
 	return;
 }
@@ -2171,7 +2171,7 @@
 
 	hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
 
-	printk_spew("Handling memory hole at 0x%08x (default)\n", hole_startk);
+	printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);
 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 	/* We need to double check if hole_startk is valid.
 	 * If it is equal to the dram base address in K (base_k),
@@ -2196,7 +2196,7 @@
 			basek_pri = base_k;
 	}
 
-	printk_spew("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
+	printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
 #endif
 	/* Find node number that needs the memory hole configured */
 	for (i=0; i<controllers; i++) {
@@ -2273,7 +2273,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_128BitEn) {
@@ -2301,17 +2301,17 @@
 			continue;
 		}
 
-		printk_debug("Initializing memory: ");
+		printk(BIOS_DEBUG, "Initializing memory: ");
 		int loops = 0;
 		do {
 			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug(" failed\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -2324,7 +2324,7 @@
 			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
 		}
 
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
Index: src/northbridge/amd/amdk8/setup_resource_map.c
===================================================================
--- src/northbridge/amd/amdk8/setup_resource_map.c	(revision 5263)
+++ src/northbridge/amd/amdk8/setup_resource_map.c	(working copy)
@@ -49,7 +49,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
 			i>>2, register_values[i],
 			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 			register_values[i+2],
@@ -129,7 +129,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
 			i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
 #endif
 		switch (register_values[i]) {
Index: src/northbridge/amd/amdk8/exit_from_self.c
===================================================================
--- src/northbridge/amd/amdk8/exit_from_self.c	(revision 5263)
+++ src/northbridge/amd/amdk8/exit_from_self.c	(working copy)
@@ -43,7 +43,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			u32 mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_Width128) {
@@ -52,7 +52,7 @@
 			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
 		}
 
-		printk_debug("before resume errata #%d\n",
+		printk(BIOS_DEBUG, "before resume errata #%d\n",
 			     (is_post_rev_g) ? 270 : 125);
 		/* 
 		   1. Restore memory controller registers as normal.
@@ -70,7 +70,7 @@
 		enable_lapic();
 		init_timer();
 
-		printk_debug("before exit errata - timer enabled\n");
+		printk(BIOS_DEBUG, "before exit errata - timer enabled\n");
 
 		if (is_post_rev_g) {
 			dcl =
@@ -86,7 +86,7 @@
 
 		udelay(800);
 
-		printk_debug("before exit errata - after mdelay\n");
+		printk(BIOS_DEBUG, "before exit errata - after mdelay\n");
 
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
 		dcl &= ~DI_EnDramInit;
@@ -108,7 +108,7 @@
 		pcidev =
 		    0x80000000 | ((((ctrl[i].node_id + 0x18) << 3) | 0x2)
 				  << 8) | 0x90;
-		printk_debug("pcidev is %x\n", pcidev);
+		printk(BIOS_DEBUG, "pcidev is %x\n", pcidev);
 		bitmask = 2;
 		__asm__ __volatile__("pushl %0\n\t"
 				     "movw $0xcf8, %%dx\n\t"
@@ -125,7 +125,7 @@
 				     "q"(bitmask):"edx");
 	}
 
-	printk_debug("after exit errata\n");
+	printk(BIOS_DEBUG, "after exit errata\n");
 
 
 	for (i = 0; i < controllers; i++) {
@@ -136,12 +136,12 @@
 		if (sysinfo->meminfo[i].dimm_mask == 0x00)
 			continue;
 
-		printk_debug("Exiting memory from self refresh: ");
+		printk(BIOS_DEBUG, "Exiting memory from self refresh: ");
 		int loops = 0;
 		do {
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 			dcm =
 			    pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
@@ -149,11 +149,11 @@
 			  0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
 
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug("timeout with with cntrl[%d]\n", i);
+			printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i);
 			continue;
 		}
 
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
Index: src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- src/northbridge/amd/amdk8/northbridge.c	(revision 5263)
+++ src/northbridge/amd/amdk8/northbridge.c	(working copy)
@@ -395,14 +395,14 @@
 
 	/* Make certain the resource has actually been set */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("%s: can't set unassigned resource @%lx %lx\n",
+		printk(BIOS_ERR, "%s: can't set unassigned resource @%lx %lx\n",
 			   __func__, resource->index, resource->flags);
 		return;
 	}
 
 	/* If I have already stored this resource don't worry about it */
 	if (resource->flags & IORESOURCE_STORED) {
-		printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
+		printk(BIOS_ERR, "%s: can't set stored resource @%lx %lx\n", __func__,
 			   resource->index, resource->flags);
 		return;
 	}
@@ -442,7 +442,7 @@
 		limit |= (nodeid & 7);
 
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-			printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
 				    __func__, dev_path(dev), link);
 			base |= PCI_IO_BASE_VGA_EN;
 		}
@@ -487,7 +487,7 @@
 	for (link = 0; link < dev->links; link++) {
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 				dev->link[link].secondary,dev->link[link].subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@@ -502,12 +502,12 @@
 	if (link == dev->links)
 		return;
 
-	printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 
 	/* allocate a temp resource for the legacy VGA buffer */
 	resource = new_resource(dev, IOINDEX(4, link));
 	if(!resource){
-		printk_debug("VGA: %s out of resources.\n", dev_path(dev));
+		printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
 		return;
 	}
 	resource->base = 0xa0000;
@@ -573,10 +573,10 @@
 static void mcf0_control_init(struct device *dev)
 {
 #if 0
-	printk_debug("NB: Function 0 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
 #endif
 #if 0
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 }
 
@@ -773,7 +773,7 @@
 	f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
 	dev = __f1_dev[node_id];
 	if (dev == NULL) {
-		printk_err("%s: node %x is NULL!\n", __func__, node_id);
+		printk(BIOS_ERR, "%s: node %x is NULL!\n", __func__, node_id);
 		return;
 	}
 	hoist = pci_read_config32(dev, 0xf0);
@@ -869,9 +869,9 @@
 	mem2 = find_resource(dev, 2);
 
 #if 1
-	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem1->base, mem1->limit, mem1->size, mem1->align);
-	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
@@ -899,9 +899,9 @@
 	}
 
 #if 1
-	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem1->base, mem1->limit, mem1->size, mem1->align);
-	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
@@ -1005,11 +1005,11 @@
 
 
 #if CONFIG_GFXUMA == 1
-		printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
+		printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
 		if ((uma_memory_base >> 10) < mmio_basek)
-			printk_alert("node %d: UMA memory starts below mmio_basek\n", i);
+			printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
 #else
-//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
+//		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
 #endif
 
 		/* See if I need to split the region to accomodate pci memory space */
@@ -1030,7 +1030,7 @@
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 #endif
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk_debug(" split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1060,7 +1060,7 @@
 			ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
 #if CONFIG_WRITE_HIGH_TABLES==1
-		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
 		if (i==0 && high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
@@ -1101,7 +1101,7 @@
 			if (!dev->link[0].disable_relaxed_ordering) {
 				httc |= HTTC_RSP_PASS_PW;
 			}
-			printk_spew("%s passpw: %s\n",
+			printk(BIOS_SPEW, "%s passpw: %s\n",
 				dev_path(dev),
 				(!dev->link[0].disable_relaxed_ordering)?
 				"enabled":"disabled");
@@ -1207,7 +1207,7 @@
 		if (cpu_dev && cpu_dev->enabled) {
 			j = pci_read_config32(cpu_dev, 0xe8);
 			j = (j >> 12) & 3; // dev is func 3
-			printk_debug("  %s siblings=%d\n", dev_path(cpu_dev), j);
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cpu_dev), j);
 
 			if(nb_cfg_54) {
 				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
@@ -1224,7 +1224,7 @@
 				       e0_later_single_core = 0;
 	       			}
 				if(e0_later_single_core) {
-					printk_debug("\tFound Rev E or Rev F later single core\r\n");
+					printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
 
 					j=1;
 				}
@@ -1287,7 +1287,7 @@
 						       cpu->path.apic.apic_id += sysconf.apicid_offset;
 					}
 				}
-				printk_debug("CPU: %s %s\n",
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
 					dev_path(cpu), cpu->enabled?"enabled":"disabled");
 			}
 
Index: src/northbridge/amd/amdk8/raminit_f.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_f.c	(revision 5263)
+++ src/northbridge/amd/amdk8/raminit_f.c	(working copy)
@@ -34,7 +34,7 @@
 #endif
 
 #if DEBUG_RAM_SETUP
-#define printk_raminit printk_debug
+#define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
 #define printk_raminit(fmt, arg...)
 #endif
@@ -691,7 +691,7 @@
 	}
 	sysinfo->ctrl_present[ctrl->node_id] = 1;
 
-	printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id);
+	printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id);
 	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
@@ -704,7 +704,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	printk_spew("done.\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
 static int is_dual_channel(const struct mem_controller *ctrl)
@@ -801,7 +801,7 @@
 	if (value <=4 ) value += 8; // add back to 1G to high
 	value += (27-5); // make 128MB to the real lines
 	if ( value != (sz->per_rank)) {
-		printk_err("Bad RANK Size --\n");
+		printk(BIOS_ERR, "Bad RANK Size --\n");
 		goto val_err;
 	}
 
@@ -1041,7 +1041,7 @@
 	}
 
 	/* Report the amount of memory. */
-	printk_debug("RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
 
 	/* Now set top of memory */
 	msr_t msr;
@@ -1175,7 +1175,7 @@
 		csbase += csbase_inc;
 	}
 
-	printk_debug("Interleaved\n");
+	printk(BIOS_DEBUG, "Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << ((27-10) + bits);
@@ -1279,7 +1279,7 @@
 	    CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
 	} else {
-		printk_debug("Interleaving disabled\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
 
@@ -1297,7 +1297,7 @@
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
 			  struct mem_info *meminfo)
 {
-	printk_debug("disabling dimm %02x\n", index);
+	printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
 	if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@@ -1370,9 +1370,9 @@
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
 	if (meminfo->is_registered) {
-		printk_spew("Registered\n");
+		printk(BIOS_SPEW, "Registered\n");
 	} else {
-		printk_spew("Unbuffered\n");
+		printk(BIOS_SPEW, "Unbuffered\n");
 	}
 	return meminfo->dimm_mask;
 }
@@ -1473,7 +1473,7 @@
 		/* Abort if the chips don't support a common CAS latency. */
 		common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
 		if (!common_cl) {
-			printk_debug("No common CAS latency supported\n");
+			printk(BIOS_DEBUG, "No common CAS latency supported\n");
 			goto single_channel;
 		} else {
 			printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
@@ -1495,7 +1495,7 @@
 			}
 		}
 	}
-	printk_spew("Enabling dual channel memory\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_BurstLength32;  /*	32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
 					32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode	*/
@@ -1514,7 +1514,7 @@
 		if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
 			/* mux capable and single dimm in channelB */
 			if (mux_cap) {
-				printk_spew("Enable 64MuxMode & BurstLength32\n");
+				printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
 				dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
 				dcm |= DCM_Mode64BitMux;
 				pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
@@ -1529,7 +1529,7 @@
 	} else { /* unmatched dual dimms ? */
 		/* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
 		meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
-		printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
+		printk(BIOS_SPEW, "Unmatched dual dimms. Use single channelA dimm.\n");
 	}
 	return meminfo->dimm_mask;
 }
@@ -1610,7 +1610,7 @@
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	printk_spew("%s\n", param->name);
+	printk(BIOS_SPEW, "%s\n", param->name);
 	return param;
 }
 
@@ -1912,7 +1912,7 @@
 	value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
 
-	printk_debug("%s\n", result.param->name);
+	printk(BIOS_DEBUG, "%s\n", result.param->name);
 
 	/* Update DRAM Timing Low with our selected cas latency */
 	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
@@ -1960,7 +1960,7 @@
 
 	if (clocks < DTL_TRC_MIN) {
 #warning We should die here or at least disable this bank.
-		printk_notice("update_dimm_Trc: can't refresh fast enough, "
+		printk(BIOS_NOTICE, "update_dimm_Trc: can't refresh fast enough, "
 			"want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
 		clocks = DTL_TRC_MIN;
 	}
@@ -2057,7 +2057,7 @@
 	}
 	
 	if (clocks > TT_MAX) {
-		printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
+		printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
 		clocks = TT_MAX;
 	}
 
@@ -2372,7 +2372,7 @@
 		if (!(meminfo->dimm_mask & (1 << i))) {
 			if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
 				spd_device = ctrl->channel1[i];
-				printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
+				printk(BIOS_DEBUG, "set_ecc spd_device: 0x%x\n", spd_device);
 			} else {
 				continue;
 			}
@@ -2405,7 +2405,7 @@
 	uint32_t reg;
 
 	if ((val < TT_MIN) || (val > TT_MAX)) {
-		printk_err(str);
+		printk(BIOS_ERR, str);
 		die(" Unknown\n");
 	}
 
@@ -2765,7 +2765,7 @@
 
 		continue;
 	dimm_err:
-		printk_debug("spd_set_dram_timing dimm_err!\n");
+		printk(BIOS_DEBUG, "spd_set_dram_timing dimm_err!\n");
 		if (rc < 0) {
 			return -1;
 		}
@@ -2815,7 +2815,7 @@
 #endif
 	meminfo = &sysinfo->meminfo[ctrl->node_id];
 
-	printk_debug("sdram_set_spd_registers: paramx :%p\n", &paramx);
+	printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :%p\n", &paramx);
 
 	activate_spd_rom(ctrl);
 	meminfo->dimm_mask = spd_detect_dimms(ctrl);
@@ -2824,7 +2824,7 @@
 
 	if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
 	{
-		printk_debug("No memory for this cpu\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
@@ -3000,7 +3000,7 @@
 	/* FIXME: How about 32 node machine later? */
 	tsc_t tsc, tsc0[8];
 
-	printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
+	printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]);
 	uint32_t dword;
 #endif
 
@@ -3034,9 +3034,9 @@
 
 	/* lets override the rest of the routine */
 	if (suspend) {
-		printk_debug("Wakeup!\n");
+		printk(BIOS_DEBUG, "Wakeup!\n");
 		exit_from_self(controllers, ctrl, sysinfo);
-		printk_debug("Mem running !\n");
+		printk(BIOS_DEBUG, "Mem running !\n");
 		return;
 	}
 
@@ -3054,7 +3054,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_Width128) {
@@ -3089,17 +3089,17 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("Initializing memory: ");
+		printk(BIOS_DEBUG, "Initializing memory: ");
 		int loops = 0;
 		do {
 			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 		} while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug(" failed\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -3127,7 +3127,7 @@
 			print_debug_dqs_tsc("     dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
 		}
 #endif
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
Index: src/northbridge/amd/amdk8/amdk8_f.h
===================================================================
--- src/northbridge/amd/amdk8/amdk8_f.h	(revision 5263)
+++ src/northbridge/amd/amdk8/amdk8_f.h	(working copy)
@@ -565,7 +565,7 @@
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
 #else
-		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -583,7 +583,7 @@
 		print_debug("mem trained failed\r\n");
 		soft_reset();
 #else
-		printk_debug("mem trained failed\n"); 
+		printk(BIOS_DEBUG, "mem trained failed\n"); 
 		hard_reset();
 #endif
 	}
Index: src/northbridge/amd/amdk8/raminit_f_dqs.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_f_dqs.c	(revision 5263)
+++ src/northbridge/amd/amdk8/raminit_f_dqs.c	(working copy)
@@ -25,7 +25,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%x\r\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\r\n", str, val);
 	}
 #endif
 }
@@ -34,7 +34,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2);
+		printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2);
 	}
 #endif
 }
@@ -43,14 +43,14 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+		printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
 	}
 #endif
 }
 
 static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
 {
-	printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+	printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
 
 }
 
@@ -854,7 +854,7 @@
 
 #if CONFIG_MEM_TRAIN_SEQ != 1
 	/* We need tidy output for type 1 */
-	printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay);
+	printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay);
 #endif
 
 	return (CTLRMaxDelay==0xae)?1:0;
@@ -1130,7 +1130,7 @@
 
 	print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3);
 
-	printk_debug("TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
+	printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
 
 	for(DQSDelay=0; DQSDelay<48; DQSDelay++) {
 		MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS)
@@ -1403,7 +1403,7 @@
 
 	print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
 
-	printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a);
+	printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a);
 
 	Errors = 0;
 	channel = 0;
@@ -1537,7 +1537,7 @@
 {
 	print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
 	if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
-		printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
+		printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
 		return 1;
 	}
 	else {
@@ -1700,7 +1700,7 @@
 		}
 		sizek = 1 << align;
 #if CONFIG_MEM_TRAIN_SEQ != 1
-		printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
+		printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
 			reg, range_startk >>10, sizek >> 10,
 			(type==MTRR_TYPE_UNCACHEABLE)?"UC":
 			    ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -1895,7 +1895,7 @@
 {
 	int pos = 0;
 	u32 reg;
-	printk_debug("DQS SAVE NVRAM: %x\n", dev);
+	printk(BIOS_DEBUG, "DQS SAVE NVRAM: %x\n", dev);
 	pos = dqs_save_MC_NVRAM_ch(dev, 0, pos);
 	pos = dqs_save_MC_NVRAM_ch(dev, 1, pos);
 	/* save the maxasync lat here */
@@ -1908,7 +1908,7 @@
 	int pos = 0;
 	u32 reg;
 
-	printk_debug("DQS RESTORE FROM NVRAM: %x\n", dev);
+	printk(BIOS_DEBUG, "DQS RESTORE FROM NVRAM: %x\n", dev);
 	pos = dqs_load_MC_NVRAM_ch(dev, 0, pos);
 	pos = dqs_load_MC_NVRAM_ch(dev, 1, pos);
 	/* load the maxasync lat here */
@@ -1950,9 +1950,9 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
-       		printk_debug(" done\r\n");
+       		printk(BIOS_DEBUG, " done\r\n");
 	}
 
 	tsc[1] = rdtsc();
@@ -1968,9 +1968,9 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:DQSPos: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
 		if(train_DqsPos(ctrl+i, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 	}
 
 	tsc[3] = rdtsc();
@@ -1981,9 +1981,9 @@
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		sysinfo->mem_trained[i]=1;
 		dqs_save_MC_NVRAM((ctrl+i)->f2);
 	}
@@ -2025,7 +2025,7 @@
 	if(v) {
 		tsc[0] = rdtsc();
 
-		printk_debug("set DQS timing:RcvrEn:Pass1: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass1: %02x\n", i);
 	}
 	if(train_DqsRcvrEn(ctrl, 1,  sysinfo)) {
 		sysinfo->mem_trained[i]=0x81; //
@@ -2033,9 +2033,9 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		tsc[1] = rdtsc();
-		printk_debug("set DQS timing:DQSPos: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i);
 	}
 
 	if(train_DqsPos(ctrl, sysinfo)) {
@@ -2044,10 +2044,10 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		tsc[2] = rdtsc();
 
-		printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
 	}
 	if(train_DqsRcvrEn(ctrl, 2,  sysinfo)){
 		sysinfo->mem_trained[i]=0x83; //
@@ -2055,7 +2055,7 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 
 		tsc[3] = rdtsc();
 	}
@@ -2106,7 +2106,7 @@
 	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
 	#if CONFIG_AP_CODE_IN_CAR == 0
-		printk_debug("CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
+		printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
 		train_ram(nodeid, sysinfo, sysinfox);
 	#else
 		/* Can copy dqs_timing to ap cache and run from cache?
Index: src/northbridge/amd/amdk8/debug.c
===================================================================
--- src/northbridge/amd/amdk8/debug.c	(revision 5263)
+++ src/northbridge/amd/amdk8/debug.c	(working copy)
@@ -10,14 +10,14 @@
 static inline void print_debug_addr(const char *str, void *val)
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
-		printk_debug("------Address debug: %s%x------\n", str, val);
+		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }
 
 #if 1
 static void print_debug_pci_dev(unsigned dev)
 {
-	printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 }
 
 static void print_pci_devices(void)
@@ -34,7 +34,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			uint8_t hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -53,10 +53,10 @@
 	for(i = 0; i < 256; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%02x:",i);
+			printk(BIOS_DEBUG, "\n%02x:",i);
 		}
 		val = pci_read_config8(dev, i);
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 	}
 	print_debug("\n");
 }
@@ -72,10 +72,10 @@
 	for(i = 0; i < 0x40; i++) {
 		uint32_t val;
 		int j;
-		printk_debug("\n%02x:",i);
+		printk(BIOS_DEBUG, "\n%02x:",i);
 		val = pci_read_config32_index_wait(dev, index_reg, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 
@@ -145,38 +145,38 @@
 		device = ctrl->channel0[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.1: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
@@ -189,7 +189,7 @@
 	for(device = 1; device < 0x80; device++) {
 		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for(j = 0; j < 256; j++) {
 			int status;
 			unsigned char byte;
@@ -198,10 +198,10 @@
 				break;
 			}
 			if ((j & 0xf) == 0) {
-				printk_debug("\n%02x: ",j);
+				printk(BIOS_DEBUG, "\n%02x: ",j);
 			}
 			byte = status & 0xff;
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		print_debug("\n");
 	}
@@ -213,14 +213,14 @@
 
 	int i;
 	udelay(2000);
-	printk_debug("%04x:\n", port);
+	printk(BIOS_DEBUG, "%04x:\n", port);
 	for(i=0;i<256;i++) {
 		uint8_t val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = inb(port);
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 		if ((i & 0x0f) == 0x0f) {
 			print_debug("\n");
 		}
@@ -234,9 +234,9 @@
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 	}
 	print_debug("\n");
  }
Index: src/northbridge/amd/amdk8/incoherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/incoherent_ht.c	(revision 5263)
+++ src/northbridge/amd/amdk8/incoherent_ht.c	(working copy)
@@ -26,7 +26,7 @@
 
 static inline void print_linkn_in (const char *strval, uint8_t byteval)
 {
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
 }
 
 static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
@@ -127,7 +127,7 @@
 	uint32_t id;
 
 	freq_cap = pci_read_config16(dev, pos);
-	printk_spew("pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
+	printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
 	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
 
 	id = pci_read_config32(dev, 0);
@@ -157,8 +157,8 @@
 	#endif
 	}
 
-	printk_spew("pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
-	//printk_spew("capping to 800/600/400/200 MHz\r\n");
+	printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
+	//printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n");
 	//freq_cap &= 0x3f;
 	return freq_cap;
 }
@@ -220,14 +220,14 @@
 	int needs_reset;
 	/* Set link width and frequency */
 
-	printk_spew("entering ht_optimize_link\r\n");
+	printk(BIOS_SPEW, "entering ht_optimize_link\r\n");
 	/* Initially assume everything is already optimized and I don't need a reset */
 	needs_reset = 0;
 
 	/* Get the frequency capabilities */
 	freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
 	freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
-	printk_spew("freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
+	printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
 
 	/* Calculate the highest possible frequency */
 	freq = log2(freq_cap1 & freq_cap2);
@@ -236,11 +236,11 @@
 	old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
 	old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
 
 	/* Set the Calculated link frequency */
 	pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
@@ -249,45 +249,45 @@
 	/* Get the width capabilities */
 	width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
 	width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
-	printk_spew("width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
+	printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
 
 	/* Calculate dev1's input width */
 	ln_width1 = link_width_to_pow2[width_cap1 & 7];
 	ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
-	printk_spew("dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width = pow2_to_link_width[ln_width1];
-	printk_spew("dev1 input width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width);
 	/* Calculate dev1's output width */
 	ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
 	ln_width2 = link_width_to_pow2[width_cap2 & 7];
-	printk_spew("dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width |= pow2_to_link_width[ln_width1] << 4;
-	printk_spew("dev1 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width);
 
 	/* See if I am changing dev1's width */
 	old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev1 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width);
 
 	/* Set dev1's widths */
 	pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
 
 	/* Calculate dev2's width */
 	width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
-	printk_spew("dev2 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width);
 
 	/* See if I am changing dev2's width */
 	old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev2 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width);
 
 	/* Set dev2's widths */
 	pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
@@ -852,16 +852,16 @@
 
 	unsigned link_pair_num = sysinfo->link_pair_num;
 
-	printk_spew("entering optimize_link_incoherent_ht\r\n");
-	printk_spew("sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
+	printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n");
+	printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
 	for(i=0; i< link_pair_num; i++) {
 		struct link_pair_st *link_pair= &sysinfo->link_pair[i];
 		reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
-		printk_spew("after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
+		printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
 	}
 
 	reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
-	printk_spew("after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
+	printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
 
 	return reset_needed;
 
Index: src/northbridge/amd/amdk8/misc_control.c
===================================================================
--- src/northbridge/amd/amdk8/misc_control.c	(revision 5263)
+++ src/northbridge/amd/amdk8/misc_control.c	(working copy)
@@ -112,7 +112,7 @@
 	int needs_reset;
 	struct device *f0_dev, *f2_dev;
 	
-	printk_debug("NB: Function 3 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
 
 	/* Disable Machine checks from Invalid Locations.
@@ -205,13 +205,13 @@
 		}
 	}
 	else {
-		printk_err("Missing f0 device!\n");
+		printk(BIOS_ERR, "Missing f0 device!\n");
 	}
 	if (needs_reset) {
-		printk_debug("resetting cpu\n");
+		printk(BIOS_DEBUG, "resetting cpu\n");
 		hard_reset();
 	}
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 
Index: src/northbridge/amd/amdmct/mct/mctdqs_d.c
===================================================================
--- src/northbridge/amd/amdmct/mct/mctdqs_d.c	(revision 5263)
+++ src/northbridge/amd/amdmct/mct/mctdqs_d.c	(working copy)
@@ -69,7 +69,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
-		printk_debug("%s%x\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\n", str, val);
 	}
 #endif
 }
@@ -78,7 +78,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
-		printk_debug("%s%08x%s%08x\n", str, val, str2, val2);
+		printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2);
 	}
 #endif
 }
Index: src/northbridge/amd/amdmct/mct/mct_d.c
===================================================================
--- src/northbridge/amd/amdmct/mct/mct_d.c	(revision 5263)
+++ src/northbridge/amd/amdmct/mct/mct_d.c	(working copy)
@@ -556,7 +556,7 @@
 			base  += NextBase;
 			limit += NextBase;
 			DramSelBaseAddr += NextBase;
-			printk_debug(" Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
+			printk(BIOS_DEBUG, " Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
 
 			if (_MemHoleRemap) {
 				if ((base < BottomIO) && (limit >= BottomIO)) {
@@ -633,7 +633,7 @@
 		devx = pDCTstat->dev_map;
 
 		if (pDCTstat->NodePresent) {
-		printk_debug(" Copy dram map from Node 0 to Node %02x \n", Node);
+		printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
 			reg = 0x40;		/*Dram Base 0*/
 			do {
 				val = Get_NB32(dev, reg);
Index: src/northbridge/amd/amdfam10/setup_resource_map.c
===================================================================
--- src/northbridge/amd/amdfam10/setup_resource_map.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/setup_resource_map.c	(working copy)
@@ -81,7 +81,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
 			i/4, register_values[i],
 			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 			register_values[i+2],
@@ -146,7 +146,7 @@
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
 		i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
 #endif
 		switch (register_values[i]) {
Index: src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- src/northbridge/amd/amdfam10/northbridge.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/northbridge.c	(working copy)
@@ -83,7 +83,7 @@
 		__f4_dev[i] = get_node_pci(i, 4);
 	}
 	if (!__f1_dev[0]) {
-		printk_err("Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
+		printk(BIOS_ERR, "Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
 		die("Cannot go on\n");
 	}
 }
@@ -568,7 +568,7 @@
 	for (link = 0; link < dev->links; link++) {
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 				dev->link[link].secondary,dev->link[link].subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@@ -583,7 +583,7 @@
 	if (link == dev->links)
 		return;
 
-	printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 	set_vga_enable_reg(nodeid, link);
 }
 
@@ -906,9 +906,9 @@
 		mem1 = find_resource(dev, 1|(link<<2));
 		mem2 = find_resource(dev, 2|(link<<2));
 
-		printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem1->base, mem1->limit, mem1->size, mem1->align);
-		printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem2->base, mem2->limit, mem2->size, mem2->align);
 
 		/* See if both resources have roughly the same limits */
@@ -934,9 +934,9 @@
 			mem1->base = resource_max(mem1);
 		}
 
-		printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem1->base, mem1->limit, mem1->size, mem1->align);
-		printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem2->base, mem2->limit, mem2->size, mem2->align);
 	}
 
@@ -1041,7 +1041,7 @@
 
 		}
 
-//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
+//		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
 
 		/* split the region to accomodate pci memory space */
 		if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
@@ -1057,7 +1057,7 @@
 					/* Leave some space for ACPI, PIRQ and MP tables */
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk(BIOS_DEBUG, "(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1086,7 +1086,7 @@
 		ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
 #if CONFIG_WRITE_HIGH_TABLES==1
-		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
 		if (i==0 && high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
@@ -1144,7 +1144,7 @@
 			if (!dev->link[0].disable_relaxed_ordering) {
 				httc |= HTTC_RSP_PASS_PW;
 			}
-			printk_spew("%s passpw: %s\n",
+			printk(BIOS_SPEW, "%s passpw: %s\n",
 				dev_path(dev),
 				(!dev->link[0].disable_relaxed_ordering)?
 				"enabled":"disabled");
@@ -1247,34 +1247,34 @@
 #if CONFIG_CBB
 	dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
 	if(dev_mc && dev_mc->bus) {
-		printk_debug("%s found", dev_path(dev_mc));
+		printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
 		pci_domain = dev_mc->bus->dev;
 		if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
-			printk_debug("\n%s move to ",dev_path(dev_mc));
+			printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
 			dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
-			printk_debug("%s",dev_path(dev_mc));
+			printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
 
 		} else {
-			printk_debug(" but it is not under pci_domain directly ");
+			printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
 		}
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 
 	}
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if(!dev_mc) {
 		dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 		if (dev_mc && dev_mc->bus) {
-			printk_debug("%s found\n", dev_path(dev_mc));
+			printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
 			pci_domain = dev_mc->bus->dev;
 			if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
 				if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) {
-					printk_debug("%s move to ",dev_path(dev_mc));
+					printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 					dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
-					printk_debug("%s\n",dev_path(dev_mc));
+					printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
 					while(dev_mc){
-						printk_debug("%s move to ",dev_path(dev_mc));
+						printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 						dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
-						printk_debug("%s\n",dev_path(dev_mc));
+						printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
 						dev_mc = dev_mc->sibling;
 					}
 				}
@@ -1286,7 +1286,7 @@
 
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if (!dev_mc) {
-		printk_err("%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
 		die("");
 	}
 
@@ -1301,7 +1301,7 @@
 			pci_domain->link[1].link = 1;
 			pci_domain->link[1].dev = pci_domain;
 			pci_domain->link[1].children = 0;
-			printk_debug("%s links increase to %d\n", dev_path(pci_domain), pci_domain->links);
+			printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(pci_domain), pci_domain->links);
 		}
 		pci_domain->link[1].secondary = CONFIG_CBB - 1;
 	}
@@ -1355,7 +1355,7 @@
 					 dev->link[j].dev = dev;
 				}
 				dev->links = linknum;
-				printk_debug("%s links increase to %d\n", dev_path(dev), dev->links);
+				printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(dev), dev->links);
 			}
 		}
 
@@ -1366,7 +1366,7 @@
 			cores_found = (j >> 12) & 3; // dev is func 3
 			if (siblings > 3)
 				cores_found |= (j >> 13) & 4;
-			printk_debug("  %s siblings=%d\n", dev_path(dev), cores_found);
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(dev), cores_found);
 		}
 
 		u32 jj;
@@ -1416,7 +1416,7 @@
 					 }
 				}
 	#endif
-				printk_debug("CPU: %s %s\n",
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
 					dev_path(cpu), cpu->enabled?"enabled":"disabled");
 			}
 
Index: src/northbridge/amd/amdfam10/amdfam10_acpi.c
===================================================================
--- src/northbridge/amd/amdfam10/amdfam10_acpi.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/amdfam10_acpi.c	(working copy)
@@ -60,7 +60,7 @@
 		if (!cpu->enabled) {
 			continue;
 		}
-		printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+		printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		cpu_index++;
 	}
@@ -89,7 +89,7 @@
 	basek = resk(res->base);
 	sizek = resk(res->size);
 
-	printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
+	printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
 			dev_path(dev), res->index, basek, sizek);
 	/*
 	 * 0-640K must be on node 0
@@ -338,7 +338,7 @@
 		if (!cpu->enabled) {
 			 continue;
 		}
-		printk_debug("ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
+		printk(BIOS_DEBUG, "ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
 
 		current	  = ( current + 0x0f) & -0x10;
 		ssdt = (acpi_header_t *)current;
Index: src/northbridge/amd/amdfam10/get_pci1234.c
===================================================================
--- src/northbridge/amd/amdfam10/get_pci1234.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/get_pci1234.c	(working copy)
@@ -75,12 +75,12 @@
 	//here we need to set hcdn
 	//1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set
 	//2. so at the same time we need update hsdn with hcdn_reg here
-//	printk_debug("sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
+//	printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
 
 	for(j=0;j<sysconf.ht_c_num;j++) {
 		u32 dwordx;
 		dwordx = sysconf.ht_c_conf_bus[j];
-//		printk_debug("sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
+//		printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
 		dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits
 		if((dwordx & 0x7fd) == dword) { //SBLINK
 			sysconf.pci1234[0] = dwordx;
Index: src/northbridge/amd/amdfam10/debug.c
===================================================================
--- src/northbridge/amd/amdfam10/debug.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/debug.c	(working copy)
@@ -28,16 +28,16 @@
 static  void print_debug_addr(const char *str, void *val)
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
-		printk_debug("------Address debug: %s%x------\n", str, val);
+		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }
 
 static void print_debug_pci_dev(u32 dev)
 {
 #if CONFIG_PCI_BUS_SEGN_BITS==0
-	printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 #else
-	printk_debug("PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 #endif
 }
 
@@ -55,7 +55,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			u8 hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -80,7 +80,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			u8 hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -103,11 +103,11 @@
 	for(i = start_reg; i < end; i+=4) {
 		u32 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%04x:",i);
+			printk(BIOS_DEBUG, "\n%04x:",i);
 		}
 		val = pci_read_config32(dev, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 	}
@@ -129,10 +129,10 @@
 	for(i = start; i < end; i++) {
 		u32 val;
 		int j;
-		printk_debug("\n%02x:",i);
+		printk(BIOS_DEBUG, "\n%02x:",i);
 		val = pci_read_config32_index_wait(dev, index_reg, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 
@@ -160,10 +160,10 @@
 	for(i = 0; i < length; i++) {
 		u32 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%02x:",i);
+			printk(BIOS_DEBUG, "\n%02x:",i);
 		}
 		val = pci_read_config32_index(dev, index_reg, i|type);
-		printk_debug(" %08x", val);
+		printk(BIOS_DEBUG, " %08x", val);
 	}
 	print_debug("\n");
 }
@@ -231,38 +231,38 @@
 		device = ctrl->spd_addr[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				u8 byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
 		device = ctrl->spd_addr[i+DIMM_SOCKETS];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.1: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				u8 byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
@@ -275,7 +275,7 @@
 	for(device = 1; device < 0x80; device++) {
 		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for(j = 0; j < 256; j++) {
 			int status;
 			u8 byte;
@@ -284,10 +284,10 @@
 				break;
 			}
 			if ((j & 0xf) == 0) {
-				printk_debug("\n%02x: ",j);
+				printk(BIOS_DEBUG, "\n%02x: ",j);
 			}
 			byte = status & 0xff;
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		print_debug("\n");
 	}
@@ -298,14 +298,14 @@
 
 	int i;
 	udelay_tsc(2000);
-	printk_debug("%04x:\n", port);
+	printk(BIOS_DEBUG, "%04x:\n", port);
 	for(i=0;i<256;i++) {
 		u8 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = inb(port);
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 		if ((i & 0x0f) == 0x0f) {
 			print_debug("\n");
 		}
@@ -319,9 +319,9 @@
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
Index: src/northbridge/amd/amdfam10/raminit_amdmct.c
===================================================================
--- src/northbridge/amd/amdfam10/raminit_amdmct.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/raminit_amdmct.c	(working copy)
@@ -20,7 +20,7 @@
 
 static  void print_raminit(const char *strval, u32 val)
 {
-	printk_debug("%s%08x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 }
 
 static  void print_tx(const char *strval, u32 val)
Index: src/northbridge/amd/amdfam10/misc_control.c
===================================================================
--- src/northbridge/amd/amdfam10/misc_control.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/misc_control.c	(working copy)
@@ -125,7 +125,7 @@
 {
 	u32 cmd;
 
-	printk_debug("NB: Function 3 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 
 	/* Disable Machine checks from Invalid Locations.
 	 * This is needed for PC backwards compatibility.
@@ -134,7 +134,7 @@
 	cmd |= (1<<6) | (1<<25);
 	pci_write_config32(dev, 0x44, cmd );
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 
Index: src/northbridge/amd/amdfam10/amdfam10_conf.c
===================================================================
--- src/northbridge/amd/amdfam10/amdfam10_conf.c	(revision 5263)
+++ src/northbridge/amd/amdfam10/amdfam10_conf.c	(working copy)
@@ -779,7 +779,7 @@
 #if 0
 		// FIXME: can we use VGA reg instead?
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-			printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
 				__func__, dev_path(dev), link);
 			tempreg |= PCI_IO_BASE_VGA_EN;
 		}
Index: src/northbridge/amd/amdfam10/amdfam10.h
===================================================================
--- src/northbridge/amd/amdfam10/amdfam10.h	(revision 5263)
+++ src/northbridge/amd/amdfam10/amdfam10.h	(working copy)
@@ -1134,7 +1134,7 @@
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
 #else
-		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -1152,7 +1152,7 @@
 		print_debug("mem trained failed\n");
 		soft_reset();
 #else
-		printk_debug("mem trained failed\n");
+		printk(BIOS_DEBUG, "mem trained failed\n");
 		hard_reset();
 #endif
 	}
Index: src/northbridge/amd/amdht/comlib.c
===================================================================
--- src/northbridge/amd/amdht/comlib.c	(revision 5263)
+++ src/northbridge/amd/amdht/comlib.c	(working copy)
@@ -240,7 +240,7 @@
 
 void ErrorStop(u32 value)
 {
-	printk_debug("Error: %08x ", value);
+	printk(BIOS_DEBUG, "Error: %08x ", value);
 
 }
 
Index: src/northbridge/amd/amdht/ht_wrapper.c
===================================================================
--- src/northbridge/amd/amdht/ht_wrapper.c	(revision 5263)
+++ src/northbridge/amd/amdht/ht_wrapper.c	(working copy)
@@ -84,13 +84,13 @@
 {
 	u8 i;
 
-	printk_debug("AMD_CB_EventNotify()\n");
-	printk_debug(" event class: %02x\n event: %04x\n data: ", evtClass, event);
+	printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
+	printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
 
 	for (i = 0; i < *pEventData0; i++) {
-		printk_debug(" %02x ", *(pEventData0 + i));
+		printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 }
 
@@ -119,7 +119,7 @@
 	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 	/* If the BUID was adjusted in early_ht we need to do the manual override */
 	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
-		printk_debug("AMD_CB_ManualBUIDSwapList()\n");
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 		if ((node == 0) && (link == 0)) {	/* BSP SB link */
 			*List = swaplist;
 			return 1;
@@ -170,9 +170,9 @@
 		AMD_CB_EventNotify	// void (*AMD_CB_EventNotify) ();
 	};
 
-	printk_debug("Enter amd_ht_init()\n");
+	printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
 	amdHtInitialize(&ht_wrapper);
-	printk_debug("Exit amd_ht_init()\n");
+	printk(BIOS_DEBUG, "Exit amd_ht_init()\n");
 
 
 }
Index: src/northbridge/intel/e7501/debug.c
===================================================================
--- src/northbridge/intel/e7501/debug.c	(revision 5263)
+++ src/northbridge/intel/e7501/debug.c	(working copy)
@@ -40,7 +40,7 @@
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 #if CONFIG_USE_INIT
-                        printk_debug("\r\n%02x:",i);
+                        printk(BIOS_DEBUG, "\r\n%02x:",i);
 #else
 			print_debug("\r\n");
 			print_debug_hex8(i);
@@ -49,7 +49,7 @@
 		}
 		val = pci_read_config8(dev, i);
 #if CONFIG_USE_INIT
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 #else
 		print_debug_char(' ');
 		print_debug_hex8(val);
@@ -102,7 +102,7 @@
 		if (device) {
 			int j;
 #if CONFIG_USE_INIT
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 #else
 			print_debug("dimm: "); 
 			print_debug_hex8(i); 
@@ -114,7 +114,7 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-					printk_debug("\r\n%02x: ", j);
+					printk(BIOS_DEBUG, "\r\n%02x: ", j);
 #else
 					print_debug("\r\n");
 					print_debug_hex8(j);
@@ -127,7 +127,7 @@
 				}
 				byte = status & 0xff;
 #if CONFIG_USE_INIT
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 #else
 				print_debug_hex8(byte);
 				print_debug_char(' ');
@@ -139,7 +139,7 @@
 		if (device) {
 			int j;
 #if CONFIG_USE_INIT
-                        printk_debug("dimm: %02x.1: %02x", i, device);
+                        printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 #else`
 			print_debug("dimm: "); 
 			print_debug_hex8(i); 
@@ -151,7 +151,7 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-                                        printk_debug("\r\n%02x: ", j);
+                                        printk(BIOS_DEBUG, "\r\n%02x: ", j);
 #else
 					print_debug("\r\n");
 					print_debug_hex8(j);
@@ -164,7 +164,7 @@
 				}
 				byte = status & 0xff;
 #if CONFIG_USE_INIT
-                                printk_debug("%02x ", byte);
+                                printk(BIOS_DEBUG, "%02x ", byte);
 #else
 				print_debug_hex8(byte);
 				print_debug_char(' ');
@@ -182,7 +182,7 @@
                 int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
 #if CONFIG_USE_INIT
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 #else
                 print_debug("smbus: ");
                 print_debug_hex8(device);
@@ -196,7 +196,7 @@
                         }
                         if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-				printk_debug("\r\n%02x: ",j);
+				printk(BIOS_DEBUG, "\r\n%02x: ",j);
 #else
                 	        print_debug("\r\n");
                                 print_debug_hex8(j);
@@ -205,7 +205,7 @@
                         }
                         byte = status & 0xff;
 #if CONFIG_USE_INIT
-                        printk_debug("%02x ", byte);
+                        printk(BIOS_DEBUG, "%02x ", byte);
 #else
                         print_debug_hex8(byte);
                         print_debug_char(' ');
@@ -220,7 +220,7 @@
 
 	int i;
 #if CONFIG_USE_INIT
-	printk_debug("%04x:\r\n", port);
+	printk(BIOS_DEBUG, "%04x:\r\n", port);
 #else
         print_debug_hex16(port);
         print_debug(":\r\n");
@@ -229,7 +229,7 @@
                 uint8_t val;
                 if ((i & 0x0f) == 0) {
 #if CONFIG_USE_INIT
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 #else
                         print_debug_hex8(i);
                         print_debug_char(':');
@@ -237,7 +237,7 @@
                 }
                 val = inb(port);
 #if CONFIG_USE_INIT
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 #else
                 print_debug_char(' ');
                 print_debug_hex8(val);
@@ -256,7 +256,7 @@
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
 #if CONFIG_USE_INIT
-			printk_debug("\r\n%08x:", i);
+			printk(BIOS_DEBUG, "\r\n%08x:", i);
 #else	
 			print_debug("\r\n");
 			print_debug_hex32(i);
@@ -264,7 +264,7 @@
 #endif
 		}
 #if CONFIG_USE_INIT	
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 #else
 		print_debug(" ");
              	print_debug_hex8((unsigned char)*((unsigned char *)i));
Index: src/northbridge/intel/e7520/northbridge.c
===================================================================
--- src/northbridge/intel/e7520/northbridge.c	(revision 5263)
+++ src/northbridge/intel/e7520/northbridge.c	(working copy)
@@ -65,7 +65,7 @@
         pci_tolm = find_pci_tolm(&dev->link[0]);
 
 #if 1
-	printk_debug("PCI mem marker = %x\n", pci_tolm);
+	printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
 #endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
Index: src/northbridge/intel/e7520/pciexp_porta.c
===================================================================
--- src/northbridge/intel/e7520/pciexp_porta.c	(revision 5263)
+++ src/northbridge/intel/e7520/pciexp_porta.c	(working copy)
@@ -30,12 +30,12 @@
 	int flag = 0;
 	do {
 		val = pci_read_config16(dev, 0x76);
-		printk_debug("pcie porta 0x76: %02x\n", val);
+		printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
 		if((val & (1<<10) )&&(!flag)) { /* training error */
 			ctl = pci_read_config16(dev, 0x74);
 			pci_write_config16(dev, 0x74, (ctl | (1<<5)));
 			val = pci_read_config16(dev, 0x76);
-			printk_debug("pcie porta reset 0x76: %02x\n", val);
+			printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
 			flag=1;
 			hard_reset();
 		}
Index: src/northbridge/intel/i440lx/raminit.c
===================================================================
--- src/northbridge/intel/i440lx/raminit.c	(revision 5263)
+++ src/northbridge/intel/i440lx/raminit.c	(working copy)
@@ -244,7 +244,7 @@
 #if 0
 	uint16_t reg16;
 	reg16 = pci_read_config16(NB, PACCFG); 
-	printk_debug("i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
+	printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
 #endif
 
 	PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
Index: src/northbridge/intel/i440lx/northbridge.c
===================================================================
--- src/northbridge/intel/i440lx/northbridge.c	(revision 5263)
+++ src/northbridge/intel/i440lx/northbridge.c	(working copy)
@@ -43,7 +43,7 @@
  */
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge Init\n");
+	printk(BIOS_SPEW, "Northbridge Init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -125,7 +125,7 @@
 		/* Convert to KB. */
 		tomk *= (8 * 1024);
 
-		printk_debug("Setting RAM size to %lu MB\n", tomk / 1024);
+		printk(BIOS_DEBUG, "Setting RAM size to %lu MB\n", tomk / 1024);
 
 		/* Compute the top of low memory. */
 		tolmk = pci_tolm / 1024;
Index: src/northbridge/intel/e7525/northbridge.c
===================================================================
--- src/northbridge/intel/e7525/northbridge.c	(revision 5263)
+++ src/northbridge/intel/e7525/northbridge.c	(working copy)
@@ -65,7 +65,7 @@
         pci_tolm = find_pci_tolm(&dev->link[0]);
 
 #if 1
-	printk_debug("PCI mem marker = %x\n", pci_tolm);
+	printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
 #endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
Index: src/northbridge/intel/i440bx/debug.c
===================================================================
--- src/northbridge/intel/i440bx/debug.c	(revision 5263)
+++ src/northbridge/intel/i440bx/debug.c	(working copy)
@@ -39,25 +39,25 @@
 {
 	unsigned device;
 	device = SMBUS_MEM_DEVICE_START;
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	while(device <= SMBUS_MEM_DEVICE_END) {
 		int status = 0;
 		int i;
-		printk_debug("dimm %02x", device);
+		printk(BIOS_DEBUG, "dimm %02x", device);
 		for(i = 0; (i < 256) && (status == 0); i++) {
 			unsigned char byte;
 			if ((i % 20) == 0) {
-				printk_debug("\n%3d: ", i);
+				printk(BIOS_DEBUG, "\n%3d: ", i);
 			}
 			status = smbus_read_byte(device, i, &byte);
 			if (status != 0) {
-				printk_debug("bad device\n");
+				printk(BIOS_DEBUG, "bad device\n");
 				continue;
 			}
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 #endif
Index: src/northbridge/intel/i440bx/northbridge.c
===================================================================
--- src/northbridge/intel/i440bx/northbridge.c	(revision 5263)
+++ src/northbridge/intel/i440bx/northbridge.c	(working copy)
@@ -15,7 +15,7 @@
 
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge Init\n");
+	printk(BIOS_SPEW, "Northbridge Init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -97,7 +97,7 @@
 		/* Convert to KB. */
 		tomk *= (8 * 1024);
 
-		printk_debug("Setting RAM size to %ld MB\n", tomk / 1024);
+		printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
 
 		/* Compute the top of low memory. */
 		tolmk = pci_tolm / 1024;
Index: src/northbridge/intel/i945/early_init.c
===================================================================
--- src/northbridge/intel/i945/early_init.c	(revision 5263)
+++ src/northbridge/intel/i945/early_init.c	(working copy)
@@ -29,108 +29,108 @@
 {
 	u8 reg8;
 
-	printk_info("\n");
+	printk(BIOS_INFO, "\n");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
 	switch (reg8) {
 	case 1:
-		printk_info("Mobile Intel(R) 82945GM/GME Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
 		break;
 	case 2:
-		printk_info("Mobile Intel(R) 82945GMS/GU Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express");
 		break;
 	case 3:
-		printk_info("Mobile Intel(R) 82945PM Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
 		break;
 	case 5:
-		printk_info("Intel(R) 82945GT Express");
+		printk(BIOS_INFO, "Intel(R) 82945GT Express");
 		break;
 	case 6:
-		printk_info("Mobile Intel(R) 82943/82940GML Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
 		break;
 	default:
-		printk_info("Unknown (%02x)", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "Unknown (%02x)", reg8);	/* Others reserved. */
 	}
-	printk_info(" Chipset\n");
+	printk(BIOS_INFO, " Chipset\n");
 
-	printk_debug("(G)MCH capable of up to FSB ");
+	printk(BIOS_DEBUG, "(G)MCH capable of up to FSB ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5;
 	switch (reg8) {
 	case 2:
-		printk_debug("800 MHz"); /* According to 965 spec */
+		printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */
 		break;
 	case 3:
-		printk_debug("667 MHz");
+		printk(BIOS_DEBUG, "667 MHz");
 		break;
 	case 4:
-		printk_debug("533 MHz");
+		printk(BIOS_DEBUG, "533 MHz");
 		break;
 	default:
-		printk_debug("N/A MHz (%02x)", reg8);
+		printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8);
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
-	printk_debug("(G)MCH capable of ");
+	printk(BIOS_DEBUG, "(G)MCH capable of ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
 	switch (reg8) {
 	case 2:
-		printk_debug("up to DDR2-667");
+		printk(BIOS_DEBUG, "up to DDR2-667");
 		break;
 	case 3:
-		printk_debug("up to DDR2-533");
+		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;
 	case 4:
-		printk_debug("DDR2-400");
+		printk(BIOS_DEBUG, "DDR2-400");
 		break;
 	default:
-		printk_info("unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void i945_detect_chipset(void)
 {
 	u8 reg8;
 
-	printk_info("\nIntel(R) ");
+	printk(BIOS_INFO, "\nIntel(R) ");
 
 	reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
 	switch (reg8) {
 	case 0:
 	case 1:
-		printk_info("82945G");
+		printk(BIOS_INFO, "82945G");
 		break;
 	case 2:
 	case 3:
-		printk_info("82945P");
+		printk(BIOS_INFO, "82945P");
 		break;
 	case 4:
-		printk_info("82945GC");
+		printk(BIOS_INFO, "82945GC");
 		break;
 	case 5:
-		printk_info("82945GZ");
+		printk(BIOS_INFO, "82945GZ");
 		break;
 	case 6:
 	case 7:
-		printk_info("82945PL");
+		printk(BIOS_INFO, "82945PL");
 		break;
 	default:
 		break;
 	}
-	printk_info(" Chipset\n");
+	printk(BIOS_INFO, " Chipset\n");
 
-	printk_debug("(G)MCH capable of ");
+	printk(BIOS_DEBUG, "(G)MCH capable of ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
 	switch (reg8) {
 	case 0:
-		printk_debug("up to DDR2-667");
+		printk(BIOS_DEBUG, "up to DDR2-667");
 		break;
 	case 3:
-		printk_debug("up to DDR2-533");
+		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;
 	default:
-		printk_info("unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void i945_setup_bars(void)
@@ -139,11 +139,10 @@
 
 	/* As of now, we don't have all the A0 workarounds implemented */
 	if (i945_silicon_revision() == 0)
-		printk_info
-		    ("Warning: i945 silicon revision A0 might not work correctly.\n");
+		printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
 
 	/* Setting up Southbridge. In the northbridge code. */
-	printk_debug("Setting up static southbridge registers...");
+	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
 
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
@@ -152,14 +151,14 @@
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);	/* Enable GPIOs */
 	setup_ich7_gpios();
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
-	printk_debug("Disabling Watchdog reboot...");
+	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
 	RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5);	/* No reset */
 	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
-	printk_debug("Setting up static northbridge registers...");
+	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	/* Set up all hardcoded northbridge BARs */
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
@@ -182,16 +181,16 @@
 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
 
 	pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
 	/* Wait for MCH BAR to come up */
-	printk_debug("Waiting for MCHBAR to come up...");
+	printk(BIOS_DEBUG, "Waiting for MCHBAR to come up...");
 	if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */
 		do {
 			reg8 = *(volatile u8 *)0xfed40000;
 		} while (!(reg8 & 0x80));
 	}
-	printk_debug("ok\n");
+	printk(BIOS_DEBUG, "ok\n");
 }
 
 static void i945_setup_egress_port(void)
@@ -199,7 +198,7 @@
 	u32 reg32;
 	u32 timeout;
 
-	printk_debug("Setting up Egress Port RCRB\n");
+	printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n");
 
 	/* Egress Port Virtual Channel 0 Configuration */
 
@@ -267,26 +266,26 @@
 	EPBAR32(EPVC1RCTL) |= (1 << 16);
 	EPBAR32(EPVC1RCTL) |= (1 << 16);
 
-	printk_debug("Loading port arbitration table ...");
+	printk(BIOS_DEBUG, "Loading port arbitration table ...");
 	/* Loop until bit 0 becomes 0 */
 	timeout = 0x7fffff;
 	while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	/* Now enable VC1 */
 	EPBAR32(EPVC1RCTL) |= (1 << 31);
 
-	printk_debug("Wait for VC1 negotiation ...");
+	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7fff;
 	while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 }
 
@@ -348,7 +347,7 @@
 
 	int activate_aspm = 1;
 
-	printk_debug("Setting up DMI RCRB\n");
+	printk(BIOS_DEBUG, "Setting up DMI RCRB\n");
 
 	/* Virtual Channel 0 Configuration */
 	reg32 = DMIBAR32(DMIVC0RCTL0);
@@ -373,14 +372,14 @@
 	/* Now enable VC1 */
 	DMIBAR32(DMIVC1RCTL) |= (1 << 31);
 
-	printk_debug("Wait for VC1 negotiation ...");
+	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7ffff;
 	while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("done..\n");
+		printk(BIOS_DEBUG, "done..\n");
 #if 1
 	/* Enable Active State Power Management (ASPM) L0 state */
 
@@ -425,10 +424,10 @@
 	DMIBAR32(0x204) = reg32;
 
 	if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) {	/* DEVEN */
-		printk_debug("Internal graphics: enabled\n");
+		printk(BIOS_DEBUG, "Internal graphics: enabled\n");
 		DMIBAR32(0x200) |= (1 << 21);
 	} else {
-		printk_debug("Internal graphics: disabled\n");
+		printk(BIOS_DEBUG, "Internal graphics: disabled\n");
 		DMIBAR32(0x200) &= ~(1 << 21);
 	}
 
@@ -474,13 +473,13 @@
 	}
 
 	/* wait for bit toggle to 0 */
-	printk_debug("Waiting for DMI hardware...");
+	printk(BIOS_DEBUG, "Waiting for DMI hardware...");
 	timeout = 0x7fffff;
 	while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	DMIBAR32(0x1c4) = 0xffffffff;
 	DMIBAR32(0x1d0) = 0xffffffff;
@@ -495,8 +494,7 @@
 
 	if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) {
 		if ((MCHBAR32(0x214) & 0xf) != 0x3) {
-			printk_info
-			    ("DMI link requires A1 stepping workaround. Rebooting.\n");
+			printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n");
 			reg32 = DMIBAR32(0x224);
 			reg32 &= ~(7 << 0);
 			reg32 |= (3 << 0);
@@ -515,7 +513,7 @@
 
 	u8 reg8;
 
-	printk_debug("Enabling PCI Express x16 Link\n");
+	printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
 
 	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
 	reg16 |= DEVEN_D1F0;
@@ -540,7 +538,7 @@
 	pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 
 	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
-	printk_debug("SLOTSTS: %04x\n", reg16);
+	printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
 	if (!(reg16 & 0x48)) {
 		goto disable_pciexpress_x16_link;
 	}
@@ -576,18 +574,18 @@
 	pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
 
 	/* Wait for training to succeed */
-	printk_debug("PCIe link training ...");
+	printk(BIOS_DEBUG, "PCIe link training ...");
 	timeout = 0x7ffff;
 	while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3)  && --timeout) ;
 
 	reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
 	if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
-		printk_debug(" Detected PCIe device %04x:%04x\n",
+		printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n",
 				reg32 & 0xffff, reg32 >> 16);
 	} else {
-		printk_debug(" timeout!\n");
+		printk(BIOS_DEBUG, " timeout!\n");
 
-		printk_debug("Restrain PCIe port to x1\n");
+		printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
 
 		reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
 		reg32 &= ~(0xf << 1);
@@ -601,17 +599,17 @@
 		reg16 &= ~(1 << 6);
 		pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 
-		printk_debug("PCIe link training ...");
+		printk(BIOS_DEBUG, "PCIe link training ...");
 		timeout = 0x7ffff;
 		while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3)  && --timeout) ;
 
 		reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
 		if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
-			printk_debug(" Detected PCIe x1 device %04x:%04x\n",
+			printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n",
 				reg32 & 0xffff, reg32 >> 16);
 		} else {
-			printk_debug(" timeout!\n");
-			printk_debug("Disabling PCIe x16 port completely.\n");
+			printk(BIOS_DEBUG, " timeout!\n");
+			printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n");
 			goto disable_pciexpress_x16_link;
 		}
 	}
@@ -620,7 +618,7 @@
 	reg16 >>= 4;
 	reg16 &= 0x3f;
 	/* reg16 == 1 -> x1; reg16 == 16 -> x16 */
-	printk_debug("PCIe x%d link training succeeded.\n", reg16);
+	printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
 
 	reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
 	reg32 &= 0xfffffc00; /* clear [9:0] */
@@ -633,9 +631,9 @@
 	}
 
 	reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
-	printk_debug("PCIe device class: %06x\n", reg32);
+	printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
 	if (reg32 == 0x030000) {
-		printk_debug("PCIe device is VGA. Disabling IGD.\n");
+		printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
 		reg16 = (1 << 1);
 		pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
 
@@ -758,7 +756,7 @@
 
 disable_pciexpress_x16_link:
 	/* For now we just disable the x16 link */
-	printk_debug("Disabling PCI Express x16 Link\n");
+	printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n");
 
 	MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
 
@@ -774,14 +772,14 @@
 	reg16 &= ~(1 << 6);
 	pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
 
-	printk_debug("Wait for link to enter detect state... ");
+	printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
 	timeout = 0x7fffff;
 	for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
 	     (reg32 & 0x000f0000) && --timeout;) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	/* Finally: Disable the PCI config header */
 	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
@@ -793,7 +791,7 @@
 {
 	u32 reg32;
 
-	printk_debug("Setting up Root Complex Topology\n");
+	printk(BIOS_DEBUG, "Setting up Root Complex Topology\n");
 	/* Egress Port Root Topology */
 
 	reg32 = EPBAR32(EPESD);
Index: src/northbridge/intel/i945/raminit.c
===================================================================
--- src/northbridge/intel/i945/raminit.c	(revision 5263)
+++ src/northbridge/intel/i945/raminit.c	(working copy)
@@ -25,7 +25,7 @@
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINTK_DEBUG(x...)	printk_debug(x)
+#define PRINTK_DEBUG(x...)	printk(BIOS_DEBUG, x)
 #else
 #define PRINTK_DEBUG(x...)
 #endif
@@ -74,12 +74,12 @@
 static void sdram_dump_mchbar_registers(void)
 {
 	int i;
-	printk_debug("Dumping MCHBAR Registers\n");
+	printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
 
 	for (i=0; i<0xfff; i+=4) {
 		if (MCHBAR32(i) == 0)
 			continue;
-		printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
+		printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
 	}
 }
 #endif
@@ -94,7 +94,7 @@
 	case 1: return 400;
 	case 2: return 533;
 	case 3: return 667;
-	default: printk_debug("memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
+	default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 	}
 	return -1;
 }
@@ -106,7 +106,7 @@
 	case 0: return 400;
 	case 1: return 533;
 	case 3: return 667;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
 	return -1;
 }
@@ -118,7 +118,7 @@
 	case 0: return 1066;
 	case 1: return 533;
 	case 2: return 800;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
 	return -1;
 }
@@ -234,7 +234,7 @@
 
 	if (reg8 & ((1<<7)|(1<<2))) {
 		if (reg8 & (1<<2)) {
-			printk_debug("SLP S4# Assertion Width Violation.\n");
+			printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 			/* Write back clears bit 2 */
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -242,7 +242,7 @@
 		}
 
 		if (reg8 & (1<<7)) {
-			printk_debug("DRAM initialization was interrupted.\n");
+			printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 			reg8 &= ~(1<<7);
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -254,7 +254,7 @@
 		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 
 		if (do_reset) {
-			printk_debug("Reset required.\n");
+			printk(BIOS_DEBUG, "Reset required.\n");
 			outb(0x00, 0xcf9);
 			outb(0x0e, 0xcf9);
 			for (;;) asm("hlt"); /* Wait for reset! */
@@ -300,10 +300,10 @@
 
 	if (sdram_capabilities_dual_channel()) {
 		sysinfo->dual_channel = 1;
-		printk_debug("This mainboard supports Dual Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 	} else {
 		sysinfo->dual_channel = 0;
-		printk_debug("This mainboard supports only Single Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 	}
 
 	/**
@@ -339,10 +339,10 @@
 		if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 			continue;
 
-		printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
+		printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 
 		if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
-			printk_debug("N/A\n");
+			printk(BIOS_DEBUG, "N/A\n");
 			continue;
 		}
 
@@ -360,29 +360,29 @@
 		case 0x08:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x8DDS\n");
+				printk(BIOS_DEBUG, "x8DDS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 				break;
 			case 0:
-				printk_debug("x8DS\n");
+				printk(BIOS_DEBUG, "x8DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		case 0x10:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x16DS\n");
+				printk(BIOS_DEBUG, "x16DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 				break;
 			case 0:
-				printk_debug("x16SS\n");
+				printk(BIOS_DEBUG, "x16SS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		default:
@@ -397,7 +397,7 @@
 	}
 
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk_info("Channel 0 has no memory populated.\n");
+		printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 	}
 }
 
@@ -556,7 +556,7 @@
 	}
 
 	if (sysinfo->memory_frequency && sysinfo->cas) {
-		printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
+		printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 				sysinfo->memory_frequency, sysinfo->cas);
 	} else {
 		die("Could not find common memory frequency and CAS\n");
@@ -599,7 +599,7 @@
 		die("DDR-II Module does not support this frequency (tRAS error)\n");
 	}
 
-	printk_debug("tRAS = %d cycles\n", tRAS_cycles);
+	printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 	sysinfo->tras = tRAS_cycles;
 }
 
@@ -640,7 +640,7 @@
 		die("DDR-II Module does not support this frequency (tRP error)\n");
 	}
 
-	printk_debug("tRP = %d cycles\n", tRP_cycles);
+	printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 	sysinfo->trp = tRP_cycles;
 }
 
@@ -680,7 +680,7 @@
 		die("DDR-II Module does not support this frequency (tRCD error)\n");
 	}
 
-	printk_debug("tRCD = %d cycles\n", tRCD_cycles);
+	printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 	sysinfo->trcd = tRCD_cycles;
 }
 
@@ -720,7 +720,7 @@
 		die("DDR-II Module does not support this frequency (tWR error)\n");
 	}
 
-	printk_debug("tWR = %d cycles\n", tWR_cycles);
+	printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 	sysinfo->twr = tWR_cycles;
 }
 
@@ -756,7 +756,7 @@
 			/* Can this happen? Go back to 127.5ns just to be sure
 			 * we don't run out of the array. This may be wrong
 			 */
-			printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
+			printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 			reg8 = 3;
 		}
 
@@ -772,7 +772,7 @@
 	}
 
 	sysinfo->trfc = tRFC_cycles[index];
-	printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
+	printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 }
 
 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
@@ -804,7 +804,7 @@
 
 		die("DDR-II module has unsupported refresh value\n");
 	}
-	printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
+	printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 }
 
 static void sdram_verify_burst_length(struct sys_info * sysinfo)
@@ -1137,18 +1137,18 @@
 
 	/* Dual Channel needs different tables. */
 	if (sdram_capabilities_dual_channel()) {
-		printk_debug("Programming Dual Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
 		strength_multiplier = dual_channel_strength_multiplier;
 		dual_channel = 1;
 		idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
 	} else {
-		printk_debug("Programming Single Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
 		strength_multiplier = single_channel_strength_multiplier;
 		dual_channel = 0;
 		idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
 	}
 
-	printk_debug("Table Index: %d\n", idx);
+	printk(BIOS_DEBUG, "Table Index: %d\n", idx);
 
 	MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
 	MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
@@ -1197,7 +1197,7 @@
 	u32 chan0dll = 0, chan1dll = 0;
 	int i;
 
-	printk_debug ("Programming DLL Timings... \n");
+	printk(BIOS_DEBUG, "Programming DLL Timings... \n");
 
 	MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
 	MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@@ -1249,7 +1249,7 @@
 	u8 reg8;
 	u32 reg32;
 
-	printk_debug ("Initializing System Memory IO... \n");
+	printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
 	/* Enable Data Half Clock Pushout */
 	reg8 = MCHBAR8(C0HCTC);
 	reg8 &= ~0x1f;
@@ -1291,7 +1291,7 @@
 {
 	u32 reg32;
 
-	printk_debug ("Enabling System Memory IO... \n");
+	printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
 
 	reg32 = MCHBAR32(RCVENMT);
 	reg32 &= ~(0x3f << 6);
@@ -1401,7 +1401,7 @@
 	/* Don't die here, I have not come across any of these to test what
 	 * actually happens.
 	 */
-	printk_err("Assymetric DIMMs are not supported by this chipset\n");
+	printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
 
 	sz.side2 -= (rows & 0x0f);		/* Subtract out rows on side 1 */
 	sz.side2 += ((rows >> 4) & 0x0f);	/* Add in rows on side 2 */
@@ -1445,7 +1445,7 @@
 
 		sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
 
-		printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
+		printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
 
 		if (!sz.side2)
 			continue;
@@ -1456,7 +1456,7 @@
 
 		sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
 
-		printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
+		printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
 	}
 }
 
@@ -1465,7 +1465,7 @@
 	int i;
 	int cum0, cum1, tolud, tom;
 
-	printk_debug ("Setting RAM size... \n");
+	printk(BIOS_DEBUG, "Setting RAM size... \n");
 
 	cum0 = 0;
 	for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
@@ -1507,9 +1507,9 @@
 
 	pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
 
-	printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
-	printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
-	printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
+	printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
+	printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
+	printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
 
 	pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
 
@@ -1521,7 +1521,7 @@
 	int i, value;
 	u16 dra0=0, dra1=0, dra = 0;
 
-	printk_debug ("Setting row attributes... \n");
+	printk(BIOS_DEBUG, "Setting row attributes... \n");
 	for(i=0; i < 2 * DIMM_SOCKETS; i++) {
 		u16 device;
 		u8 columnsrows;
@@ -1561,8 +1561,8 @@
 	MCHBAR16(C0DRA0) = dra0;
 	MCHBAR16(C1DRA0) = dra1;
 
-	printk_debug("C0DRA = 0x%04x\n", dra0);
-	printk_debug("C1DRA = 0x%04x\n", dra1);
+	printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
+	printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
 
 	return 0;
 }
@@ -1587,7 +1587,7 @@
 		if (sysinfo->banks[i] != 8)
 			continue;
 
-		printk_spew("DIMM%d has 8 banks.\n", i);
+		printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
 
 		if (i & 1)
 			MCHBAR16(off32) |= 0x50;
@@ -1852,7 +1852,7 @@
 {
 	u32 reg32;
 
-	printk_debug("Setting mode of operation for memory channels...");
+	printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
 
 	if (sdram_capabilities_interleave() &&
 		    ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
@@ -1870,21 +1870,21 @@
 
 	if(sysinfo->interleaved) {
 		/* Dual Channel Interleaved */
-		printk_debug("Dual Channel Interleaved.\n");
+		printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
 		reg32 |= (1 << 1);
 	} else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
 		/* Channel 1 only */
-		printk_debug("Single Channel 1 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 1 only.\n");
 		reg32 |= (1 << 2);
 	} else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
 			SYSINFO_DIMM_NOT_POPULATED) {
 		/* Dual Channel Assymetric */
-		printk_debug("Dual Channel Assymetric.\n");
+		printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
 		reg32 |= (1 << 0);
 	} else {
 		/* All bits 0 means Single Channel 0 operation */
-		printk_debug("Single Channel 0 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 0 only.\n");
 	}
 
 	reg32 |= (1 << 10);
@@ -1934,14 +1934,14 @@
 #define VOLTAGE_1_05	0x00
 #define VOLTAGE_1_50	0x01
 
-	printk_debug ("Setting Graphics Frequency... \n");
+	printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
 
-	printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
+	printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
 
 	voltage = VOLTAGE_1_05;
 	if (MCHBAR32(DFT_STRAP1) & (1 << 20))
 		voltage = VOLTAGE_1_50;
-	printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
+	printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
 
 	/* Gate graphics hardware for frequency change */
 	reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
@@ -1971,12 +1971,12 @@
 			freq = CRCLK_166MHz;
 	}
 
-	printk_debug("Render: ");
+	printk(BIOS_DEBUG, "Render: ");
 	switch (freq) {
-	case CRCLK_166MHz: printk_debug("166Mhz"); break;
-	case CRCLK_200MHz: printk_debug("200Mhz"); break;
-	case CRCLK_250MHz: printk_debug("250Mhz"); break;
-	case CRCLK_400MHz: printk_debug("400Mhz"); break;
+	case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
+	case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
+	case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
+	case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
 	}
 
 	if (i945_silicon_revision() == 0) {
@@ -2021,10 +2021,10 @@
 
 	if (voltage == VOLTAGE_1_05) {
 		reg8 |= CDCLK_200MHz;
-		printk_debug(" Display: 200MHz\n");
+		printk(BIOS_DEBUG, " Display: 200MHz\n");
 	} else {
 		reg8 |= CDCLK_320MHz;
-		printk_debug(" Display: 320MHz\n");
+		printk(BIOS_DEBUG, " Display: 320MHz\n");
 	}
 	pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
 
@@ -2050,21 +2050,21 @@
 	offset++;
 #endif
 
-	printk_debug ("Setting Memory Frequency... ");
+	printk(BIOS_DEBUG, "Setting Memory Frequency... ");
 
 	clkcfg = MCHBAR32(CLKCFG);
 
-	printk_debug("CLKCFG=0x%08x, ", clkcfg);
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
 
 	clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
 
 	if (sysinfo->mvco4x) {
-		printk_debug("MVCO 4x, ");
+		printk(BIOS_DEBUG, "MVCO 4x, ");
 		clkcfg &= ~(1 << 12);
 	}
 
 	if (sysinfo->clkcfg_bit7) {
-		printk_debug("second VCO, ");
+		printk(BIOS_DEBUG, "second VCO, ");
 
 		clkcfg |= (1 << 7);
 	}
@@ -2077,7 +2077,7 @@
 	}
 
 	if (MCHBAR32(CLKCFG) == clkcfg) {
-		printk_debug ("ok (unchanged)\n");
+		printk(BIOS_DEBUG, "ok (unchanged)\n");
 		return;
 	}
 
@@ -2118,8 +2118,8 @@
 	goto vco_update;
 out:
 
-	printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
-	printk_debug ("ok\n");
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
+	printk(BIOS_DEBUG, "ok\n");
 }
 
 static void sdram_program_clock_crossing(void)
@@ -2222,28 +2222,28 @@
 	};
 #endif
 
-	printk_debug("Programming Clock Crossing...");
+	printk(BIOS_DEBUG, "Programming Clock Crossing...");
 
-	printk_debug("MEM=");
+	printk(BIOS_DEBUG, "MEM=");
 	switch (memclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 2; break;
-	case 667:	printk_debug("667"); idx += 4; break;
-	default: printk_debug("RSVD %x", memclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 2; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 4; break;
+	default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
 	}
 
-	printk_debug(" FSB=");
+	printk(BIOS_DEBUG, " FSB=");
 	switch (fsbclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 6; break;
-	case 667:	printk_debug("667"); idx += 12; break;
-	case 800:	printk_debug("800"); idx += 18; break;
-	case 1066:	printk_debug("1066"); idx += 24; break;
-	default: printk_debug("RSVD %x\n", fsbclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 6; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 12; break;
+	case 800:	printk(BIOS_DEBUG, "800"); idx += 18; break;
+	case 1066:	printk(BIOS_DEBUG, "1066"); idx += 24; break;
+	default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
 	}
 
 	if (command_clock_crossing[idx]==0xffffffff) {
-		printk_debug("Invalid MEM/FSB combination!\n");
+		printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
 	}
 
 	MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
@@ -2254,7 +2254,7 @@
 	MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
 	MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
 
-	printk_debug("... ok\n");
+	printk(BIOS_DEBUG, "... ok\n");
 }
 
 static void sdram_disable_fast_dispatch(void)
@@ -2569,7 +2569,7 @@
 #ifdef C2_SELF_REFRESH_DISABLE
 
 	if (integrated_graphics) {
-		printk_debug("C2 self-refresh with IGD\n");
+		printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
 		MCHBAR16(MIPMC4) = 0x0468;
 		MCHBAR16(MIPMC5) = 0x046c;
 		MCHBAR16(MIPMC6) = 0x046c;
@@ -2728,7 +2728,7 @@
 
 	if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
-		printk_debug("one dimm per channel config.. \n");
+		printk(BIOS_DEBUG, "one dimm per channel config.. \n");
 
 		reg32 = MCHBAR32(C0ODT);
 		reg32 &= ~(7 << 28);
@@ -2832,7 +2832,7 @@
 			continue;
 		}
 
-		printk_debug("jedec enable sequence: bank %d\n", i);
+		printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
 		switch (i) {
 		case 0:
 			/* Start at address 0 */
@@ -2845,7 +2845,7 @@
 			}
 		default:
 			if (nonzero != -1) {
-				printk_debug("bankaddr from bank size of rank %d\n", nonzero);
+				printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
 				bankaddr += sysinfo->banksize[nonzero] <<
 					(sysinfo->interleaved ? 26 : 25);
 				break;
@@ -3010,7 +3010,7 @@
 
 	sdram_detect_errors();
 
-	printk_debug ("Setting up RAM controller.\n");
+	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
 	memset(&sysinfo, 0, sizeof(sysinfo));
 
@@ -3131,7 +3131,7 @@
 	reg8 &= ~(1 << 7);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 
-	printk_debug("RAM initialization finished.\n");
+	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
 	sdram_setup_processor_side();
 }
Index: src/northbridge/intel/i945/northbridge.c
===================================================================
--- src/northbridge/intel/i945/northbridge.c	(revision 5263)
+++ src/northbridge/intel/i945/northbridge.c	(working copy)
@@ -75,11 +75,11 @@
 {
 	u32 pcie_config_base, pcie_config_size;
 
-	printk_debug("Adding UMA memory area\n");
+	printk(BIOS_DEBUG, "Adding UMA memory area\n");
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
 
-	printk_debug("Adding PCIe config bar\n");
+	printk(BIOS_DEBUG, "Adding PCIe config bar\n");
 	get_pcie_bar(&pcie_config_base, &pcie_config_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		pcie_config_base, pcie_config_size);
@@ -140,13 +140,13 @@
 	 * this way?
 	 */
 	pci_tolm = find_pci_tolm(&dev->link[0]);
-	printk_debug("pci_tolm: 0x%x\n", pci_tolm);
+	printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
 
-	printk_spew("Base of stolen memory: 0x%08x\n",
+	printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
 		    pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
 
 	tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
-	printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
+	printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
 
 	tomk = tolud << 14;
 
@@ -154,7 +154,7 @@
 	reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
 	if (reg8 & 1) {
 		int tseg_size = 0;
-		printk_debug("TSEG decoded, subtracting ");
+		printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
 		reg8 >>= 1;
 		reg8 &= 3;
 		switch (reg8) {
@@ -169,14 +169,14 @@
 			break;	/* TSEG = 8M */
 		}
 
-		printk_debug("%dM\n", tseg_size >> 10);
+		printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
 		tomk -= tseg_size;
 	}
 
 	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
 	if (!(reg16 & 2)) {
 		int uma_size = 0;
-		printk_debug("IGD decoded, subtracting ");
+		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 		reg16 >>= 4;
 		reg16 &= 7;
 		switch (reg16) {
@@ -188,7 +188,7 @@
 			break;
 		}
 
-		printk_debug("%dM UMA\n", uma_size >> 10);
+		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
 		tomk -= uma_size;
 
 		/* For reserving UMA memory in the memory map */
@@ -199,8 +199,8 @@
 	/* The following needs to be 2 lines, otherwise the second
 	 * number is always 0
 	 */
-	printk_info("Available memory: %dK", (uint32_t)tomk);
-	printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
+	printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
+	printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
 
 	/* Report the memory regions */
 	ram_resource(dev, 3, 0, 640);
@@ -253,7 +253,7 @@
 	resource->flags =
 	    IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
 	    IORESOURCE_ASSIGNED;
-	printk_debug("Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
 		     (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
 }
 
@@ -289,15 +289,15 @@
 {
 	switch (pci_read_config32(dev, SKPAD)) {
 	case 0xcafebabe:
-		printk_debug("Normal boot.\n");
+		printk(BIOS_DEBUG, "Normal boot.\n");
 		acpi_slp_type=0;
 		break;
 	case 0xcafed00d:
-		printk_debug("S3 Resume.\n");
+		printk(BIOS_DEBUG, "S3 Resume.\n");
 		acpi_slp_type=3;
 		break;
 	default:
-		printk_debug("Unknown boot method, assuming normal.\n");
+		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
 		acpi_slp_type=0;
 		break;
 	}
Index: src/northbridge/intel/i945/rcven.c
===================================================================
--- src/northbridge/intel/i945/rcven.c	(revision 5263)
+++ src/northbridge/intel/i945/rcven.c	(working copy)
@@ -67,7 +67,7 @@
 {
 	u32 reg32;
 
-	printk_spew("    set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
+	printk(BIOS_SPEW, "    set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
 
 	reg32 = MCHBAR32(C0DRT1 + channel_offset);
 	reg32 &= 0xf0ffffff;
@@ -76,7 +76,7 @@
 
 	/* This should never happen: */
 	if (coarse > 0x0f)
-		printk_debug("set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
+		printk(BIOS_DEBUG, "set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
 
 	/* medium control
 	 *
@@ -102,7 +102,7 @@
 
 static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
 {
-	printk_spew("  normalize()\n");
+	printk(BIOS_SPEW, "  normalize()\n");
 
 	if (*fine < 0x80)
 		return 0;
@@ -111,7 +111,7 @@
 	*mediumcoarse += 1;
 
 	if (*mediumcoarse >= 0x40) {
-		printk_debug("Normalize Error\n");
+		printk(BIOS_DEBUG, "Normalize Error\n");
 		return -1;
 	}
 
@@ -129,11 +129,11 @@
 	/* find start of the data phase */
 	u32 reg32;
 
-	printk_spew("  find_preamble()\n");
+	printk(BIOS_SPEW, "  find_preamble()\n");
 
 	do {
 		if (*mediumcoarse < 4) {
-			printk_debug("No Preamble found.\n");
+			printk(BIOS_DEBUG, "No Preamble found.\n");
 			return -1;
 		}
 		*mediumcoarse -= 4;
@@ -146,7 +146,7 @@
 	} while (reg32 & (1 << 19));
 
 	if (!(reg32 & (1 << 18))) {
-		printk_debug("No Preamble found (neither high nor low).\n");
+		printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\n");
 		return -1;
 	}
 
@@ -159,14 +159,14 @@
 
 static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
 {
-	printk_spew("  add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
+	printk(BIOS_SPEW, "  add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
 			*mediumcoarse, *fine);
 	if (*fine >= 0x80) {
 		*fine -= 0x80;
 
 		*mediumcoarse += 2;
 		if (*mediumcoarse >= 0x40) {
-			printk_debug("clocks at max.\n");
+			printk(BIOS_DEBUG, "clocks at max.\n");
 			return -1;
 		}
 
@@ -186,7 +186,7 @@
 {
 	u32 rcvenmt;
 
-	printk_spew("  find_strobes_low()\n");
+	printk(BIOS_SPEW, "  find_strobes_low()\n");
 
 	for (;;) {
 		MCHBAR8(C0WL0REOST + channel_offset) = *fine;
@@ -211,7 +211,7 @@
 
 	}
 
-	printk_debug("Could not find low strobe\n");
+	printk(BIOS_DEBUG, "Could not find low strobe\n");
 	return 0;
 }
 
@@ -222,7 +222,7 @@
 	int counter;
 	u32 rcvenmt;
 
-	printk_spew("  find_strobes_edge()\n");
+	printk(BIOS_SPEW, "  find_strobes_edge()\n");
 
 	counter = 8;
 	set_receive_enable(channel_offset, *mediumcoarse & 3,
@@ -257,7 +257,7 @@
 			continue;
 		}
 
-		printk_debug("Could not find rising edge.\n");
+		printk(BIOS_DEBUG, "Could not find rising edge.\n");
 		return -1;
 	}
 
@@ -286,7 +286,7 @@
 	u8 mediumcoarse;
 	u8 fine;
 
-	printk_spew("receive_enable_autoconfig() for channel %d\n",
+	printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n",
 		    channel_offset ? 1 : 0);
 
 	/* Set initial values */
@@ -315,7 +315,7 @@
 	 * It can be removed when the output message is not printed anymore
 	 */
 	if (MCHBAR8(C0WL0REOST + channel_offset) == 0) {
-		printk_debug("Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
+		printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
 	}
 
 	return 0;
Index: src/northbridge/intel/i945/debug.c
===================================================================
--- src/northbridge/intel/i945/debug.c	(revision 5263)
+++ src/northbridge/intel/i945/debug.c	(working copy)
@@ -36,9 +36,9 @@
 			(((id >> 16) & 0xffff) == 0x0000)) {
 			continue;
 		}
-		printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
+		printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
 			(dev >> 15) & 0x1f, (dev >> 12) & 7);
-		printk_debug(" [%04x:%04x]\n", id &0xffff, id >> 16);
+		printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16);
 	}
 }
 
@@ -46,17 +46,17 @@
 {
 	int i;
 
-	printk_debug("PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
 
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = pci_read_config8(dev, i);
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 		if ((i & 0x0f) == 0x0f) {
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
 	}
 }
@@ -85,21 +85,21 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	printk_debug("\ndimm %02x", device);
+        	printk(BIOS_DEBUG, "\ndimm %02x", device);
 		
                 for(i = 0; (i < 256) ; i++) {
                         if ((i % 16) == 0) {
-				printk_debug("\n%02x: ", i);
+				printk(BIOS_DEBUG, "\n%02x: ", i);
                         }
 			status = smbus_read_byte(device, i);
                         if (status < 0) {
-			         printk_debug("bad device: %02x\n", -status);
+			         printk(BIOS_DEBUG, "bad device: %02x\n", -status);
 			         break; 
 			}
-			printk_debug("%02x ", status);
+			printk(BIOS_DEBUG, "%02x ", status);
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 
@@ -109,9 +109,9 @@
 	print_debug("dump_mem:");
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
         }
         print_debug("\n");
  }
Index: src/northbridge/intel/i855/northbridge.c
===================================================================
--- src/northbridge/intel/i855/northbridge.c	(revision 5263)
+++ src/northbridge/intel/i855/northbridge.c	(working copy)
@@ -79,13 +79,13 @@
 	device_t mc_dev;
         uint32_t pci_tolm;
         
-        printk_debug("Entered with dev vid = %x\n", dev->vendor);
-	printk_debug("Entered with dev did = %x\n", dev->device);
+        printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
+	printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
 
         pci_tolm = find_pci_tolm(&dev->link[0]);	
 	mc_dev = dev->link[0].children->sibling;
-	printk_debug("MC dev vendor = %x\n", mc_dev->vendor);
-	printk_debug("MC dev device = %x\n", mc_dev->device);
+	printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
+	printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
 	
 	if (mc_dev) {
 		/* Figure out which areas are/should be occupied by RAM.
@@ -120,8 +120,8 @@
 		 */
 		 
 		/* Report the memory regions */
-		printk_debug("tomk = %d\n", tomk);
-		printk_debug("tolmk = %d\n", tolmk);
+		printk(BIOS_DEBUG, "tomk = %d\n", tomk);
+		printk(BIOS_DEBUG, "tolmk = %d\n", tolmk);
 
 		idx = 10;
 		/* avoid pam region */
Index: src/northbridge/intel/i82810/northbridge.c
===================================================================
--- src/northbridge/intel/i82810/northbridge.c	(revision 5263)
+++ src/northbridge/intel/i82810/northbridge.c	(working copy)
@@ -34,7 +34,7 @@
 
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge init\n");
+	printk(BIOS_SPEW, "Northbridge init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -142,7 +142,7 @@
 		drp_value = drp_value >> 4;	// >>= 4; //? mess with later
 		tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
 
-		printk_debug("Setting RAM size to %d MB\n", tomk);
+		printk(BIOS_DEBUG, "Setting RAM size to %d MB\n", tomk);
 
 		/* Convert tomk from MB to KB. */
 		tomk = tomk << 10;
@@ -151,12 +151,12 @@
 		/* Check for VGA reserved memory. */
 		if (CONFIG_VIDEO_MB == 512) {
 			tomk -= 512;
-			printk_debug("Allocating %s RAM for VGA\n", "512KB");
+			printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "512KB");
 		} else if (CONFIG_VIDEO_MB == 1) {
 			tomk -= 1024 ;
-			printk_debug("Allocating %s RAM for VGA\n", "1MB");
+			printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "1MB");
 		} else {
-			printk_debug("Allocating %s RAM for VGA\n", "0MB");
+			printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "0MB");
 		}
 #endif
 
Index: src/northbridge/intel/i3100/pciexp_porta_ep80579.c
===================================================================
--- src/northbridge/intel/i3100/pciexp_porta_ep80579.c	(revision 5263)
+++ src/northbridge/intel/i3100/pciexp_porta_ep80579.c	(working copy)
@@ -44,7 +44,7 @@
 		pci_write_config32(dev, 0x3c, config->intrline);
 	}
 
-	printk_spew("configure PCIe port as \"Slot Implemented\"\n");
+	printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n");
 	val = pci_read_config16(dev, 0x66);
 	val &= ~(1<<8);
 	val |= 1<<8;
@@ -58,7 +58,7 @@
 {
 	u8 val8;
 	if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-		printk_spew("Enable VGA IO/MEM forwarding on PCIe port\n");
+		printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n");
 		pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8);
 		
 		dev->command |= PCI_COMMAND_IO;
@@ -76,12 +76,12 @@
 	int flag = 0;
 	do {
 		val = pci_read_config16(dev, 0x76);
-		printk_debug("pcie porta 0x76: %02x\n", val);
+		printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
 		if ((val & (1<<11)) && (!flag)) { /* training error */
 			ctl = pci_read_config16(dev, 0x74);
 			pci_write_config16(dev, 0x74, (ctl | (1<<5)));
 			val = pci_read_config16(dev, 0x76);
-			printk_debug("pcie porta reset 0x76: %02x\n", val);
+			printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
 			flag=1;
 			hard_reset();
 		}
Index: src/northbridge/intel/i3100/northbridge.c
===================================================================
--- src/northbridge/intel/i3100/northbridge.c	(revision 5263)
+++ src/northbridge/intel/i3100/northbridge.c	(working copy)
@@ -86,7 +86,7 @@
         pci_tolm = find_pci_tolm(&dev->link[0]);
 
 #if 1
-	printk_debug("PCI mem marker = %x\n", pci_tolm);
+	printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
 #endif
 	/* FIXME Me temporary hack */
 	if(pci_tolm > 0xe0000000)
Index: src/northbridge/intel/i3100/pciexp_porta.c
===================================================================
--- src/northbridge/intel/i3100/pciexp_porta.c	(revision 5263)
+++ src/northbridge/intel/i3100/pciexp_porta.c	(working copy)
@@ -52,12 +52,12 @@
 	int flag = 0;
 	do {
 		val = pci_read_config16(dev, 0x76);
-		printk_debug("pcie porta 0x76: %02x\n", val);
+		printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
 		if ((val & (1<<10)) && (!flag)) { /* training error */
 			ctl = pci_read_config16(dev, 0x74);
 			pci_write_config16(dev, 0x74, (ctl | (1<<5)));
 			val = pci_read_config16(dev, 0x76);
-			printk_debug("pcie porta reset 0x76: %02x\n", val);
+			printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
 			flag=1;
 			hard_reset();
 		}
Index: src/northbridge/intel/i82830/i82830_smihandler.c
===================================================================
--- src/northbridge/intel/i82830/i82830_smihandler.c	(revision 5263)
+++ src/northbridge/intel/i82830/i82830_smihandler.c	(working copy)
@@ -80,17 +80,17 @@
 static void
 dump(u8 * addr, u32 len)
 {
-	printk_debug("\n%s(%p, %x):\n", __func__, addr, len);
+	printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
 	while (len) {
 		unsigned int tmpCnt = len;
 		unsigned char x;
 		if (tmpCnt > 8)
 			tmpCnt = 8;
-		printk_debug("\n%p: ", addr);
+		printk(BIOS_DEBUG, "\n%p: ", addr);
 		// print hex
 		while (tmpCnt--) {
 			x = *addr++;
-			printk_debug("%02x ", x);
+			printk(BIOS_DEBUG, "%02x ", x);
 		}
 		tmpCnt = len;
 		if (tmpCnt > 8)
@@ -105,10 +105,10 @@
 				//non-printable char
 				x = '.';
 			}
-			printk_debug("%c", x);
+			printk(BIOS_DEBUG, "%c", x);
 		}
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 #endif
 
@@ -150,19 +150,19 @@
 static void mbi_call(u8 subf, banner_id_t *banner_id)
 {
 #ifdef DEBUG_SMI_I82830
-	printk_debug("MBI\n");
-	printk_debug("|- sub function %x\n", subf);
-	printk_debug("|- banner id @ %x\n", (u32)banner_id);
-	printk_debug("|  |- mhid %x\n", banner_id->mhid);
-	printk_debug("|  |- function %x\n", banner_id->function);
-	printk_debug("|  |- return status %x\n", banner_id->retsts);
-	printk_debug("|  |- rfu %x\n", banner_id->rfu);
+	printk(BIOS_DEBUG, "MBI\n");
+	printk(BIOS_DEBUG, "|- sub function %x\n", subf);
+	printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
+	printk(BIOS_DEBUG, "|  |- mhid %x\n", banner_id->mhid);
+	printk(BIOS_DEBUG, "|  |- function %x\n", banner_id->function);
+	printk(BIOS_DEBUG, "|  |- return status %x\n", banner_id->retsts);
+	printk(BIOS_DEBUG, "|  |- rfu %x\n", banner_id->rfu);
 #endif
 
 	switch(banner_id->function) {
 	case 0x0001: {
 		version_t *version;
-		printk_debug("|- MBI_QueryInterface\n");
+		printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
 		version = (version_t *)banner_id;
 		version->banner.retsts = MSH_OK;
 		version->versionmajor=1;
@@ -171,18 +171,18 @@
 		break;
 	}
 	case 0x0002:
-		printk_debug("|- MBI_Attach\n");
-		printk_debug("|  |- Not Implemented!\n");
+		printk(BIOS_DEBUG, "|- MBI_Attach\n");
+		printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
 		break;
 	case 0x0003:
-		printk_debug("|- MBI_Detach\n");
-		printk_debug("|  |- Not Implemented!\n");
+		printk(BIOS_DEBUG, "|- MBI_Detach\n");
+		printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
 		break;
 	case 0x0201: {
 		obj_header_t *obj_header = (obj_header_t *)banner_id;
 		mbi_header_t *mbi_header = NULL;
-		printk_debug("|- MBI_GetObjectHeader\n");
-		printk_debug("|  |- objnum = %d\n", obj_header->objnum);
+		printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
+		printk(BIOS_DEBUG, "|  |- objnum = %d\n", obj_header->objnum);
 
 		int i, count=0;
 		obj_header->banner.retsts = MSH_IF_NOT_FOUND;
@@ -201,15 +201,15 @@
 			if (obj_header->objnum == count) {
 				int headerlen = ALIGN(sizeof(mbi_header) + mbi_header->name_len + 15, 16);
 #ifdef DEBUG_SMI_I82830
-				printk_debug("|  |- headerlen = %d\n", headerlen);
+				printk(BIOS_DEBUG, "|  |- headerlen = %d\n", headerlen);
 #endif
 				memcpy(&obj_header->header, mbi_header, headerlen);
 				obj_header->banner.retsts = MSH_OK;
-				printk_debug("|     |- MBI module '");
+				printk(BIOS_DEBUG, "|     |- MBI module '");
 				int j;
 				for (j=0; j < mbi_header->name_len && mbi_header->name[j]; j++)
-					printk_debug("%c",  mbi_header->name[j]);
-				printk_debug("' found.\n");
+					printk(BIOS_DEBUG, "%c",  mbi_header->name[j]);
+				printk(BIOS_DEBUG, "' found.\n");
 #ifdef DEBUG_SMI_I82830
 				dump(banner_id, sizeof(obj_header_t) + 16);
 #endif
@@ -219,21 +219,21 @@
 			count++;
 		}
 		if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) 
-			printk_debug("|     |- MBI object #%d not found.\n", obj_header->objnum);
+			printk(BIOS_DEBUG, "|     |- MBI object #%d not found.\n", obj_header->objnum);
 		break;
 	}
 	case 0x0203: {
 		get_object_t *getobj = (get_object_t *)banner_id;
 		mbi_header_t *mbi_header = NULL;
-		printk_debug("|- MBI_GetObject\n");
+		printk(BIOS_DEBUG, "|- MBI_GetObject\n");
 #ifdef DEBUG_SMI_I82830
-		printk_debug("|  |- handle = %016lx\n", getobj->handle);
+		printk(BIOS_DEBUG, "|  |- handle = %016lx\n", getobj->handle);
 #endif
-		printk_debug("|  |- objnum = %d\n", getobj->objnum);
-		printk_debug("|  |- start = %x\n", getobj->start);
-		printk_debug("|  |- numbytes = %x\n", getobj->numbytes);
-		printk_debug("|  |- buflen = %x\n", getobj->buflen);
-		printk_debug("|  |- buffer = %x\n", getobj->buffer);
+		printk(BIOS_DEBUG, "|  |- objnum = %d\n", getobj->objnum);
+		printk(BIOS_DEBUG, "|  |- start = %x\n", getobj->start);
+		printk(BIOS_DEBUG, "|  |- numbytes = %x\n", getobj->numbytes);
+		printk(BIOS_DEBUG, "|  |- buflen = %x\n", getobj->buflen);
+		printk(BIOS_DEBUG, "|  |- buffer = %x\n", getobj->buffer);
 
 		int i, count=0;
 		getobj->banner.retsts = MSH_IF_NOT_FOUND;
@@ -250,7 +250,7 @@
 			len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16);
 			
 			if (getobj->objnum == count) {
-				printk_debug("|  |- len = %x\n", len);
+				printk(BIOS_DEBUG, "|  |- len = %x\n", len);
 				memcpy((void *)(getobj->buffer + OBJ_OFFSET),
 						((char *)mbi_header) + 0x20 , (len > getobj->buflen ? getobj->buflen : len));
 
@@ -264,15 +264,15 @@
 			count++;
 		}
 		if (getobj->banner.retsts == MSH_IF_NOT_FOUND) 
-			printk_debug("MBI module %d not found.\n", getobj->objnum);
+			printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
 		break;
 	}
 	default:
-		printk_debug("|- function %x\n", banner_id->function);
-		printk_debug("|  |- Unknown Function!\n");
+		printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
+		printk(BIOS_DEBUG, "|  |- Unknown Function!\n");
 		break;
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	//dump(banner_id, 0x20);
 }
 
@@ -291,7 +291,7 @@
 {
 	u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
 	// mmio &= 0xfff80000;
-	// printk_debug("mmio=%x\n", mmio);
+	// printk(BIOS_DEBUG, "mmio=%x\n", mmio);
 	u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
 
 	if (!(swsmi & 1))
@@ -301,7 +301,7 @@
 
 	switch ((swsmi>>1) & 0xf) {
 	case 0:
-		printk_debug("Interface Function Presence Test.\n");
+		printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
 		swsmi = 0;
 		swsmi &= ~(7 << 5); // Exit: Result
 		swsmi |= (SMI_IFC_SUCCESS << 5);
@@ -312,11 +312,11 @@
 		write32(mmio + 0x71428, 0x494e5443);
 		return;
 	case 4:
-		printk_debug("Get BIOS Data.\n");
-		printk_debug("swsmi=%04x\n", swsmi);
+		printk(BIOS_DEBUG, "Get BIOS Data.\n");
+		printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
 		break;
 	case 5:
-		printk_debug("Call MBI Functions.\n");
+		printk(BIOS_DEBUG, "Call MBI Functions.\n");
 		mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
 		// swsmi = 0x0000;
 		swsmi &= ~(7 << 5); // Exit: Result
@@ -324,11 +324,11 @@
 		pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
 		return;
 	case 6:
-		printk_debug("System BIOS Callbacks.\n");
-		printk_debug("swsmi=%04x\n", swsmi);
+		printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
+		printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
 		break;
 	default:
-		printk_debug("Unknown SMI interface call %04x\n", swsmi);
+		printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
 		break;
 	}
 
@@ -354,15 +354,15 @@
 
 static void dump_err_status(u32 errsts)
 {
-	printk_debug("ERRSTS: ");
-	if (errsts & (1 << 12)) printk_debug("MBI ");
-	if (errsts & (1 <<  9)) printk_debug("LCKF ");
-	if (errsts & (1 <<  8)) printk_debug("DTF ");
-	if (errsts & (1 <<  5)) printk_debug("UNSC ");
-	if (errsts & (1 <<  4)) printk_debug("OOGF ");
-	if (errsts & (1 <<  3)) printk_debug("IAAF ");
-	if (errsts & (1 <<  2)) printk_debug("ITTEF ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "ERRSTS: ");
+	if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
+	if (errsts & (1 <<  9)) printk(BIOS_DEBUG, "LCKF ");
+	if (errsts & (1 <<  8)) printk(BIOS_DEBUG, "DTF ");
+	if (errsts & (1 <<  5)) printk(BIOS_DEBUG, "UNSC ");
+	if (errsts & (1 <<  4)) printk(BIOS_DEBUG, "OOGF ");
+	if (errsts & (1 <<  3)) printk(BIOS_DEBUG, "IAAF ");
+	if (errsts & (1 <<  2)) printk(BIOS_DEBUG, "ITTEF ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
Index: src/northbridge/intel/i82830/northbridge.c
===================================================================
--- src/northbridge/intel/i82830/northbridge.c	(revision 5263)
+++ src/northbridge/intel/i82830/northbridge.c	(working copy)
@@ -35,7 +35,7 @@
 
 static void northbridge_init(device_t dev)
 {
-	printk_spew("Northbridge init\n");
+	printk(BIOS_SPEW, "Northbridge init\n");
 }
 
 static struct device_operations northbridge_operations = {
@@ -95,7 +95,7 @@
 
 int add_northbridge_resources(struct lb_memory *mem)
 {
-	printk_debug("Adding IGD UMA memory area\n");
+	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
 
@@ -120,10 +120,10 @@
 
 		if (CONFIG_VIDEO_MB == 512) {
 			igd_memory = (CONFIG_VIDEO_MB);
-			printk_debug("%dKB IGD UMA\n", igd_memory >> 10);
+			printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
 		} else {
 			igd_memory = (CONFIG_VIDEO_MB * 1024);
-			printk_debug("%dMB IGD UMA\n", igd_memory >> 10);
+			printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
 		}
 
 		/* Get the value of the highest DRB. This tells the end of
@@ -136,7 +136,7 @@
 		/* For reserving UMA memory in the memory map */
 		uma_memory_base = tomk * 1024ULL;
 		uma_memory_size = igd_memory * 1024ULL;
-		printk_debug("Available memory: %ldKB\n", tomk);
+		printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
 
 		/* Compute the top of low memory. */
 		tolmk = pci_tolm >> 10;
Index: src/northbridge/intel/i82830/vga.c
===================================================================
--- src/northbridge/intel/i82830/vga.c	(revision 5263)
+++ src/northbridge/intel/i82830/vga.c	(working copy)
@@ -31,21 +31,21 @@
 
 static void vga_init(device_t dev)
 {
-	printk_info("Starting Graphics Initialization\n");
+	printk(BIOS_INFO, "Starting Graphics Initialization\n");
 	struct cbfs_file *file = cbfs_find("mbi.bin");
 	void *mbi = NULL;
 	unsigned int mbi_len = 0;
 
 	if (file) {
 		if (ntohl(file->type) != CBFS_TYPE_MBI) {
-			printk_info( "CBFS:  MBI binary is of type %x instead of"
+			printk(BIOS_INFO,  "CBFS:  MBI binary is of type %x instead of"
 			       "type %x\n", file->type, CBFS_TYPE_MBI);
 		} else {
 			mbi = (void *) CBFS_SUBHEADER(file);
 			mbi_len = file->len;
 		}
 	} else {
-		printk_info( "Could not find MBI.\n");
+		printk(BIOS_INFO,  "Could not find MBI.\n");
 	}
 
 	if (mbi && mbi_len) {
@@ -59,7 +59,7 @@
 	}
 
 	pci_dev_init(dev);
-	printk_info("Graphics Initialization Complete\n");
+	printk(BIOS_INFO, "Graphics Initialization Complete\n");
 
 	/* Enable TV-Out */
 #if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -68,7 +68,7 @@
 #define PIPE_A_TV	(1 << 3)
 #define PIPE_B_CRT	(1 << 8)
 #define PIPE_B_TV	(1 << 10)
-	printk_debug("Enabling TV-Out\n"); 
+	printk(BIOS_DEBUG, "Enabling TV-Out\n"); 
 	void runInt10(void);
 	M.x86.R_AX = 0x5f64;
 	M.x86.R_BX = 0x0001; // Set Display Device, force execution
@@ -77,13 +77,13 @@
 	runInt10();
 	switch (M.x86.R_AX) {
 	case 0x005f:
-		printk_debug("... failed.\n");
+		printk(BIOS_DEBUG, "... failed.\n");
 		break;
 	case 0x015f:
-		printk_debug("... ok.\n");
+		printk(BIOS_DEBUG, "... ok.\n");
 		break;
 	default:
-		printk_debug("... not supported.\n");
+		printk(BIOS_DEBUG, "... not supported.\n");
 		break;
 	}
 #endif
Index: src/pc80/i8259.c
===================================================================
--- src/pc80/i8259.c	(revision 5263)
+++ src/pc80/i8259.c	(working copy)
@@ -113,26 +113,26 @@
 {
 	u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
 
-	printk_spew("%s: current interrupts are 0x%x\n", __func__, int_bits);
+	printk(BIOS_SPEW, "%s: current interrupts are 0x%x\n", __func__, int_bits);
 	if (is_level_triggered)
 		int_bits |= (1 << int_num);
 	else
 		int_bits &= ~(1 << int_num);
 
 	/* Write new values */
-	printk_spew("%s: try to set interrupts 0x%x\n", __func__, int_bits);
+	printk(BIOS_SPEW, "%s: try to set interrupts 0x%x\n", __func__, int_bits);
 	outb((u8)(int_bits & 0xff), ELCR1);
 	outb((u8)(int_bits >> 8), ELCR2);
 
 #ifdef PARANOID_IRQ_TRIGGERS
 	/* Try reading back the new values. This seems like an error but is not ... */
 	if (inb(ELCR1) != (int_bits & 0xff)) {
-		printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
+		printk(BIOS_ERR, "%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
 				__func__, (int_bits & 0xff), inb(ELCR1));
 	}
 
 	if (inb(ELCR2) != (int_bits >> 8)) {
-		printk_err("%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
+		printk(BIOS_ERR, "%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
 				__func__, (int_bits>>8), inb(ELCR2));
 	}
 #endif
Index: src/pc80/keyboard.c
===================================================================
--- src/pc80/keyboard.c	(revision 5263)
+++ src/pc80/keyboard.c	(working copy)
@@ -71,7 +71,7 @@
 	}
 
 	if (!timeout) {
-		printk_warning("Unexpected Keyboard controller input buffer full\n");
+		printk(BIOS_WARNING, "Unexpected Keyboard controller input buffer full\n");
 	}
 	return !!timeout;
 }
@@ -85,7 +85,7 @@
 	}
 
 	if (!timeout) {
-		printk_warning("Keyboard controller output buffer result timeout\n");
+		printk(BIOS_WARNING, "Keyboard controller output buffer result timeout\n");
 	}
 	return !!timeout;
 }
@@ -100,8 +100,8 @@
 	}
 
 	if (!timeout) {
-		printk_err("Couldn't cleanup the keyboard controller buffers\n");
-		printk_err("Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n",
+		printk(BIOS_ERR, "Couldn't cleanup the keyboard controller buffers\n");
+		printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n",
 				KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA));
 	}
 
@@ -123,7 +123,7 @@
 
 	if (!kbc_output_buffer_full()) {
 		/* There probably is no keyboard controller. */
-		printk_err("Could not reset keyboard controller.\n");
+		printk(BIOS_ERR, "Could not reset keyboard controller.\n");
 		return 0;
 	}
 
@@ -131,7 +131,7 @@
 	self_test = inb(KBD_DATA);
 
 	if (self_test != 0x55) {
-		printk_err("Keyboard Controller self-test failed: 0x%x\n",
+		printk(BIOS_ERR, "Keyboard Controller self-test failed: 0x%x\n",
 				self_test);
 		return 0;
 	}
@@ -148,7 +148,7 @@
 		if (!kbc_input_buffer_empty()) return 0;
 		outb(command, KBD_DATA);
 		if (!kbc_output_buffer_full()) {
-			printk_err("Could not send keyboard command %02x\n",
+			printk(BIOS_ERR, "Could not send keyboard command %02x\n",
 					command);
 			return 0;
 		}
@@ -162,7 +162,7 @@
 void pc_keyboard_init(struct pc_keyboard *keyboard)
 {
 	u8 regval;
-	printk_debug("Keyboard init...\n");
+	printk(BIOS_DEBUG, "Keyboard init...\n");
 
 	/* Run a keyboard controller self-test */
 	if (!kbc_self_test())
@@ -174,7 +174,7 @@
 	if (!kbc_input_buffer_empty()) return;
 	outb(0x20, KBD_DATA);	/* send cmd: enable keyboard */
 	if (!kbc_input_buffer_empty()) {
-		printk_info("Timeout while enabling keyboard\n");
+		printk(BIOS_INFO, "Timeout while enabling keyboard\n");
 		return;
 	}
 
@@ -185,23 +185,23 @@
 	regval = send_keyboard(0xFF);
 	if (regval == KBD_REPLY_RESEND) {
 		/* keeps sending RESENDs, probably no keyboard. */
-		printk_info("No PS/2 keyboard detected.\n");
+		printk(BIOS_INFO, "No PS/2 keyboard detected.\n");
 		return;
 	}
 
 	if (regval != KBD_REPLY_ACK) {
-		printk_err("Keyboard selftest failed ACK: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard selftest failed ACK: 0x%x\n", regval);
 		return;
 	}
 
 	if (!kbc_output_buffer_full()) {
-		printk_err("Timeout waiting for keyboard after reset.\n");
+		printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n");
 		return;
 	}
 
 	regval = inb(KBD_DATA);
 	if (regval != 0xAA) {
-		printk_err("Keyboard selftest failed: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard selftest failed: 0x%x\n", regval);
 		return;
 	}
 
@@ -213,27 +213,27 @@
 	/* disable the keyboard */
 	regval = send_keyboard(0xF5);
 	if (regval != KBD_REPLY_ACK) {
-		printk_err("Keyboard disable failed ACK: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard disable failed ACK: 0x%x\n", regval);
 		return;
 	}
 
 	/* Set scancode command */
 	regval = send_keyboard(0xF0);
 	if (regval != KBD_REPLY_ACK) {
-		printk_err("Keyboard set scancode cmd failed ACK: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", regval);
 		return;
 	}
 	/* Set scancode mode 2 */
 	regval = send_keyboard(0x02);
 	if (regval != KBD_REPLY_ACK) {
-		printk_err("Keyboard set scancode mode failed ACK: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard set scancode mode failed ACK: 0x%x\n", regval);
 		return;
 	}
 
 	/* enable the keyboard */
 	regval = send_keyboard(0xF4);
 	if (regval != KBD_REPLY_ACK) {
-		printk_err("Keyboard enable failed ACK: 0x%x\n", regval);
+		printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval);
 		return;
 	}
 
@@ -243,7 +243,7 @@
 	if (!kbc_input_buffer_empty()) return;
 	outb(0x61, KBD_DATA);	/* send cmd: enable keyboard and IRQ 1 */
 	if (kbc_output_buffer_full()) {
-		printk_err("Timeout during final keyboard enable\n");
+		printk(BIOS_ERR, "Timeout during final keyboard enable\n");
 		return;
 	}
 }
Index: src/pc80/mc146818rtc.c
===================================================================
--- src/pc80/mc146818rtc.c	(revision 5263)
+++ src/pc80/mc146818rtc.c	(working copy)
@@ -140,7 +140,7 @@
 	int cmos_invalid, checksum_invalid;
 #endif
 
-	printk_debug("RTC Init\n");
+	printk(BIOS_DEBUG, "RTC Init\n");
 
 #if CONFIG_HAVE_OPTION_TABLE
 	/* See if there has been a CMOS power problem. */
@@ -152,7 +152,7 @@
 			PC_CKS_RANGE_END,PC_CKS_LOC);
 
 	if (invalid || cmos_invalid || checksum_invalid) {
-		printk_warning("RTC:%s%s%s zeroing cmos\n",
+		printk(BIOS_WARNING, "RTC:%s%s%s zeroing cmos\n",
 			invalid?" Clear requested":"", 
 			cmos_invalid?" Power Problem":"",
 			checksum_invalid?" Checksum invalid":"");
@@ -188,7 +188,7 @@
 	checksum_invalid = !rtc_checksum_valid(CONFIG_LB_CKS_RANGE_START,
 			CONFIG_LB_CKS_RANGE_END,CONFIG_LB_CKS_LOC);
 	if(checksum_invalid)
-		printk_debug("Invalid CMOS LB checksum\n");
+		printk(BIOS_DEBUG, "Invalid CMOS LB checksum\n");
 
 	/* Make certain we have a valid checksum */
 	rtc_set_checksum(PC_CKS_RANGE_START,
@@ -257,7 +257,7 @@
 		}
 	}
 	if(!found) {
-		printk_debug("WARNING: No cmos option '%s'\n", name);
+		printk(BIOS_DEBUG, "WARNING: No cmos option '%s'\n", name);
 		return(-2);
 	}
 	
Index: src/arch/i386/smp/ioapic.c
===================================================================
--- src/arch/i386/smp/ioapic.c	(revision 5263)
+++ src/arch/i386/smp/ioapic.c	(working copy)
@@ -40,13 +40,13 @@
 	u32 low, high;
 	u32 i, ioapic_interrupts;
 
-	printk_debug("IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); 
+	printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); 
 
 	/* Read the available number of interrupts */
 	ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
 	if (!ioapic_interrupts || ioapic_interrupts == 0xff)
 		ioapic_interrupts = 24;
-	printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts); 
+	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); 
 
 	low = DISABLED;
 	high = NONE;
@@ -55,11 +55,11 @@
 		io_apic_write(ioapic_base, i * 2 + 0x10, low);
 		io_apic_write(ioapic_base, i * 2 + 0x11, high);
 
-		printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+		printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
 	}
 
 	if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
-		printk_warning("IO APIC not responding.\n");
+		printk(BIOS_WARNING, "IO APIC not responding.\n");
 		return;
 	}
 }
@@ -70,12 +70,12 @@
 	u32 low, high;
 	u32 i, ioapic_interrupts;
 
-	printk_debug("IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); 
-	printk_debug("IOAPIC: Bootstrap Processor Local APIC = %02x\n",
+	printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); 
+	printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n",
 			bsp_lapicid);
 
 	if (ioapic_id) {
-		printk_debug("IOAPIC: ID = 0x%02x\n", ioapic_id); 
+		printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); 
 		/* Set IOAPIC ID if it has been specified */
 		io_apic_write(ioapic_base, 0x00, 
 			(io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | 
@@ -86,7 +86,7 @@
 	ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
 	if (!ioapic_interrupts || ioapic_interrupts == 0xff)
 		ioapic_interrupts = 24;
-	printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts); 
+	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); 
 
 
 // XXX this decision should probably be made elsewhere, and
@@ -101,11 +101,11 @@
 	/* For the Pentium 4 and above APICs deliver their interrupts
 	 * on the front side bus, enable that.
 	 */
-	printk_debug("IOAPIC: Enabling interrupts on FSB\n"); 
+	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); 
 	io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0));
 #endif
 #ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
-	printk_debug("IOAPIC: Enabling interrupts on APIC serial bus\n"); 
+	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); 
 	io_apic_write(ioapic_base, 0x03, 0);
 #endif
 
@@ -117,11 +117,11 @@
 	io_apic_write(ioapic_base, 0x11, high);
 
 	if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
-		printk_warning("IO APIC not responding.\n");
+		printk(BIOS_WARNING, "IO APIC not responding.\n");
 		return;
 	}
 
-	printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
+	printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
 
 	low = DISABLED;
 	high = NONE;
@@ -130,6 +130,6 @@
 		io_apic_write(ioapic_base, i * 2 + 0x10, low);
 		io_apic_write(ioapic_base, i * 2 + 0x11, high);
 
-		printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+		printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
 	}
 }
Index: src/arch/i386/smp/mpspec.c
===================================================================
--- src/arch/i386/smp/mpspec.c	(revision 5263)
+++ src/arch/i386/smp/mpspec.c	(working copy)
@@ -177,7 +177,7 @@
 	mpc->mpc_dstirq = dstirq;
 	smp_add_mpc_entry(mc, sizeof(*mpc));
 #ifdef DEBUG_MPTABLE
-	printk_debug("add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n",
+	printk(BIOS_DEBUG, "add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n",
 				srcbus, srcbusirq, dstapic, dstirq);
 	hexdump(__func__, mpc, sizeof(*mpc));
 #endif
@@ -215,7 +215,7 @@
 
 			if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) {
 				/* pci device */
-				printk_debug("route irq: %s\n", dev_path(child));
+				printk(BIOS_DEBUG, "route irq: %s\n", dev_path(child));
 				for (i = 0; i < 4; i++)
 					smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]);
 				goto next;
@@ -225,7 +225,7 @@
 			case PCI_CLASS_BRIDGE_PCI:
 			case PCI_CLASS_BRIDGE_PCMCIA:
 			case PCI_CLASS_BRIDGE_CARDBUS:
-				printk_debug("route irq bridge: %s\n", dev_path(child));
+				printk(BIOS_DEBUG, "route irq bridge: %s\n", dev_path(child));
 				smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x);
 			}
 
Index: src/arch/i386/boot/gdt.c
===================================================================
--- src/arch/i386/boot/gdt.c	(revision 5263)
+++ src/arch/i386/boot/gdt.c	(working copy)
@@ -47,7 +47,7 @@
 			printk(BIOS_ERR, "Error: Could not relocate GDT.\n");
 			return;
 		}
-		printk_debug("Moving GDT to %p...", newgdt);
+		printk(BIOS_DEBUG, "Moving GDT to %p...", newgdt);
 		memcpy((void*)newgdt, &gdt, num_gdt_bytes);
 	}
 
@@ -55,6 +55,6 @@
 	gdtarg.limit = num_gdt_bytes - 1;
 
 	__asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg));
-	printk_debug("ok\n");
+	printk(BIOS_DEBUG, "ok\n");
 }
 
Index: src/arch/i386/boot/multiboot.c
===================================================================
--- src/arch/i386/boot/multiboot.c	(revision 5263)
+++ src/arch/i386/boot/multiboot.c	(working copy)
@@ -112,7 +112,7 @@
 	mbi->mmap_length = ((u32) mb_mem) - mbi->mmap_addr;
 	mbi->flags |= MB_INFO_MEM_MAP;
 
-	printk_info("Multiboot Information structure has been written.\n");
+	printk(BIOS_INFO, "Multiboot Information structure has been written.\n");
 
 	return (unsigned long)mb_mem;
 }
Index: src/arch/i386/boot/pirq_routing.c
===================================================================
--- src/arch/i386/boot/pirq_routing.c	(revision 5263)
+++ src/arch/i386/boot/pirq_routing.c	(working copy)
@@ -14,10 +14,10 @@
 	uint8_t sum=0;
 	int i;
 
-	printk_info("Checking Interrupt Routing Table consistency...\n");
+	printk(BIOS_INFO, "Checking Interrupt Routing Table consistency...\n");
 
 	if (sizeof(struct irq_routing_table) != rt->size) {
-		printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
+		printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
 			       sizeof(struct irq_routing_table),
 			       rt->size
 			);
@@ -27,21 +27,21 @@
 	for (i = 0; i < rt->size; i++)
 		sum += addr[i];
 
-	printk_debug("%s(): Interrupt Routing Table located at %p.\n",
+	printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n",
 		     __func__, addr);
 
 	
 	sum = rt->checksum - sum;
 
 	if (sum != rt->checksum) {
-		printk_warning("Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n",
+		printk(BIOS_WARNING, "Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n",
 			       rt->checksum, sum);
 		rt->checksum = sum;
 	}
 
 	if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION ||
 	    rt->size % 16 ) {
-		printk_warning("Interrupt Routing Table not valid.\n");
+		printk(BIOS_WARNING, "Interrupt Routing Table not valid.\n");
 		return;
 	}
 
@@ -54,11 +54,11 @@
 	 * function would have bailed out earlier.
 	 */
 	if (sum) {
-		printk_warning("Checksum error in Interrupt Routing Table "
+		printk(BIOS_WARNING, "Checksum error in Interrupt Routing Table "
 				"could not be fixed.\n");
 	}
 
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 }
 
 static int verify_copy_pirq_routing_table(unsigned long addr)
@@ -68,14 +68,14 @@
 
 	rt_curr = (uint8_t*)addr;
 	rt_orig = (uint8_t*)&intel_irq_routing_table;
-	printk_info("Verifing copy of Interrupt Routing Table at 0x%08x... ", addr);
+	printk(BIOS_INFO, "Verifing copy of Interrupt Routing Table at 0x%08x... ", addr);
 	for (i = 0; i < intel_irq_routing_table.size; i++) {
 		if (*(rt_curr + i) != *(rt_orig + i)) {
-			printk_info("failed\n");
+			printk(BIOS_INFO, "failed\n");
 			return -1;
 		}
 	}
-	printk_info("done\n");
+	printk(BIOS_INFO, "done\n");
 	
 	check_pirq_routing_table((struct irq_routing_table *)addr);
 	
@@ -90,9 +90,9 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Copying Interrupt Routing Table to 0x%08lx... ", addr);
+	printk(BIOS_INFO, "Copying Interrupt Routing Table to 0x%08lx... ", addr);
 	memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size);
-	printk_info("done.\n");
+	printk(BIOS_INFO, "done.\n");
 #if CONFIG_DEBUG
 	verify_copy_pirq_routing_table(addr);
 #endif
@@ -114,7 +114,7 @@
 	/* Set PCI IRQs. */
 	for (i = 0; i < num_entries; i++) {
 
-		printk_debug("PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i,
+		printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i,
 			pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot);
 
 		for (j = 0; j < 4; j++) {
@@ -123,12 +123,12 @@
 			int bitmap = pirq_tbl->slots[i].irq[j].bitmap;
 			int irq = 0;
 
-			printk_debug("INT: %c link: %x bitmap: %x  ",
+			printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x  ",
 				'A' + j, link, bitmap);
 
 			if (!bitmap|| !link || link > 4) {
 
-				printk_debug("not routed\n");
+				printk(BIOS_DEBUG, "not routed\n");
 				irq_slot[j] = irq;
 				continue;
 			}
@@ -154,7 +154,7 @@
 			else
 				irq = pirq[link - 1];
 
-			printk_debug("IRQ: %d\n", irq);
+			printk(BIOS_DEBUG, "IRQ: %d\n", irq);
 			irq_slot[j] = irq;
 		}
 
@@ -163,10 +163,10 @@
 			pirq_tbl->slots[i].devfn >> 3, irq_slot);
 	}
 
-	printk_debug("PIRQ1: %d\n", pirq[0]);
-	printk_debug("PIRQ2: %d\n", pirq[1]);
-	printk_debug("PIRQ3: %d\n", pirq[2]);
-	printk_debug("PIRQ4: %d\n", pirq[3]);
+	printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]);
+	printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]);
+	printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]);
+	printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]);
 
 	pirq_assign_irqs(pirq);
 }
Index: src/arch/i386/boot/boot.c
===================================================================
--- src/arch/i386/boot/boot.c	(revision 5263)
+++ src/arch/i386/boot/boot.c	(working copy)
@@ -84,13 +84,13 @@
 	adjusted_boot_notes = (unsigned long)&elf_boot_notes;
 	adjusted_boot_notes += adjust; 
 
-	printk_spew("entry    = 0x%08lx\n", (unsigned long)entry);
-	printk_spew("lb_start = 0x%08lx\n", lb_start);
-	printk_spew("lb_size  = 0x%08lx\n", lb_size);
-	printk_spew("adjust   = 0x%08lx\n", adjust);
-	printk_spew("buffer   = 0x%08lx\n", buffer);
-	printk_spew("     elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes);
-	printk_spew("adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes);
+	printk(BIOS_SPEW, "entry    = 0x%08lx\n", (unsigned long)entry);
+	printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start);
+	printk(BIOS_SPEW, "lb_size  = 0x%08lx\n", lb_size);
+	printk(BIOS_SPEW, "adjust   = 0x%08lx\n", adjust);
+	printk(BIOS_SPEW, "buffer   = 0x%08lx\n", buffer);
+	printk(BIOS_SPEW, "     elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes);
+	printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes);
 	
 	/* Jump to kernel */
 	__asm__ __volatile__(
Index: src/arch/i386/boot/coreboot_table.c
===================================================================
--- src/arch/i386/boot/coreboot_table.c	(revision 5263)
+++ src/arch/i386/boot/coreboot_table.c	(working copy)
@@ -307,7 +307,7 @@
 	head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
 	head->header_checksum = 0;
 	head->header_checksum = compute_ip_checksum(head, sizeof(*head));
-	printk_debug("Wrote coreboot table at: %p - %p  checksum %x\n",
+	printk(BIOS_DEBUG, "Wrote coreboot table at: %p - %p  checksum %x\n",
 		head, rec, head->table_checksum);
 	return (unsigned long)rec;
 }
@@ -428,7 +428,7 @@
 	int i;
 	entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
 	
-	printk_debug("coreboot memory table:\n");
+	printk(BIOS_DEBUG, "coreboot memory table:\n");
 	for(i = 0; i < entries; i++) {
 		uint64_t entry_start = unpack_lb64(mem->map[i].start);
 		uint64_t entry_size = unpack_lb64(mem->map[i].size);
@@ -445,7 +445,7 @@
 		default: entry_type="UNKNOWN!"; break;
 		}
 
-		printk_debug("%2d. %016llx-%016llx: %s\n", 
+		printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", 
 			i, entry_start, entry_start+entry_size-1, entry_type);
 		
 	}
@@ -497,19 +497,19 @@
 	struct lb_memory *mem;
 
 #if CONFIG_WRITE_HIGH_TABLES == 1
-	printk_debug("Writing high table forward entry at 0x%08lx\n",
+	printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
 	lb_forward(head, (struct lb_header*)rom_table_end);
 
 	low_table_end = (unsigned long) lb_table_fini(head, 0);
-	printk_debug("New low_table_end: 0x%08lx\n", low_table_end);
-	printk_debug("Now going to write high coreboot table at 0x%08lx\n",
+	printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end);
+	printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n",
 			rom_table_end);
 	
 	head = lb_table_init(rom_table_end);
 	rom_table_end = (unsigned long)head;
-	printk_debug("rom_table_end = 0x%08lx\n", rom_table_end);
+	printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
 #else
 	if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */
 		/* We need to put lbtable on  to [0xf0000,0x100000) */
@@ -521,16 +521,16 @@
 	}
 #endif
  
-	printk_debug("Adjust low_table_end from 0x%08lx to ", low_table_end);
+	printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end);
 	low_table_end += 0xfff; // 4K aligned
 	low_table_end &= ~0xfff;
-	printk_debug("0x%08lx \n", low_table_end);
+	printk(BIOS_DEBUG, "0x%08lx \n", low_table_end);
 
 	/* The Linux kernel assumes this region is reserved */
-	printk_debug("Adjust rom_table_end from 0x%08lx to ", rom_table_end);
+	printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end);
 	rom_table_end += 0xffff; // 64K align
 	rom_table_end &= ~0xffff;
-	printk_debug("0x%08lx \n", rom_table_end);
+	printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
 
 #if (CONFIG_HAVE_OPTION_TABLE == 1) 
 	{
@@ -553,7 +553,7 @@
 		rom_table_start, rom_table_end-rom_table_start);
 
 #if CONFIG_WRITE_HIGH_TABLES == 1
-	printk_debug("Adding high table area\n");
+	printk(BIOS_DEBUG, "Adding high table area\n");
 	// should this be LB_MEM_ACPI?
 	lb_add_memory_range(mem, LB_MEM_TABLE,
 		high_tables_base, high_tables_size);
Index: src/arch/i386/boot/tables.c
===================================================================
--- src/arch/i386/boot/tables.c	(revision 5263)
+++ src/arch/i386/boot/tables.c	(working copy)
@@ -53,12 +53,12 @@
 	unsigned long high_table_pointer;
 
 	if (!high_tables_base) {
-		printk_err("ERROR: High Tables Base is not set.\n");
+		printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n");
 		// Are there any boards without?
 		// Stepan thinks we should die() here!
 	}
 
-	printk_debug("High Tables Base is %llx.\n", high_tables_base);
+	printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base);
 
 	rom_table_start = 0xf0000; 
 	rom_table_end =   0xf0000;
@@ -169,7 +169,7 @@
 				(acpi_rsdt_t *)(high_rsdp->rsdt_address),
 				(acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address));
 		} else {
-			printk_err("ERROR: Didn't find RSDP in high table.\n");
+			printk(BIOS_ERR, "ERROR: Didn't find RSDP in high table.\n");
 		}
 		rom_table_end = ALIGN(rom_table_end + sizeof(acpi_rsdp_t), 16);
 	} else {
@@ -202,7 +202,7 @@
 
 		if (new_high_table_pointer > (high_table_pointer +
 					MAX_COREBOOT_TABLE_SIZE))
-			printk_err("%s: coreboot table didn't fit (%lx)\n",
+			printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n",
 				   __func__, new_high_table_pointer -
 				   high_table_pointer);
 
Index: src/arch/i386/boot/acpi.c
===================================================================
--- src/arch/i386/boot/acpi.c	(revision 5263)
+++ src/arch/i386/boot/acpi.c	(working copy)
@@ -69,7 +69,7 @@
 	}
 
 	if (i >= entries_num) {
-		printk_err("ACPI: Error: Could not add ACPI table, too many tables.\n");
+		printk(BIOS_ERR, "ACPI: Error: Could not add ACPI table, too many tables.\n");
 		return;
 	}
 
@@ -101,7 +101,7 @@
 				xsdt->header.length);
 	}
 
-	printk_debug("ACPI: added table %d/%d Length now %d\n",
+	printk(BIOS_DEBUG, "ACPI: added table %d/%d Length now %d\n",
 			i+1, entries_num, rsdt->header.length);
 }
 
@@ -497,17 +497,17 @@
 	if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0)
 		return NULL;
 
-	printk_debug("Looking on %p for valid checksum\n", rsdp);
+	printk(BIOS_DEBUG, "Looking on %p for valid checksum\n", rsdp);
 
 	if (acpi_checksum((void *)rsdp, 20) != 0)
 		return NULL;
-	printk_debug("Checksum 1 passed\n");
+	printk(BIOS_DEBUG, "Checksum 1 passed\n");
 
 	if ((rsdp->revision > 1) && (acpi_checksum((void *)rsdp,
 						rsdp->length) != 0))
 		return NULL;
 
-	printk_debug("Checksum 2 passed all OK\n");
+	printk(BIOS_DEBUG, "Checksum 2 passed all OK\n");
 
 	return rsdp;
 }
@@ -534,7 +534,7 @@
 	if (!acpi_is_wakeup())
 		return NULL;
 
-	printk_debug("Trying to find the wakeup vector ...\n");
+	printk(BIOS_DEBUG, "Trying to find the wakeup vector ...\n");
 
 	/* find RSDP */
 	for (p = (char *) 0xe0000; p <  (char *) 0xfffff; p+=16) {
@@ -545,11 +545,11 @@
 	if (rsdp == NULL)
 		return NULL;
 
-	printk_debug("RSDP found at %p\n", rsdp);
+	printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp);
 	rsdt = (acpi_rsdt_t *) rsdp->rsdt_address;
 	
 	end = (char *) rsdt + rsdt->header.length;
-	printk_debug("RSDT found at %p ends at %p\n", rsdt, end);
+	printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end);
 
 	for (i = 0; ((char *) &rsdt->entry[i]) < end; i++) {
 		fadt = (acpi_fadt_t *) rsdt->entry[i];
@@ -561,17 +561,17 @@
 	if (fadt == NULL)
 		return NULL;
 
-	printk_debug("FADT found at %p\n", fadt);
+	printk(BIOS_DEBUG, "FADT found at %p\n", fadt);
 	facs = (acpi_facs_t *)fadt->firmware_ctrl;
 
 	if (facs == NULL) {
-		printk_debug("No FACS found, wake up from S3 not possible.\n");
+		printk(BIOS_DEBUG, "No FACS found, wake up from S3 not possible.\n");
 		return NULL;
 	}
 
-	printk_debug("FACS found at %p\n", facs);
+	printk(BIOS_DEBUG, "FACS found at %p\n", facs);
 	wake_vec = (void *) facs->firmware_waking_vector;
-	printk_debug("OS waking vector is %p\n", wake_vec);
+	printk(BIOS_DEBUG, "OS waking vector is %p\n", wake_vec);
 	return wake_vec;
 }
 
Index: src/arch/i386/lib/exception.c
===================================================================
--- src/arch/i386/lib/exception.c	(revision 5263)
+++ src/arch/i386/lib/exception.c	(working copy)
@@ -475,7 +475,7 @@
 		put_packet(out_buffer);
 	}
 #else /* !CONFIG_GDB_STUB */
-	printk_emerg(
+	printk(BIOS_EMERG, 
 		"Unexpected Exception: %d @ %02x:%08x - Halting\n"
 		"Code: %d eflags: %08x\n"
 		"eax: %08x ebx: %08x ecx: %08x edx: %08x\n"
Index: src/arch/i386/lib/pci_ops_auto.c
===================================================================
--- src/arch/i386/lib/pci_ops_auto.c	(revision 5263)
+++ src/arch/i386/lib/pci_ops_auto.c	(working copy)
@@ -37,7 +37,7 @@
 			return 1;
 		}
 	}
-	printk_err("PCI: Sanity check failed\n");
+	printk(BIOS_ERR, "PCI: Sanity check failed\n");
 	return 0;
 }
 
@@ -58,7 +58,7 @@
 			pci_sanity_check(&pci_cf8_conf1)) 
 		{
 			outl(tmp, 0xCF8);
-			printk_debug("PCI: Using configuration type 1\n");
+			printk(BIOS_DEBUG, "PCI: Using configuration type 1\n");
 			return &pci_cf8_conf1;
 		}
 		outl(tmp, 0xCF8);
@@ -74,7 +74,7 @@
 		if ((inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) &&
 			pci_sanity_check(&pci_cf8_conf2))
 		{
-			printk_debug("PCI: Using configuration type 2\n");
+			printk(BIOS_DEBUG, "PCI: Using configuration type 2\n");
 			return &pci_cf8_conf2;
 		}
 	}
@@ -94,7 +94,7 @@
  */
 void pci_set_method(device_t dev)
 {
-	printk_info("Finding PCI configuration type.\n");
+	printk(BIOS_INFO, "Finding PCI configuration type.\n");
 	dev->ops->ops_pci_bus = pci_remember_direct();
 	post_code(0x5f);
 }
Index: src/arch/i386/lib/cpu.c
===================================================================
--- src/arch/i386/lib/cpu.c	(revision 5263)
+++ src/arch/i386/lib/cpu.c	(working copy)
@@ -224,7 +224,7 @@
 	
 	info = cpu_info();
 
-	printk_info("Initializing CPU #%ld\n", info->index);
+	printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index);
 
 	cpu = info->cpu;
 	if (!cpu) {
@@ -233,12 +233,12 @@
 
 	/* Find what type of cpu we are dealing with */
 	identify_cpu(cpu);
-	printk_debug("CPU: vendor %s device %x\n",
+	printk(BIOS_DEBUG, "CPU: vendor %s device %x\n",
 		cpu_vendor_name(cpu->vendor), cpu->device);
 
 	get_fms(&c, cpu->device);
 
-	printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
+	printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
 	
 	/* Lookup the cpu's operations */
 	set_cpu_ops(cpu);
@@ -249,7 +249,7 @@
 		set_cpu_ops(cpu);
 		cpu->device += c.x86_mask;
 		if(!cpu->ops) die("Unknown cpu");
-		printk_debug("Using generic cpu ops (good)\n");
+		printk(BIOS_DEBUG, "Using generic cpu ops (good)\n");
 	}
 	
 
@@ -260,7 +260,7 @@
 		cpu->ops->init(cpu);
 	}
 
-	printk_info("CPU #%ld initialized\n", info->index);
+	printk(BIOS_INFO, "CPU #%ld initialized\n", info->index);
 
 	return;
 }
Index: src/arch/i386/lib/console_printk.c
===================================================================
--- src/arch/i386/lib/console_printk.c	(revision 5263)
+++ src/arch/i386/lib/console_printk.c	(working copy)
@@ -1,21 +1,21 @@
 
-#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
-#define printk_alert(fmt, arg...)   do_printk(BIOS_ALERT   ,fmt, ##arg)
+#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
+#define printk(BIOS_ALERT, fmt, arg...)   do_printk(BIOS_ALERT   ,fmt, ##arg)
 #define printk_crit(fmt, arg...)    do_printk(BIOS_CRIT    ,fmt, ##arg)
-#define printk_err(fmt, arg...)     do_printk(BIOS_ERR     ,fmt, ##arg)
-#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
+#define printk(BIOS_ERR, fmt, arg...)     do_printk(BIOS_ERR     ,fmt, ##arg)
+#define printk(BIOS_WARNING, fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
 #define printk_notice(fmt, arg...)  do_printk(BIOS_NOTICE  ,fmt, ##arg)
-#define printk_info(fmt, arg...)    do_printk(BIOS_INFO    ,fmt, ##arg)
-#define printk_debug(fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
-#define printk_spew(fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
+#define printk(BIOS_INFO, fmt, arg...)    do_printk(BIOS_INFO    ,fmt, ##arg)
+#define printk(BIOS_DEBUG, fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
+#define printk(BIOS_SPEW, fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
 
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_EMERG
 #undef  printk_emerg
-#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
+#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_ALERT
 #undef  printk_alert
-#define printk_alert(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
+#define printk(BIOS_ALERT, fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_CRIT
 #undef  printk_crit
@@ -23,11 +23,11 @@
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_ERR
 #undef  printk_err
-#define printk_err(fmt, arg...)     do_printk(BIOS_EMERG   , "", ##arg)
+#define printk(BIOS_ERR, fmt, arg...)     do_printk(BIOS_EMERG   , "", ##arg)
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_WARNING
 #undef  printk_warning
-#define printk_warning(fmt, arg...) do_printk(BIOS_EMERG   , "", ##arg)
+#define printk(BIOS_WARNING, fmt, arg...) do_printk(BIOS_EMERG   , "", ##arg)
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_NOTICE
 #undef  printk_notice
@@ -35,22 +35,22 @@
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_INFO
 #undef  printk_info
-#define printk_info(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
+#define printk(BIOS_INFO, fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_DEBUG
 #undef  printk_debug
-#define printk_debug(fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
+#define printk(BIOS_DEBUG, fmt, arg...)   do_printk(BIOS_EMERG   , "", ##arg)
 #endif
 #if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_SPEW
 #undef  printk_spew
-#define printk_spew(fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
+#define printk(BIOS_SPEW, fmt, arg...)    do_printk(BIOS_EMERG   , "", ##arg)
 #endif
 
 #define print_emerg(STR)   printk_emerg  ("%s", (STR))
 #define print_alert(STR)   printk_alert  ("%s", (STR))
 #define print_crit(STR)    printk_crit   ("%s", (STR))
 #define print_err(STR)     printk_err    ("%s", (STR))
-#define print_warning(STR) printk_warning("%s", (STR))
+#define print_warning(STR) printk(BIOS_WARNING, "%s", (STR))
 #define print_notice(STR)  printk_notice ("%s", (STR))
 #define print_info(STR)    printk_info   ("%s", (STR))
 #define print_debug(STR)   printk_debug  ("%s", (STR))
@@ -60,7 +60,7 @@
 #define print_alert_char(CH)   printk_alert  ("%c", (CH))
 #define print_crit_char(CH)    printk_crit   ("%c", (CH))
 #define print_err_char(CH)     printk_err    ("%c", (CH))
-#define print_warning_char(CH) printk_warning("%c", (CH))
+#define print_warning_char(CH) printk(BIOS_WARNING, "%c", (CH))
 #define print_notice_char(CH)  printk_notice ("%c", (CH))
 #define print_info_char(CH)    printk_info   ("%c", (CH))
 #define print_debug_char(CH)   printk_debug  ("%c", (CH))
@@ -70,7 +70,7 @@
 #define print_alert_hex8(HEX)   printk_alert  ("%02x",  (HEX))
 #define print_crit_hex8(HEX)    printk_crit   ("%02x",  (HEX))
 #define print_err_hex8(HEX)     printk_err    ("%02x",  (HEX))
-#define print_warning_hex8(HEX) printk_warning("%02x",  (HEX))
+#define print_warning_hex8(HEX) printk(BIOS_WARNING, "%02x",  (HEX))
 #define print_notice_hex8(HEX)  printk_notice ("%02x",  (HEX))
 #define print_info_hex8(HEX)    printk_info   ("%02x",  (HEX))
 #define print_debug_hex8(HEX)   printk_debug  ("%02x",  (HEX))
@@ -80,7 +80,7 @@
 #define print_alert_hex16(HEX)   printk_alert  ("%04x", (HEX))
 #define print_crit_hex16(HEX)    printk_crit   ("%04x", (HEX))
 #define print_err_hex16(HEX)     printk_err    ("%04x", (HEX))
-#define print_warning_hex16(HEX) printk_warning("%04x", (HEX))
+#define print_warning_hex16(HEX) printk(BIOS_WARNING, "%04x", (HEX))
 #define print_notice_hex16(HEX)  printk_notice ("%04x", (HEX))
 #define print_info_hex16(HEX)    printk_info   ("%04x", (HEX))
 #define print_debug_hex16(HEX)   printk_debug  ("%04x", (HEX))
@@ -90,7 +90,7 @@
 #define print_alert_hex32(HEX)   printk_alert  ("%08x", (HEX))
 #define print_crit_hex32(HEX)    printk_crit   ("%08x", (HEX))
 #define print_err_hex32(HEX)     printk_err    ("%08x", (HEX))
-#define print_warning_hex32(HEX) printk_warning("%08x", (HEX))
+#define print_warning_hex32(HEX) printk(BIOS_WARNING, "%08x", (HEX))
 #define print_notice_hex32(HEX)  printk_notice ("%08x", (HEX))
 #define print_info_hex32(HEX)    printk_info   ("%08x", (HEX))
 #define print_debug_hex32(HEX)   printk_debug  ("%08x", (HEX))
Index: src/drivers/trident/blade3d/blade3d.c
===================================================================
--- src/drivers/trident/blade3d/blade3d.c	(revision 5263)
+++ src/drivers/trident/blade3d/blade3d.c	(working copy)
@@ -777,7 +777,7 @@
 
 	//if chip revB
 	if (CHIPREV == 0x02) {
-		printk_debug("blade3d: chip revision B\n");
+		printk(BIOS_DEBUG, "blade3d: chip revision B\n");
 		outp(Port_CRX, 0xc0);
 		outp(Port_CRX + 1, 0x00);
 	}
@@ -805,7 +805,7 @@
 	lpMode3_temp = &Mode3_temp[0];
 	lpInit_reg = &Init_reg[0];
 
-	printk_debug("blade3d: config_OEM_regs()\n");
+	printk(BIOS_DEBUG, "blade3d: config_OEM_regs()\n");
 	
 	outp(Port_GRX, 0x24);
 	outp(Port_GRX + 1, 0xe0);
@@ -943,13 +943,13 @@
 		}
 
 	} else {			//SGRAM
-		printk_debug("blade3d: No SGRAM found.\n");
+		printk(BIOS_DEBUG, "blade3d: No SGRAM found.\n");
 	}
 }
 
 static void config_video_memory(void)
 {
-	printk_debug("blade3d: Error: no video memory init\n");
+	printk(BIOS_DEBUG, "blade3d: Error: no video memory init\n");
 }
 
 static void set_video_mode(void)
@@ -959,7 +959,7 @@
 	lpDef_Reg_struct lpMode3_reg;
 	lpMode3_reg = &Mode3_reg[0];
 
-	printk_debug("blade3d: setting video mode\n");
+	printk(BIOS_DEBUG, "blade3d: setting video mode\n");
 	outp(0x3c2, 0x67);
 	for (i = 0; i < Length_Mode3_reg; i++) {
 		if (lpMode3_reg[i].rPort == Port_BRX) {
@@ -982,7 +982,7 @@
 static void set_font(void)
 {
 
-	printk_debug("blade3d: setting font (not implemented)\n");
+	printk(BIOS_DEBUG, "blade3d: setting font (not implemented)\n");
 }
 
 static void clear_MEM(void)
@@ -1008,7 +1008,7 @@
 
 static void trident_blade3d_init(struct device *dev)
 {
-	printk_info("blade3d: initializing video card\n");
+	printk(BIOS_INFO, "blade3d: initializing video card\n");
 	init9880();
 }
 
Index: src/drivers/si/3114/si_sata.c
===================================================================
--- src/drivers/si/3114/si_sata.c	(revision 5263)
+++ src/drivers/si/3114/si_sata.c	(working copy)
@@ -45,7 +45,7 @@
         	dword &= ~(1<<0);
         	pci_write_config32(dev, 0x40, dword);
 
-		printk_debug("Class code restored.\n");
+		printk(BIOS_DEBUG, "Class code restored.\n");
 
 	}
 
Index: src/drivers/generic/debug/debug_dev.c
===================================================================
--- src/drivers/generic/debug/debug_dev.c	(revision 5263)
+++ src/drivers/generic/debug/debug_dev.c	(working copy)
@@ -17,10 +17,10 @@
       for(i=0;i<256;i++) {
 	      byte = pci_read_config8(dev, i);
    
-	      if((i & 0xf)==0) printk_debug("\n%02x:",i);
-	      printk_debug(" %02x",byte);
+	      if((i & 0xf)==0) printk(BIOS_DEBUG, "\n%02x:",i);
+	      printk(BIOS_DEBUG, " %02x",byte);
       }
-      printk_debug("\n");
+      printk(BIOS_DEBUG, "\n");
 }
 
 static void print_mem(void)
@@ -28,10 +28,10 @@
         unsigned int i;
 	unsigned int start = 0xfffff000;
 	for(i=start;i<0xffffffff;i++) {
-             if((i & 0xf)==0) printk_debug("\n %08x:",i);
-             printk_debug(" %02x",(unsigned char)*((unsigned char *)i));
+             if((i & 0xf)==0) printk(BIOS_DEBUG, "\n %08x:",i);
+             printk(BIOS_DEBUG, " %02x",(unsigned char)*((unsigned char *)i));
              }
-	printk_debug(" %02x\n",(unsigned char)*((unsigned char *)i));
+	printk(BIOS_DEBUG, " %02x\n",(unsigned char)*((unsigned char *)i));
 
  }
 static void print_pci_regs_all(void)
@@ -51,7 +51,7 @@
 				if(!dev->enabled) {
 					continue;
 				}
-			        printk_debug("\n%02x:%02x:%02x aka %s", 
+			        printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", 
 					bus, device, function, dev_path(dev));
 				print_pci_regs(dev);
 			}
@@ -65,19 +65,19 @@
 	unsigned index;
 	unsigned eax, ebx, ecx, edx;
 	index = 0x80000007;
-	printk_debug("calling cpuid 0x%08x\n", index);
+	printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
 	asm volatile(
 		"cpuid"
 		: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
 		: "a" (index)
 		);
-	printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+	printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n",
 		index, eax, ebx, ecx, edx);
 	if (edx & (3 << 1)) {
 		index = 0xC0010042;
-		printk_debug("Reading msr: 0x%08x\n", index);
+		printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index);
 		msr = rdmsr(index);
-		printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+		printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x\n",
 			index, msr.hi, msr.lo);
 	}
 
@@ -85,23 +85,23 @@
 static void print_smbus_regs(struct device *dev)
 {               
 	int j;
-	printk_debug("smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link);
-	printk_debug("%s", dev_path(dev));
+	printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link);
+	printk(BIOS_DEBUG, "%s", dev_path(dev));
 	for(j = 0; j < 256; j++) {
 		int status;
 		unsigned char byte;
 		status = smbus_read_byte(dev, j);
 		if (status < 0) {
-		//	printk_debug("bad device status= %08x\r\n", status);
+		//	printk(BIOS_DEBUG, "bad device status= %08x\r\n", status);
 			break;
 		}
                 if ((j & 0xf) == 0) {
-                        printk_debug("\r\n%02x: ", j);
+                        printk(BIOS_DEBUG, "\r\n%02x: ", j);
                 }  
 		byte = status & 0xff;
-		printk_debug("%02x ", byte);
+		printk(BIOS_DEBUG, "%02x ", byte);
 	}
-	printk_debug("\r\n");
+	printk(BIOS_DEBUG, "\r\n");
 }
 
 static void print_smbus_regs_all(struct device *dev)
@@ -133,28 +133,28 @@
         unsigned index;
         unsigned eax, ebx, ecx, edx;
         index = 0x80000008;
-        printk_debug("calling cpuid 0x%08x\n", index);
+        printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
         asm volatile(
                 "cpuid"
                 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
                 : "a" (index)
                 );
-        printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+        printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n",
                 index, eax, ebx, ecx, edx);
 
-        printk_debug("core number %d\n", ecx & 0xff);   
+        printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff);   
 
         index = 0xc001001f;
-        printk_debug("Reading msr: 0x%08x\n", index);
+        printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index);
         msr = rdmsr(index);
-        printk_debug("msr[0x%08x]: 0x%08x%08x bit 54 is %d\n",
+        printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x bit 54 is %d\n",
                 index, msr.hi, msr.lo, (msr.hi>> (54-32)) & 1);
 #if 0
         msr.hi |= (1<<(54-32));
         wrmsr(index, msr);
 
         msr = rdmsr(index);
-        printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+        printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x\n",
                 index, msr.hi, msr.lo);
 #endif
 
@@ -166,7 +166,7 @@
 	unsigned int n, eax, ebx, ecx, edx;
 
         index = 0x80000000;
-        printk_debug("calling cpuid 0x%08x\n", index);
+        printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
         asm volatile(
                 "cpuid"
                 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
@@ -176,25 +176,25 @@
 
         if (n >= 0x80000005) {
 	        index = 0x80000005;
-	        printk_debug("calling cpuid 0x%08x\n", index);
+	        printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
         	asm volatile(
                 	"cpuid"
 	                : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
         	        : "a" (index)
                 	);
-                printk_debug("CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
+                printk(BIOS_DEBUG, "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
                         edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
         }
 
         if (n >= 0x80000006) {
                 index = 0x80000006;
-                printk_debug("calling cpuid 0x%08x\n", index);
+                printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index);
                 asm volatile(
                         "cpuid"
                         : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
                         : "a" (index)
                         );
-        	printk_debug("CPU: L2 Cache: %dK (%d bytes/line)\n",
+        	printk(BIOS_DEBUG, "CPU: L2 Cache: %dK (%d bytes/line)\n",
                 	ecx >> 16, ecx & 0xFF);
         }
 
@@ -220,11 +220,11 @@
 	
 	tsc_t tsc;
 	tsc = rdtsc();
-        printk_debug("tsc: 0x%08x%08x\n",
+        printk(BIOS_DEBUG, "tsc: 0x%08x%08x\n",
                      tsc.hi, tsc.lo);
 	udelay(1);
         tsc = rdtsc();
-        printk_debug("tsc: 0x%08x%08x after udelay(1) \n",
+        printk(BIOS_DEBUG, "tsc: 0x%08x%08x after udelay(1) \n",
                      tsc.hi, tsc.lo);
 
 }
@@ -238,11 +238,11 @@
 	switch(dev->path.pnp.device) {
 	case 0:
 		parent = dev->bus->dev;
-		printk_debug("DEBUG: %s", dev_path(parent));
+		printk(BIOS_DEBUG, "DEBUG: %s", dev_path(parent));
 		if(parent->chip_ops && parent->chip_ops->name) {
-			printk_debug(": %s\n", parent->chip_ops->name);
+			printk(BIOS_DEBUG, ": %s\n", parent->chip_ops->name);
 		} else {
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
 		break;
 		
Index: src/drivers/ati/ragexl/xlinit.c
===================================================================
--- src/drivers/ati/ragexl/xlinit.c	(revision 5263)
+++ src/drivers/ati/ragexl/xlinit.c	(working copy)
@@ -541,7 +541,7 @@
 #endif
 
 #if 0
-	printk_debug("ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
+	printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
 #endif
 
     	chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
@@ -557,11 +557,11 @@
             		info->features = aty_chips[j].features;
             		goto found;
         }
-    	printk_spew("ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
+    	printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
     	return ;
 
 found:
-    	printk_info("ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
+    	printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
 #if 0
     	if (M64_HAS(INTEGRATED)) {
         	/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
@@ -717,7 +717,7 @@
 
     if (atyfb_decode_var(&var, &info->default_par, info)) {
 #if 0	
-        printk_debug("atyfb: can't set default video mode\n");
+        printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");
 #endif
         return ;
     }
@@ -750,7 +750,7 @@
 
 #if PLL_CRTC_DECODE==1
 
-    printk_spew("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
+    printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
                          info->current_par.crtc.bpp,
@@ -762,7 +762,7 @@
                          info->current_par.crtc.bpp,
                          info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
 #else
-    printk_spew("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
+    printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
                          info->default_par.crtc.bpp,
@@ -1184,7 +1184,7 @@
     atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
    
 #if 0 
-    printk_info("atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
+    printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
 #endif
 
     if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
Index: src/drivers/ati/ragexl/mach64_ct.c
===================================================================
--- src/drivers/ati/ragexl/mach64_ct.c	(revision 5263)
+++ src/drivers/ati/ragexl/mach64_ct.c	(working copy)
@@ -2,7 +2,7 @@
 
 /* FIXME: remove the FAIL definition */
 #if 0
-#define FAIL(x) do { printk_debug(x); return -EINVAL; } while (0)
+#define FAIL(x) do { printk(BIOS_DEBUG, x); return -EINVAL; } while (0)
 #else
 #define FAIL(x) 
 #endif
@@ -31,7 +31,7 @@
     u32 memcntl, n, t_pfc, t_rp, t_ras, t_rcd, t_crd, t_rcc, t_lat;
 
 #if DEBUG_PLL==1
-    printk_debug("aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult);
+    printk(BIOS_DEBUG, "aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult);
 #endif
     
     /* (64*xclk/vclk/bpp)<<11 = xclocks_per_row<<11 */
@@ -150,7 +150,7 @@
     pllsclk = (1000000 * 2 * pll->sclk_fb_div) /
 	    (info->ref_clk_per * pll->pll_ref_div);
 
-    printk_debug("aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n",
+    printk(BIOS_DEBUG, "aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n",
 	   pllsclk, pllsclk / pll->mclk_post_div_real);
 #endif
     
@@ -175,7 +175,7 @@
 #if DEBUG_PLL==1
     pllmclk = (1000000 * pll->mclk_fb_mult * pll->mclk_fb_div) /
 	    (info->ref_clk_per * pll->pll_ref_div);
-    printk_debug("aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n",
+    printk(BIOS_DEBUG, "aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n",
 	   pllmclk, pllmclk / pll->xclk_post_div_real);
 #endif
     
@@ -301,7 +301,7 @@
 void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll)
 {
 #if DEBUG_PLL==1
-    printk_debug("aty_set_pll_ct: about to program:\n"
+    printk(BIOS_DEBUG, "aty_set_pll_ct: about to program:\n"
 	   "refdiv=%d, extcntl=0x%02x, mfbdiv=%d\n"
 	   "spllcntl2=0x%02x, sfbdiv=%d, gencntl=0x%02x\n"
 	   "vclkcntl=0x%02x, vpostdiv=0x%02x, vfbdiv=%d\n"
Index: src/drivers/emulation/qemu/init.c
===================================================================
--- src/drivers/emulation/qemu/init.c	(revision 5263)
+++ src/drivers/emulation/qemu/init.c	(working copy)
@@ -56,7 +56,7 @@
 {
     int width=640, height=480, depth=8;
 
-    printk_debug("Initializing VGA!\n");
+    printk(BIOS_DEBUG, "Initializing VGA!\n");
     
     vbe_outw(VBE_DISPI_INDEX_XRES, width);
     vbe_outw(VBE_DISPI_INDEX_YRES, height);
Index: src/drivers/i2c/adm1026/adm1026.c
===================================================================
--- src/drivers/i2c/adm1026/adm1026.c	(revision 5263)
+++ src/drivers/i2c/adm1026/adm1026.c	(working copy)
@@ -44,7 +44,7 @@
 
         result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
         if (!(result & CFG1_MONITOR)) {
-                printk_debug("ADM1026: monitoring would not enable");
+                printk(BIOS_DEBUG, "ADM1026: monitoring would not enable");
         }
 }
 static void adm1026_noop(device_t dummy)
Index: src/drivers/i2c/adm1027/adm1027.c
===================================================================
--- src/drivers/i2c/adm1027/adm1027.c	(revision 5263)
+++ src/drivers/i2c/adm1027/adm1027.c	(working copy)
@@ -26,7 +26,7 @@
 	result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
 
 	if (!(result & CFG1_RDY)) {
-		printk_debug("ADM1027: monitoring not ready\r\n");
+		printk(BIOS_DEBUG, "ADM1027: monitoring not ready\r\n");
 		return;
 	}
 	result = (result | CFG1_STRT);
@@ -34,9 +34,9 @@
 
 	result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
 	if (!(result & CFG1_STRT)) {
-		printk_debug("ADM1027: monitoring would not enable\r\n");
+		printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\r\n");
 	}
-	printk_debug("ADM1027: monitoring enabled\r\n");
+	printk(BIOS_DEBUG, "ADM1027: monitoring enabled\r\n");
 }
 
 static void adm1027_init(device_t dev)
Index: util/mptable/mptable.c
===================================================================
--- util/mptable/mptable.c	(revision 5263)
+++ util/mptable/mptable.c	(working copy)
@@ -340,7 +340,7 @@
 "	/* Compute the checksums */",
 "	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);",
 "	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);",
-"	printk_debug(\"Wrote the mp table end at: %p - %p\\n\",",
+"	printk(BIOS_DEBUG, \"Wrote the mp table end at: %p - %p\\n\",",
 "		mc, smp_next_mpe_entry(mc));",
 "	return smp_next_mpe_entry(mc);",
 "}",
