This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
makes include/console/console.h and console/console.c usable both in
__PRE_RAM__ and coreboot_ram stages.

While debugging this, I removed an indirection from the e7520 ram init code
(same as we did on a couple of other chipsets, removes some register pressure
 from romcc)

Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code 
in cache_as_ram.inc)

Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>


 Kconfig                                          |    4 
 arch/i386/lib/console.c                          |   41 ---
 arch/i386/lib/console_print.c                    |  124 -----------
 console/Makefile.inc                             |    2 
 console/console.c                                |   46 ++++
 include/console/console.h                        |  243 ++++++++++++++++++++---
 mainboard/a-trend/atc-6220/romstage.c            |    2 
 mainboard/a-trend/atc-6240/romstage.c            |    2 
 mainboard/abit/be6-ii_v2_0/romstage.c            |    2 
 mainboard/advantech/pcm-5820/romstage.c          |    2 
 mainboard/amd/db800/romstage.c                   |    2 
 mainboard/amd/dbm690t/romstage.c                 |    2 
 mainboard/amd/mahogany/romstage.c                |    2 
 mainboard/amd/mahogany_fam10/romstage.c          |    2 
 mainboard/amd/norwich/romstage.c                 |    2 
 mainboard/amd/pistachio/romstage.c               |    2 
 mainboard/amd/rumba/romstage.c                   |    2 
 mainboard/amd/serengeti_cheetah/ap_romstage.c    |   17 -
 mainboard/amd/serengeti_cheetah/romstage.c       |    2 
 mainboard/amd/serengeti_cheetah_fam10/romstage.c |    2 
 mainboard/arima/hdama/romstage.c                 |    2 
 mainboard/artecgroup/dbe61/romstage.c            |    2 
 mainboard/asi/mb_5blgp/romstage.c                |    2 
 mainboard/asi/mb_5blmp/romstage.c                |    2 
 mainboard/asus/a8n_e/romstage.c                  |    2 
 mainboard/asus/a8v-e_se/romstage.c               |    2 
 mainboard/asus/m2v-mx_se/romstage.c              |    2 
 mainboard/asus/mew-am/romstage.c                 |    2 
 mainboard/asus/mew-vm/romstage.c                 |    2 
 mainboard/asus/p2b-d/romstage.c                  |    2 
 mainboard/asus/p2b-ds/romstage.c                 |    2 
 mainboard/asus/p2b-f/romstage.c                  |    2 
 mainboard/asus/p2b-ls/romstage.c                 |    2 
 mainboard/asus/p2b/romstage.c                    |    2 
 mainboard/asus/p3b-f/romstage.c                  |    2 
 mainboard/axus/tc320/romstage.c                  |    2 
 mainboard/azza/pt-6ibd/romstage.c                |    2 
 mainboard/bcom/winnet100/romstage.c              |    2 
 mainboard/bcom/winnetp680/romstage.c             |    2 
 mainboard/biostar/m6tba/romstage.c               |    2 
 mainboard/broadcom/blast/romstage.c              |    2 
 mainboard/compaq/deskpro_en_sff_p600/romstage.c  |    2 
 mainboard/dell/s1850/romstage.c                  |    4 
 mainboard/digitallogic/adl855pc/romstage.c       |    2 
 mainboard/digitallogic/msm586seg/romstage.c      |    2 
 mainboard/digitallogic/msm800sev/romstage.c      |    2 
 mainboard/eaglelion/5bcm/romstage.c              |    2 
 mainboard/emulation/qemu-x86/romstage.c          |    2 
 mainboard/gigabyte/ga-6bxc/romstage.c            |    2 
 mainboard/gigabyte/ga_2761gxdk/ap_romstage.c     |   20 -
 mainboard/gigabyte/ga_2761gxdk/romstage.c        |    2 
 mainboard/gigabyte/m57sli/ap_romstage.c          |   20 -
 mainboard/gigabyte/m57sli/romstage.c             |    2 
 mainboard/hp/dl145_g3/romstage.c                 |    2 
 mainboard/hp/e_vectra_p2706t/romstage.c          |    2 
 mainboard/ibm/e325/romstage.c                    |    2 
 mainboard/ibm/e326/romstage.c                    |    2 
 mainboard/iei/juki-511p/romstage.c               |    2 
 mainboard/iei/nova4899r/romstage.c               |    2 
 mainboard/iei/pcisa-lx-800-r10/romstage.c        |    2 
 mainboard/intel/d945gclf/romstage.c              |    2 
 mainboard/intel/eagleheights/romstage.c          |    2 
 mainboard/intel/jarrell/romstage.c               |    4 
 mainboard/intel/mtarvon/romstage.c               |    2 
 mainboard/intel/truxton/romstage.c               |    2 
 mainboard/intel/xe7501devkit/romstage.c          |    2 
 mainboard/iwill/dk8_htx/romstage.c               |    2 
 mainboard/iwill/dk8s2/romstage.c                 |    2 
 mainboard/iwill/dk8x/romstage.c                  |    2 
 mainboard/jetway/j7f24/romstage.c                |    2 
 mainboard/kontron/986lcd-m/romstage.c            |    2
 mainboard/kontron/kt690/romstage.c               |    2 
 mainboard/lippert/frontrunner/romstage.c         |    2 
 mainboard/lippert/roadrunner-lx/romstage.c       |    2 
 mainboard/lippert/spacerunner-lx/romstage.c      |    2 
 mainboard/mitac/6513wu/romstage.c                |    2 
 mainboard/msi/ms6119/romstage.c                  |    2 
 mainboard/msi/ms6147/romstage.c                  |    2 
 mainboard/msi/ms6156/romstage.c                  |    2 
 mainboard/msi/ms6178/romstage.c                  |    2 
 mainboard/msi/ms7135/romstage.c                  |    2 
 mainboard/msi/ms7260/ap_romstage.c               |    6 
 mainboard/msi/ms7260/romstage.c                  |    2 
 mainboard/msi/ms9185/romstage.c                  |    2 
 mainboard/msi/ms9282/romstage.c                  |    2 
 mainboard/msi/ms9652_fam10/romstage.c            |    2 
 mainboard/nec/powermate2000/romstage.c           |    2 
 mainboard/newisys/khepri/romstage.c              |    2 
 mainboard/nvidia/l1_2pvv/ap_romstage.c           |   20 -
 mainboard/nvidia/l1_2pvv/romstage.c              |    2 
 mainboard/olpc/btest/romstage.c                  |    2 
 mainboard/olpc/rev_a/romstage.c                  |    2 
 mainboard/pcengines/alix1c/romstage.c            |    2 
 mainboard/rca/rm4100/romstage.c                  |    2 
 mainboard/roda/rk886ex/romstage.c                |    2 
 mainboard/soyo/sy-6ba-plus-iii/romstage.c        |    2 
 mainboard/sunw/ultra40/romstage.c                |    2 
 mainboard/supermicro/h8dme/ap_romstage.c         |   17 -
 mainboard/supermicro/h8dme/romstage.c            |    2 
 mainboard/supermicro/h8dmr/ap_romstage.c         |   17 -
 mainboard/supermicro/h8dmr/romstage.c            |    2 
 mainboard/supermicro/h8dmr_fam10/romstage.c      |    2 
 mainboard/supermicro/h8qme_fam10/romstage.c      |    2 
 mainboard/supermicro/x6dai_g/romstage.c          |    2 
 mainboard/supermicro/x6dhe_g/romstage.c          |    4 
 mainboard/supermicro/x6dhe_g2/romstage.c         |    4 
 mainboard/supermicro/x6dhr_ig/romstage.c         |    4 
 mainboard/supermicro/x6dhr_ig2/romstage.c        |    4 
 mainboard/technexion/tim5690/romstage.c          |    2 
 mainboard/technexion/tim8690/romstage.c          |    2 
 mainboard/technologic/ts5300/romstage.c          |    2 
 mainboard/televideo/tc7020/romstage.c            |    2 
 mainboard/thomson/ip1000/romstage.c              |    2 
 mainboard/tyan/s1846/romstage.c                  |    2 
 mainboard/tyan/s2735/romstage.c                  |   19 -
 mainboard/tyan/s2850/romstage.c                  |    2 
 mainboard/tyan/s2875/romstage.c                  |    2 
 mainboard/tyan/s2880/romstage.c                  |    2 
 mainboard/tyan/s2881/romstage.c                  |    2 
 mainboard/tyan/s2882/romstage.c                  |    2 
 mainboard/tyan/s2885/romstage.c                  |    2 
 mainboard/tyan/s2891/romstage.c                  |    2 
 mainboard/tyan/s2892/romstage.c                  |    2 
 mainboard/tyan/s2895/romstage.c                  |    2 
 mainboard/tyan/s2912/ap_romstage.c               |    6 
 mainboard/tyan/s2912/romstage.c                  |    2 
 mainboard/tyan/s2912_fam10/romstage.c            |    2 
 mainboard/tyan/s4880/romstage.c                  |    2 
 mainboard/tyan/s4882/romstage.c                  |    2 
 mainboard/via/epia-cn/romstage.c                 |    2 
 mainboard/via/epia-m/romstage.c                  |    2 
 mainboard/via/epia-m700/romstage.c               |   10 
 mainboard/via/epia-n/romstage.c                  |    2 
 mainboard/via/epia/romstage.c                    |    2 
 mainboard/via/pc2500e/romstage.c                 |    2 
 mainboard/via/vt8454c/romstage.c                 |    2 
 mainboard/winent/pl6064/romstage.c               |    2 
 northbridge/amd/amdk8/raminit_test.c             |    2 
 northbridge/intel/e7520/raminit.c                |   66 +++---
 northbridge/intel/e7520/raminit.h                |    6 
 northbridge/via/vx800/examples/romstage.c        |   10 
 142 files changed, 467 insertions(+), 497 deletions(-)

Index: src/Kconfig
===================================================================
--- src/Kconfig	(revision 5336)
+++ src/Kconfig	(working copy)
@@ -796,10 +796,6 @@
 	bool
 	default n
 
-config USE_INIT
-	bool
-	default n
-
 config ENABLE_APIC_EXT_ID
 	bool
 	default n
Index: src/include/console/console.h
===================================================================
--- src/include/console/console.h	(revision 5336)
+++ src/include/console/console.h	(working copy)
@@ -4,6 +4,7 @@
 #include <stdint.h>
 #include <console/loglevel.h>
 
+#ifndef __PRE_RAM__
 void console_init(void);
 void console_tx_byte(unsigned char byte);
 void console_tx_flush(void);
@@ -11,6 +12,9 @@
 int console_tst_byte(void);
 void post_code(uint8_t value);
 void __attribute__ ((noreturn)) die(const char *msg);
+#if CONFIG_CONSOLE_VGA == 1
+void vga_console_init(void);
+#endif
 
 struct console_driver {
 	void (*init)(void);
@@ -27,6 +31,10 @@
 extern struct console_driver econsole_drivers[];
 
 extern int console_loglevel;
+#endif /* !__PRE_RAM__ */
+
+#ifndef __ROMCC__
+// #if CONFIG_USE_PRINTK_IN_CAR
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
 
 #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS
@@ -34,6 +42,10 @@
  * disabling cache as ram for a maximum console log level of 6 and above while
  * it worked fine without. In order to catch such issues reliably we are
  * always doing a function call to do_printk with the full number of arguments.
+ * Our favorite reason to do it this way was:
+ *   disable_car();
+ *   printk(BIOS_DEBUG, "CAR disabled\n"); // oops, garbage stack pointer
+ *   move_stack();
  * This slightly increases the code size and some unprinted strings will end
  * up in the final coreboot binary (most of them compressed). If you want to
  * avoid this, do a
@@ -60,35 +72,35 @@
 	} while(0)
 #endif
 
-#define print_emerg(STR)   printk(BIOS_EMERG,  "%s", (STR))
-#define print_alert(STR)   printk(BIOS_ALERT,  "%s", (STR))
-#define print_crit(STR)    printk(BIOS_CRIT,   "%s", (STR))
-#define print_err(STR)     printk(BIOS_ERR,    "%s", (STR))
-#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR))
-#define print_notice(STR)  printk(BIOS_NOTICE, "%s", (STR))
-#define print_info(STR)    printk(BIOS_INFO,   "%s", (STR))
-#define print_debug(STR)   printk(BIOS_DEBUG,  "%s", (STR))
-#define print_spew(STR)    printk(BIOS_SPEW,   "%s", (STR))
+#define print_emerg(STR)         printk(BIOS_EMERG,  "%s", (STR))
+#define print_alert(STR)         printk(BIOS_ALERT,  "%s", (STR))
+#define print_crit(STR)          printk(BIOS_CRIT,   "%s", (STR))
+#define print_err(STR)           printk(BIOS_ERR,    "%s", (STR))
+#define print_warning(STR)       printk(BIOS_WARNING,"%s", (STR))
+#define print_notice(STR)        printk(BIOS_NOTICE, "%s", (STR))
+#define print_info(STR)          printk(BIOS_INFO,   "%s", (STR))
+#define print_debug(STR)         printk(BIOS_DEBUG,  "%s", (STR))
+#define print_spew(STR)          printk(BIOS_SPEW,   "%s", (STR))
 
-#define print_emerg_char(CH)   printk(BIOS_EMERG,  "%c", (CH))
-#define print_alert_char(CH)   printk(BIOS_ALERT,  "%c", (CH))
-#define print_crit_char(CH)    printk(BIOS_CRIT,   "%c", (CH))
-#define print_err_char(CH)     printk(BIOS_ERR,    "%c", (CH))
-#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH))
-#define print_notice_char(CH)  printk(BIOS_NOTICE, "%c", (CH))
-#define print_info_char(CH)    printk(BIOS_INFO,   "%c", (CH))
-#define print_debug_char(CH)   printk(BIOS_DEBUG,  "%c", (CH))
-#define print_spew_char(CH)    printk(BIOS_SPEW,   "%c", (CH))
+#define print_emerg_char(CH)     printk(BIOS_EMERG,  "%c", (CH))
+#define print_alert_char(CH)     printk(BIOS_ALERT,  "%c", (CH))
+#define print_crit_char(CH)      printk(BIOS_CRIT,   "%c", (CH))
+#define print_err_char(CH)       printk(BIOS_ERR,    "%c", (CH))
+#define print_warning_char(CH)   printk(BIOS_WARNING,"%c", (CH))
+#define print_notice_char(CH)    printk(BIOS_NOTICE, "%c", (CH))
+#define print_info_char(CH)      printk(BIOS_INFO,   "%c", (CH))
+#define print_debug_char(CH)     printk(BIOS_DEBUG,  "%c", (CH))
+#define print_spew_char(CH)      printk(BIOS_SPEW,   "%c", (CH))
 
-#define print_emerg_hex8(HEX)   printk(BIOS_EMERG,  "%02x",  (HEX))
-#define print_alert_hex8(HEX)   printk(BIOS_ALERT,  "%02x",  (HEX))
-#define print_crit_hex8(HEX)    printk(BIOS_CRIT,   "%02x",  (HEX))
-#define print_err_hex8(HEX)     printk(BIOS_ERR,    "%02x",  (HEX))
-#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x",  (HEX))
-#define print_notice_hex8(HEX)  printk(BIOS_NOTICE, "%02x",  (HEX))
-#define print_info_hex8(HEX)    printk(BIOS_INFO,   "%02x",  (HEX))
-#define print_debug_hex8(HEX)   printk(BIOS_DEBUG,  "%02x",  (HEX))
-#define print_spew_hex8(HEX)    printk(BIOS_SPEW,   "%02x",  (HEX))
+#define print_emerg_hex8(HEX)    printk(BIOS_EMERG,  "%02x",  (HEX))
+#define print_alert_hex8(HEX)    printk(BIOS_ALERT,  "%02x",  (HEX))
+#define print_crit_hex8(HEX)     printk(BIOS_CRIT,   "%02x",  (HEX))
+#define print_err_hex8(HEX)      printk(BIOS_ERR,    "%02x",  (HEX))
+#define print_warning_hex8(HEX)  printk(BIOS_WARNING,"%02x",  (HEX))
+#define print_notice_hex8(HEX)   printk(BIOS_NOTICE, "%02x",  (HEX))
+#define print_info_hex8(HEX)     printk(BIOS_INFO,   "%02x",  (HEX))
+#define print_debug_hex8(HEX)    printk(BIOS_DEBUG,  "%02x",  (HEX))
+#define print_spew_hex8(HEX)     printk(BIOS_SPEW,   "%02x",  (HEX))
 
 #define print_emerg_hex16(HEX)   printk(BIOS_EMERG,  "%04x", (HEX))
 #define print_alert_hex16(HEX)   printk(BIOS_ALERT,  "%04x", (HEX))
@@ -109,9 +121,182 @@
 #define print_info_hex32(HEX)    printk(BIOS_INFO,   "%08x", (HEX))
 #define print_debug_hex32(HEX)   printk(BIOS_DEBUG,  "%08x", (HEX))
 #define print_spew_hex32(HEX)    printk(BIOS_SPEW,   "%08x", (HEX))
+#else
+/* __ROMCC__ */
+static void __console_tx_byte(unsigned char byte)
+{
+	uart_tx_byte(byte);
+}
 
-#if CONFIG_CONSOLE_VGA == 1
-void vga_console_init(void);
+static void __console_tx_nibble(unsigned nibble)
+{
+	unsigned char digit;
+	digit = nibble + '0';
+	if (digit > '9') {
+		digit += 39;
+	}
+	__console_tx_byte(digit);
+}
+
+static void __console_tx_char(int loglevel, unsigned char byte)
+{
+	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+		uart_tx_byte(byte);
+	}
+}
+
+static void __console_tx_hex8(int loglevel, unsigned char value)
+{
+	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+		__console_tx_nibble((value >>  4U) & 0x0fU);
+		__console_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_tx_hex16(int loglevel, unsigned short value)
+{
+	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+		__console_tx_nibble((value >> 12U) & 0x0fU);
+		__console_tx_nibble((value >>  8U) & 0x0fU);
+		__console_tx_nibble((value >>  4U) & 0x0fU);
+		__console_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_tx_hex32(int loglevel, unsigned int value)
+{
+	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+		__console_tx_nibble((value >> 28U) & 0x0fU);
+		__console_tx_nibble((value >> 24U) & 0x0fU);
+		__console_tx_nibble((value >> 20U) & 0x0fU);
+		__console_tx_nibble((value >> 16U) & 0x0fU);
+		__console_tx_nibble((value >> 12U) & 0x0fU);
+		__console_tx_nibble((value >>  8U) & 0x0fU);
+		__console_tx_nibble((value >>  4U) & 0x0fU);
+		__console_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_tx_string(int loglevel, const char *str)
+{
+	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+		unsigned char ch;
+		while((ch = *str++) != '\0') {
+			//if (ch == '\n')
+			//	__console_tx_byte('\r');
+			__console_tx_byte(ch);
+		}
+	}
+}
+
+#define FUNCTIONS_FOR_PRINT
+#ifdef  FUNCTIONS_FOR_PRINT
+static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
+static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
+static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
+static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
+static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
+
+static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
+static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
+static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
+static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
+static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
+
+static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
+static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
+static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
+static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
+static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
+
+static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
+static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
+static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
+static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
+static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
+
+static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
+static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
+static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
+static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
+static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
+
+static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
+static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
+static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
+static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
+static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
+
+static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
+static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
+static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
+static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
+static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
+
+static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
+static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
+static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
+static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
+static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
+
+static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
+static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
+static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
+static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
+static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
+
+#else
+#define print_emerg(STR)         __console_tx_string(BIOS_EMERG, STR)
+#define print_alert(STR)         __console_tx_string(BIOS_ALERT, STR)
+#define print_crit(STR)          __console_tx_string(BIOS_CRIT, STR)
+#define print_err(STR)           __console_tx_string(BIOS_ERR, STR)
+#define print_warning(STR)       __console_tx_string(BIOS_WARNING, STR)
+#define print_notice(STR)        __console_tx_string(BIOS_NOTICE, STR)
+#define print_info(STR)          __console_tx_string(BIOS_INFO, STR)
+#define print_debug(STR)         __console_tx_string(BIOS_DEBUG, STR)
+#define print_spew(STR)          __console_tx_string(BIOS_SPEW, STR)
+
+#define print_emerg_char(CH)     __console_tx_char(BIOS_EMERG, CH)
+#define print_alert_char(CH)     __console_tx_char(BIOS_ALERT, CH)
+#define print_crit_char(CH)      __console_tx_char(BIOS_CRIT, CH)
+#define print_err_char(CH)       __console_tx_char(BIOS_ERR, CH)
+#define print_warning_char(CH)   __console_tx_char(BIOS_WARNING, CH)
+#define print_notice_char(CH)    __console_tx_char(BIOS_NOTICE, CH)
+#define print_info_char(CH)      __console_tx_char(BIOS_INFO, CH)
+#define print_debug_char(CH)     __console_tx_char(BIOS_DEBUG, CH)
+#define print_spew_char(CH)      __console_tx_char(BIOS_SPEW, CH)
+
+#define print_emerg_hex8(HEX)    __console_tx_hex8(BIOS_EMERG, HEX)
+#define print_alert_hex8(HEX)    __console_tx_hex8(BIOS_ALERT, HEX)
+#define print_crit_hex8(HEX)     __console_tx_hex8(BIOS_CRIT, HEX)
+#define print_err_hex8(HEX)      __console_tx_hex8(BIOS_ERR, HEX)
+#define print_warning_hex8(HEX)  __console_tx_hex8(BIOS_WARNING, HEX)
+#define print_notice_hex8(HEX)   __console_tx_hex8(BIOS_NOTICE, HEX)
+#define print_info_hex8(HEX)     __console_tx_hex8(BIOS_INFO, HEX)
+#define print_debug_hex8(HEX)    __console_tx_hex8(BIOS_DEBUG, HEX)
+#define print_spew_hex8(HEX)     __console_tx_hex8(BIOS_SPEW, HEX)
+
+#define print_emerg_hex16(HEX)   __console_tx_hex16(BIOS_EMERG, HEX)
+#define print_alert_hex16(HEX)   __console_tx_hex16(BIOS_ALERT, HEX)
+#define print_crit_hex16(HEX)    __console_tx_hex16(BIOS_CRIT, HEX)
+#define print_err_hex16(HEX)     __console_tx_hex16(BIOS_ERR, HEX)
+#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX)
+#define print_notice_hex16(HEX)  __console_tx_hex16(BIOS_NOTICE, HEX)
+#define print_info_hex16(HEX)    __console_tx_hex16(BIOS_INFO, HEX)
+#define print_debug_hex16(HEX)   __console_tx_hex16(BIOS_DEBUG, HEX)
+#define print_spew_hex16(HEX)    __console_tx_hex16(BIOS_SPEW, HEX)
+
+#define print_emerg_hex32(HEX)   __console_tx_hex32(BIOS_EMERG, HEX)
+#define print_alert_hex32(HEX)   __console_tx_hex32(BIOS_ALERT, HEX)
+#define print_crit_hex32(HEX)    __console_tx_hex32(BIOS_CRIT, HEX)
+#define print_err_hex32(HEX)     __console_tx_hex32(BIOS_ERR, HEX)
+#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX)
+#define print_notice_hex32(HEX)  __console_tx_hex32(BIOS_NOTICE, HEX)
+#define print_info_hex32(HEX)    __console_tx_hex32(BIOS_INFO, HEX)
+#define print_debug_hex32(HEX)   __console_tx_hex32(BIOS_DEBUG, HEX)
+#define print_spew_hex32(HEX)    __console_tx_hex32(BIOS_SPEW, HEX)
 #endif
 
+#endif
+
 #endif /* CONSOLE_CONSOLE_H_ */
Index: src/mainboard/iwill/dk8_htx/romstage.c
===================================================================
--- src/mainboard/iwill/dk8_htx/romstage.c	(revision 5336)
+++ src/mainboard/iwill/dk8_htx/romstage.c	(working copy)
@@ -30,7 +30,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/iwill/dk8s2/romstage.c
===================================================================
--- src/mainboard/iwill/dk8s2/romstage.c	(revision 5336)
+++ src/mainboard/iwill/dk8s2/romstage.c	(working copy)
@@ -30,7 +30,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/iwill/dk8x/romstage.c
===================================================================
--- src/mainboard/iwill/dk8x/romstage.c	(revision 5336)
+++ src/mainboard/iwill/dk8x/romstage.c	(working copy)
@@ -30,7 +30,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/axus/tc320/romstage.c
===================================================================
--- src/mainboard/axus/tc320/romstage.c	(revision 5336)
+++ src/mainboard/axus/tc320/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/bcom/winnetp680/romstage.c
===================================================================
--- src/mainboard/bcom/winnetp680/romstage.c	(revision 5336)
+++ src/mainboard/bcom/winnetp680/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/bcom/winnet100/romstage.c
===================================================================
--- src/mainboard/bcom/winnet100/romstage.c	(revision 5336)
+++ src/mainboard/bcom/winnet100/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/televideo/tc7020/romstage.c
===================================================================
--- src/mainboard/televideo/tc7020/romstage.c	(revision 5336)
+++ src/mainboard/televideo/tc7020/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/broadcom/blast/romstage.c
===================================================================
--- src/mainboard/broadcom/blast/romstage.c	(revision 5336)
+++ src/mainboard/broadcom/blast/romstage.c	(working copy)
@@ -14,7 +14,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #if 0
Index: src/mainboard/thomson/ip1000/romstage.c
===================================================================
--- src/mainboard/thomson/ip1000/romstage.c	(revision 5336)
+++ src/mainboard/thomson/ip1000/romstage.c	(working copy)
@@ -28,7 +28,7 @@
 #include <arch/llshell.h>
 #include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
Index: src/mainboard/supermicro/x6dai_g/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/x6dai_g/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
 #include "northbridge/intel/e7525/raminit.h"
Index: src/mainboard/supermicro/h8dmr/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/h8dmr/romstage.c	(working copy)
@@ -53,7 +53,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/supermicro/h8dmr/ap_romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/ap_romstage.c	(revision 5336)
+++ src/mainboard/supermicro/h8dmr/ap_romstage.c	(working copy)
@@ -43,26 +43,11 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 
-#if CONFIG_USE_INIT == 0
-        #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/uart8250.c"
 #include "console/vtxprintf.c"
 #include "./arch/i386/lib/printk_init.c"
 
-#if 0 
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/supermicro/x6dhe_g/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/x6dhe_g/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
@@ -62,10 +62,12 @@
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
+			/*
 			.f0 = PCI_DEV(0, 0x00, 0),
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
+			*/
 			.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
 			.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
 		}
Index: src/mainboard/supermicro/h8dme/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/h8dme/romstage.c	(working copy)
@@ -50,7 +50,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/supermicro/h8dme/ap_romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/ap_romstage.c	(revision 5336)
+++ src/mainboard/supermicro/h8dme/ap_romstage.c	(working copy)
@@ -43,26 +43,11 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 
-#if CONFIG_USE_INIT == 0
-        #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/uart8250.c"
 #include "console/vtxprintf.c"
 #include "./arch/i386/lib/printk_init.c"
 
-#if 0 
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/supermicro/h8dmr_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/h8dmr_fam10/romstage.c	(working copy)
@@ -47,7 +47,7 @@
 // for enable the FAN
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>
Index: src/mainboard/supermicro/x6dhe_g2/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/x6dhe_g2/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
@@ -62,10 +62,12 @@
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
+			/*
 			.f0 = PCI_DEV(0, 0x00, 0),
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
+			*/
 		    	.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
 			.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
 
Index: src/mainboard/supermicro/h8qme_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/h8qme_fam10/romstage.c	(working copy)
@@ -48,7 +48,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>
Index: src/mainboard/supermicro/x6dhr_ig/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/x6dhr_ig/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
@@ -63,10 +63,12 @@
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
+			/*
 			.f0 = PCI_DEV(0, 0x00, 0),
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
+			*/
 			.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
 			.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
 		}
Index: src/mainboard/supermicro/x6dhr_ig2/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/romstage.c	(revision 5336)
+++ src/mainboard/supermicro/x6dhr_ig2/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
@@ -63,10 +63,12 @@
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
+			/*
 			.f0 = PCI_DEV(0, 0x00, 0),
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
+			*/
 			.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
 			.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
 		}
Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
===================================================================
--- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(revision 5336)
+++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/kontron/986lcd-m/romstage.c
===================================================================
--- src/mainboard/kontron/986lcd-m/romstage.c	(revision 5336)
+++ src/mainboard/kontron/986lcd-m/romstage.c	(working copy)
@@ -47,7 +47,7 @@
 
 #include <console/console.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT
Index: src/mainboard/kontron/kt690/romstage.c
===================================================================
--- src/mainboard/kontron/kt690/romstage.c	(revision 5336)
+++ src/mainboard/kontron/kt690/romstage.c	(working copy)
@@ -44,7 +44,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #define post_code(x) outb(x, 0x80)
 
Index: src/mainboard/a-trend/atc-6240/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6240/romstage.c	(revision 5336)
+++ src/mainboard/a-trend/atc-6240/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/a-trend/atc-6220/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6220/romstage.c	(revision 5336)
+++ src/mainboard/a-trend/atc-6220/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/gigabyte/m57sli/ap_romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/ap_romstage.c	(revision 5336)
+++ src/mainboard/gigabyte/m57sli/ap_romstage.c	(working copy)
@@ -43,23 +43,11 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 
-#if CONFIG_USE_INIT == 0
-        #include "lib/memcpy.c"
-#endif
+#include "lib/uart8250.c"
+#include "arch/i386/lib/printk_init.c"
+#include "console/vtxprintf.c"
+#include "console/console.c"
 
-#include "arch/i386/lib/console.c"
-
-#if 0 
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/gigabyte/m57sli/romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/romstage.c	(revision 5336)
+++ src/mainboard/gigabyte/m57sli/romstage.c	(working copy)
@@ -52,7 +52,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/gigabyte/ga_2761gxdk/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(revision 5336)
+++ src/mainboard/gigabyte/ga_2761gxdk/romstage.c	(working copy)
@@ -54,7 +54,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	(revision 5336)
+++ src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	(working copy)
@@ -45,23 +45,11 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 
-#if CONFIG_USE_INIT == 0
-        #include "lib/memcpy.c"
-#endif
+#include "lib/uart8250.c"
+#include "arch/i386/lib/printk_init.c"
+#include "console/vtxprintf.c"
+#include "console/console.c"
 
-#include "arch/i386/lib/console.c"
-
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/gigabyte/ga-6bxc/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/romstage.c	(revision 5336)
+++ src/mainboard/gigabyte/ga-6bxc/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/digitallogic/msm800sev/romstage.c
===================================================================
--- src/mainboard/digitallogic/msm800sev/romstage.c	(revision 5336)
+++ src/mainboard/digitallogic/msm800sev/romstage.c	(working copy)
@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/digitallogic/adl855pc/romstage.c
===================================================================
--- src/mainboard/digitallogic/adl855pc/romstage.c	(revision 5336)
+++ src/mainboard/digitallogic/adl855pc/romstage.c	(working copy)
@@ -12,7 +12,7 @@
 #include <stdlib.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
Index: src/mainboard/digitallogic/msm586seg/romstage.c
===================================================================
--- src/mainboard/digitallogic/msm586seg/romstage.c	(revision 5336)
+++ src/mainboard/digitallogic/msm586seg/romstage.c	(working copy)
@@ -7,7 +7,7 @@
 #include <arch/hlt.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 //#include "lib/delay.c"
Index: src/mainboard/mitac/6513wu/romstage.c
===================================================================
--- src/mainboard/mitac/6513wu/romstage.c	(revision 5336)
+++ src/mainboard/mitac/6513wu/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/olpc/btest/romstage.c
===================================================================
--- src/mainboard/olpc/btest/romstage.c	(revision 5336)
+++ src/mainboard/olpc/btest/romstage.c	(working copy)
@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/olpc/rev_a/romstage.c
===================================================================
--- src/mainboard/olpc/rev_a/romstage.c	(revision 5336)
+++ src/mainboard/olpc/rev_a/romstage.c	(working copy)
@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/emulation/qemu-x86/romstage.c
===================================================================
--- src/mainboard/emulation/qemu-x86/romstage.c	(revision 5336)
+++ src/mainboard/emulation/qemu-x86/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
Index: src/mainboard/technologic/ts5300/romstage.c
===================================================================
--- src/mainboard/technologic/ts5300/romstage.c	(revision 5336)
+++ src/mainboard/technologic/ts5300/romstage.c	(working copy)
@@ -13,7 +13,7 @@
 #include <arch/hlt.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 
Index: src/mainboard/amd/pistachio/romstage.c
===================================================================
--- src/mainboard/amd/pistachio/romstage.c	(revision 5336)
+++ src/mainboard/amd/pistachio/romstage.c	(working copy)
@@ -37,7 +37,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #define post_code(x) outb(x, 0x80)
 
Index: src/mainboard/amd/mahogany/romstage.c
===================================================================
--- src/mainboard/amd/mahogany/romstage.c	(revision 5336)
+++ src/mainboard/amd/mahogany/romstage.c	(working copy)
@@ -43,7 +43,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #define post_code(x) outb(x, 0x80)
 
Index: src/mainboard/amd/dbm690t/romstage.c
===================================================================
--- src/mainboard/amd/dbm690t/romstage.c	(revision 5336)
+++ src/mainboard/amd/dbm690t/romstage.c	(working copy)
@@ -43,7 +43,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #define post_code(x) outb(x, 0x80)
 
Index: src/mainboard/amd/rumba/romstage.c
===================================================================
--- src/mainboard/amd/rumba/romstage.c	(revision 5336)
+++ src/mainboard/amd/rumba/romstage.c	(working copy)
@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/amd/serengeti_cheetah/ap_romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/ap_romstage.c	(revision 5336)
+++ src/mainboard/amd/serengeti_cheetah/ap_romstage.c	(working copy)
@@ -23,25 +23,10 @@
 #include "pc80/serial.c"
 #include "./arch/i386/lib/printk_init.c"
 
-#if CONFIG_USE_INIT == 0
-	#include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/uart8250.c"
 #include "console/vtxprintf.c"
 
-#if 0 
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/amd/serengeti_cheetah/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/romstage.c	(revision 5336)
+++ src/mainboard/amd/serengeti_cheetah/romstage.c	(working copy)
@@ -40,7 +40,7 @@
 }
 #endif
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
Index: src/mainboard/amd/mahogany_fam10/romstage.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/romstage.c	(revision 5336)
+++ src/mainboard/amd/mahogany_fam10/romstage.c	(working copy)
@@ -47,7 +47,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "pc80/serial.c"
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
Index: src/mainboard/amd/norwich/romstage.c
===================================================================
--- src/mainboard/amd/norwich/romstage.c	(revision 5336)
+++ src/mainboard/amd/norwich/romstage.c	(working copy)
@@ -24,7 +24,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(revision 5336)
+++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	(working copy)
@@ -47,7 +47,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "pc80/serial.c"
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
Index: src/mainboard/amd/db800/romstage.c
===================================================================
--- src/mainboard/amd/db800/romstage.c	(revision 5336)
+++ src/mainboard/amd/db800/romstage.c	(working copy)
@@ -24,7 +24,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/biostar/m6tba/romstage.c
===================================================================
--- src/mainboard/biostar/m6tba/romstage.c	(revision 5336)
+++ src/mainboard/biostar/m6tba/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/rca/rm4100/romstage.c
===================================================================
--- src/mainboard/rca/rm4100/romstage.c	(revision 5336)
+++ src/mainboard/rca/rm4100/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
Index: src/mainboard/nec/powermate2000/romstage.c
===================================================================
--- src/mainboard/nec/powermate2000/romstage.c	(revision 5336)
+++ src/mainboard/nec/powermate2000/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/azza/pt-6ibd/romstage.c
===================================================================
--- src/mainboard/azza/pt-6ibd/romstage.c	(revision 5336)
+++ src/mainboard/azza/pt-6ibd/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/iei/nova4899r/romstage.c
===================================================================
--- src/mainboard/iei/nova4899r/romstage.c	(revision 5336)
+++ src/mainboard/iei/nova4899r/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
Index: src/mainboard/iei/pcisa-lx-800-r10/romstage.c
===================================================================
--- src/mainboard/iei/pcisa-lx-800-r10/romstage.c	(revision 5336)
+++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c	(working copy)
@@ -24,7 +24,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/iei/juki-511p/romstage.c
===================================================================
--- src/mainboard/iei/juki-511p/romstage.c	(revision 5336)
+++ src/mainboard/iei/juki-511p/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
Index: src/mainboard/hp/dl145_g3/romstage.c
===================================================================
--- src/mainboard/hp/dl145_g3/romstage.c	(revision 5336)
+++ src/mainboard/hp/dl145_g3/romstage.c	(working copy)
@@ -58,7 +58,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/hp/e_vectra_p2706t/romstage.c
===================================================================
--- src/mainboard/hp/e_vectra_p2706t/romstage.c	(revision 5336)
+++ src/mainboard/hp/e_vectra_p2706t/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 /* TODO: It's a PC87364 actually! */
 #include "superio/nsc/pc87360/pc87360_early_serial.c"
Index: src/mainboard/tyan/s2912/ap_romstage.c
===================================================================
--- src/mainboard/tyan/s2912/ap_romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2912/ap_romstage.c	(working copy)
@@ -43,12 +43,8 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 
-#if CONFIG_USE_INIT == 0
-	#include "lib/memcpy.c"
-#endif
+#include "console/console.c"
 
-#include "arch/i386/lib/console.c"
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/tyan/s2912/romstage.c
===================================================================
--- src/mainboard/tyan/s2912/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2912/romstage.c	(working copy)
@@ -52,7 +52,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/tyan/s2850/romstage.c
===================================================================
--- src/mainboard/tyan/s2850/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2850/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #if 0
Index: src/mainboard/tyan/s2735/romstage.c
===================================================================
--- src/mainboard/tyan/s2735/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2735/romstage.c	(working copy)
@@ -9,20 +9,9 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 
@@ -139,7 +128,7 @@
         	        "movl   %%esp, %0\n\t"
 	                : "=a" (v_esp)
 	        );
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 	        printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
 #else
 	        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
@@ -151,7 +140,7 @@
 
 cpu_reset_x:
 
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
         printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset);
 #else
         print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
@@ -200,7 +189,7 @@
                 {  
                         print_debug("Use Ram as Stack now - \r\n");
                 }
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
                 printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
 #else
                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
Index: src/mainboard/tyan/s2880/romstage.c
===================================================================
--- src/mainboard/tyan/s2880/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2880/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2881/romstage.c
===================================================================
--- src/mainboard/tyan/s2881/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2881/romstage.c	(working copy)
@@ -14,7 +14,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #if 0
Index: src/mainboard/tyan/s1846/romstage.c
===================================================================
--- src/mainboard/tyan/s1846/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s1846/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/tyan/s4880/romstage.c
===================================================================
--- src/mainboard/tyan/s4880/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s4880/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2891/romstage.c
===================================================================
--- src/mainboard/tyan/s2891/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2891/romstage.c	(working copy)
@@ -15,7 +15,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2882/romstage.c
===================================================================
--- src/mainboard/tyan/s2882/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2882/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2892/romstage.c
===================================================================
--- src/mainboard/tyan/s2892/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2892/romstage.c	(working copy)
@@ -15,7 +15,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s4882/romstage.c
===================================================================
--- src/mainboard/tyan/s4882/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s4882/romstage.c	(working copy)
@@ -9,7 +9,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2875/romstage.c
===================================================================
--- src/mainboard/tyan/s2875/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2875/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2885/romstage.c
===================================================================
--- src/mainboard/tyan/s2885/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2885/romstage.c	(working copy)
@@ -9,7 +9,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #if 0
Index: src/mainboard/tyan/s2895/romstage.c
===================================================================
--- src/mainboard/tyan/s2895/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2895/romstage.c	(working copy)
@@ -17,7 +17,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/tyan/s2912_fam10/romstage.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/romstage.c	(revision 5336)
+++ src/mainboard/tyan/s2912_fam10/romstage.c	(working copy)
@@ -46,7 +46,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/pcengines/alix1c/romstage.c
===================================================================
--- src/mainboard/pcengines/alix1c/romstage.c	(revision 5336)
+++ src/mainboard/pcengines/alix1c/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/artecgroup/dbe61/romstage.c
===================================================================
--- src/mainboard/artecgroup/dbe61/romstage.c	(revision 5336)
+++ src/mainboard/artecgroup/dbe61/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/asi/mb_5blgp/romstage.c
===================================================================
--- src/mainboard/asi/mb_5blgp/romstage.c	(revision 5336)
+++ src/mainboard/asi/mb_5blgp/romstage.c	(working copy)
@@ -24,7 +24,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/asi/mb_5blmp/romstage.c
===================================================================
--- src/mainboard/asi/mb_5blmp/romstage.c	(revision 5336)
+++ src/mainboard/asi/mb_5blmp/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
Index: src/mainboard/abit/be6-ii_v2_0/romstage.c
===================================================================
--- src/mainboard/abit/be6-ii_v2_0/romstage.c	(revision 5336)
+++ src/mainboard/abit/be6-ii_v2_0/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/lippert/roadrunner-lx/romstage.c
===================================================================
--- src/mainboard/lippert/roadrunner-lx/romstage.c	(revision 5336)
+++ src/mainboard/lippert/roadrunner-lx/romstage.c	(working copy)
@@ -28,7 +28,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/lippert/frontrunner/romstage.c
===================================================================
--- src/mainboard/lippert/frontrunner/romstage.c	(revision 5336)
+++ src/mainboard/lippert/frontrunner/romstage.c	(working copy)
@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/lippert/spacerunner-lx/romstage.c
===================================================================
--- src/mainboard/lippert/spacerunner-lx/romstage.c	(revision 5336)
+++ src/mainboard/lippert/spacerunner-lx/romstage.c	(working copy)
@@ -29,7 +29,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/via/epia-m700/romstage.c
===================================================================
--- src/mainboard/via/epia-m700/romstage.c	(revision 5336)
+++ src/mainboard/via/epia-m700/romstage.c	(working copy)
@@ -33,16 +33,14 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/vx800/vx800.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
 #include <string.h>
-#endif
 #include "cpu/x86/lapic/boot_cpu.c"
 
 /* This file contains the board-special SI value for raminit.c. */
@@ -726,7 +724,7 @@
 		 */
 		unsigned v_esp;
 		__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 		printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
 #else
 		print_debug("v_esp=");
@@ -745,7 +743,7 @@
 	 */
 	cpu_reset = 0;
 
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 	printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
 #else
 	print_debug("cpu_reset = ");
@@ -795,7 +793,7 @@
 		else
 			print_debug("Use Ram as Stack now - \r\n");
 
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 		printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
 #else
 		print_debug("new_cpu_reset = ");
Index: src/mainboard/via/vt8454c/romstage.c
===================================================================
--- src/mainboard/via/vt8454c/romstage.c	(revision 5336)
+++ src/mainboard/via/vt8454c/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/cx700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/epia-m/romstage.c
===================================================================
--- src/mainboard/via/epia-m/romstage.c	(revision 5336)
+++ src/mainboard/via/epia-m/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/vt8623/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/epia-n/romstage.c
===================================================================
--- src/mainboard/via/epia-n/romstage.c	(revision 5336)
+++ src/mainboard/via/epia-n/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/cn400/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/epia-cn/romstage.c
===================================================================
--- src/mainboard/via/epia-cn/romstage.c	(revision 5336)
+++ src/mainboard/via/epia-cn/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/epia/romstage.c
===================================================================
--- src/mainboard/via/epia/romstage.c	(revision 5336)
+++ src/mainboard/via/epia/romstage.c	(working copy)
@@ -6,7 +6,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/vt8601/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/via/pc2500e/romstage.c
===================================================================
--- src/mainboard/via/pc2500e/romstage.c	(revision 5336)
+++ src/mainboard/via/pc2500e/romstage.c	(working copy)
@@ -28,7 +28,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/dell/s1850/romstage.c
===================================================================
--- src/mainboard/dell/s1850/romstage.c	(revision 5336)
+++ src/mainboard/dell/s1850/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
@@ -170,10 +170,12 @@
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
+			/*
 			.f0 = PCI_DEV(0, 0x00, 0),
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
+			*/
 			/* the wiring on this part is really messed up */
 			/* this is my best guess so far */
 			.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
Index: src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
===================================================================
--- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(revision 5336)
+++ src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/roda/rk886ex/romstage.c
===================================================================
--- src/mainboard/roda/rk886ex/romstage.c	(revision 5336)
+++ src/mainboard/roda/rk886ex/romstage.c	(working copy)
@@ -40,7 +40,7 @@
 
 #include <console/console.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT
Index: src/mainboard/msi/ms7135/romstage.c
===================================================================
--- src/mainboard/msi/ms7135/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms7135/romstage.c	(working copy)
@@ -51,7 +51,7 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
Index: src/mainboard/msi/ms6119/romstage.c
===================================================================
--- src/mainboard/msi/ms6119/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms6119/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/msi/ms6147/romstage.c
===================================================================
--- src/mainboard/msi/ms6147/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms6147/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/msi/ms6156/romstage.c
===================================================================
--- src/mainboard/msi/ms6156/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms6156/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/msi/ms9282/romstage.c
===================================================================
--- src/mainboard/msi/ms9282/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms9282/romstage.c	(working copy)
@@ -45,7 +45,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
Index: src/mainboard/msi/ms6178/romstage.c
===================================================================
--- src/mainboard/msi/ms6178/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms6178/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/msi/ms9185/romstage.c
===================================================================
--- src/mainboard/msi/ms9185/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms9185/romstage.c	(working copy)
@@ -50,7 +50,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #if 0
 static void post_code(uint8_t value) {
Index: src/mainboard/msi/ms9652_fam10/romstage.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms9652_fam10/romstage.c	(working copy)
@@ -46,7 +46,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/msi/ms7260/romstage.c
===================================================================
--- src/mainboard/msi/ms7260/romstage.c	(revision 5336)
+++ src/mainboard/msi/ms7260/romstage.c	(working copy)
@@ -56,7 +56,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/msi/ms7260/ap_romstage.c
===================================================================
--- src/mainboard/msi/ms7260/ap_romstage.c	(revision 5336)
+++ src/mainboard/msi/ms7260/ap_romstage.c	(working copy)
@@ -39,10 +39,8 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-#include "arch/i386/lib/console.c"
+
+#include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/arima/hdama/romstage.c
===================================================================
--- src/mainboard/arima/hdama/romstage.c	(revision 5336)
+++ src/mainboard/arima/hdama/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/sunw/ultra40/romstage.c
===================================================================
--- src/mainboard/sunw/ultra40/romstage.c	(revision 5336)
+++ src/mainboard/sunw/ultra40/romstage.c	(working copy)
@@ -17,7 +17,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/advantech/pcm-5820/romstage.c
===================================================================
--- src/mainboard/advantech/pcm-5820/romstage.c	(revision 5336)
+++ src/mainboard/advantech/pcm-5820/romstage.c	(working copy)
@@ -24,7 +24,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
Index: src/mainboard/eaglelion/5bcm/romstage.c
===================================================================
--- src/mainboard/eaglelion/5bcm/romstage.c	(revision 5336)
+++ src/mainboard/eaglelion/5bcm/romstage.c	(working copy)
@@ -6,7 +6,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
Index: src/mainboard/newisys/khepri/romstage.c
===================================================================
--- src/mainboard/newisys/khepri/romstage.c	(revision 5336)
+++ src/mainboard/newisys/khepri/romstage.c	(working copy)
@@ -15,7 +15,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #if 0
Index: src/mainboard/jetway/j7f24/romstage.c
===================================================================
--- src/mainboard/jetway/j7f24/romstage.c	(revision 5336)
+++ src/mainboard/jetway/j7f24/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
Index: src/mainboard/technexion/tim8690/romstage.c
===================================================================
--- src/mainboard/technexion/tim8690/romstage.c	(revision 5336)
+++ src/mainboard/technexion/tim8690/romstage.c	(working copy)
@@ -43,7 +43,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #define post_code(x) outb(x, 0x80)
 
Index: src/mainboard/technexion/tim5690/romstage.c
===================================================================
--- src/mainboard/technexion/tim5690/romstage.c	(revision 5336)
+++ src/mainboard/technexion/tim5690/romstage.c	(working copy)
@@ -43,7 +43,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 
 #define post_code(x) outb(x, 0x80)
 
Index: src/mainboard/winent/pl6064/romstage.c
===================================================================
--- src/mainboard/winent/pl6064/romstage.c	(revision 5336)
+++ src/mainboard/winent/pl6064/romstage.c	(working copy)
@@ -25,7 +25,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
Index: src/mainboard/ibm/e326/romstage.c
===================================================================
--- src/mainboard/ibm/e326/romstage.c	(revision 5336)
+++ src/mainboard/ibm/e326/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/ibm/e325/romstage.c
===================================================================
--- src/mainboard/ibm/e325/romstage.c	(revision 5336)
+++ src/mainboard/ibm/e325/romstage.c	(working copy)
@@ -10,7 +10,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
Index: src/mainboard/nvidia/l1_2pvv/ap_romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/ap_romstage.c	(revision 5336)
+++ src/mainboard/nvidia/l1_2pvv/ap_romstage.c	(working copy)
@@ -43,23 +43,11 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 
-#if CONFIG_USE_INIT == 0
-	#include "lib/memcpy.c"
-#endif
+#include "lib/uart8250.c"
+#include "arch/i386/lib/printk_init.c"
+#include "console/vtxprintf.c"
+#include "console/console.c"
 
-#include "arch/i386/lib/console.c"
-
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-	int i;
-	for(i=0;i<0x80000;i++) {
-		outb(value, 0x80);
-	}
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/nvidia/l1_2pvv/romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/romstage.c	(revision 5336)
+++ src/mainboard/nvidia/l1_2pvv/romstage.c	(working copy)
@@ -52,7 +52,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
Index: src/mainboard/intel/xe7501devkit/romstage.c
===================================================================
--- src/mainboard/intel/xe7501devkit/romstage.c	(revision 5336)
+++ src/mainboard/intel/xe7501devkit/romstage.c	(working copy)
@@ -9,7 +9,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
Index: src/mainboard/intel/d945gclf/romstage.c
===================================================================
--- src/mainboard/intel/d945gclf/romstage.c	(revision 5336)
+++ src/mainboard/intel/d945gclf/romstage.c	(working copy)
@@ -38,7 +38,7 @@
 
 #include <console/console.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT
Index: src/mainboard/intel/truxton/romstage.c
===================================================================
--- src/mainboard/intel/truxton/romstage.c	(revision 5336)
+++ src/mainboard/intel/truxton/romstage.c	(working copy)
@@ -29,7 +29,7 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
Index: src/mainboard/intel/mtarvon/romstage.c
===================================================================
--- src/mainboard/intel/mtarvon/romstage.c	(revision 5336)
+++ src/mainboard/intel/mtarvon/romstage.c	(working copy)
@@ -28,7 +28,7 @@
 #include <cpu/x86/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
Index: src/mainboard/intel/eagleheights/romstage.c
===================================================================
--- src/mainboard/intel/eagleheights/romstage.c	(revision 5336)
+++ src/mainboard/intel/eagleheights/romstage.c	(working copy)
@@ -33,7 +33,7 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #include "lib/ramtest.c"
Index: src/mainboard/intel/jarrell/romstage.c
===================================================================
--- src/mainboard/intel/jarrell/romstage.c	(revision 5336)
+++ src/mainboard/intel/jarrell/romstage.c	(working copy)
@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
@@ -60,10 +60,12 @@
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
+			/*
 			.f0 = PCI_DEV(0, 0x00, 0),
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
+			*/
 			.channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
 			.channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
 		}
Index: src/mainboard/asus/p2b-ls/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ls/romstage.c	(revision 5336)
+++ src/mainboard/asus/p2b-ls/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/mew-am/romstage.c
===================================================================
--- src/mainboard/asus/mew-am/romstage.c	(revision 5336)
+++ src/mainboard/asus/mew-am/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/asus/p2b/romstage.c
===================================================================
--- src/mainboard/asus/p2b/romstage.c	(revision 5336)
+++ src/mainboard/asus/p2b/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/p2b-d/romstage.c
===================================================================
--- src/mainboard/asus/p2b-d/romstage.c	(revision 5336)
+++ src/mainboard/asus/p2b-d/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/p2b-f/romstage.c
===================================================================
--- src/mainboard/asus/p2b-f/romstage.c	(revision 5336)
+++ src/mainboard/asus/p2b-f/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/a8v-e_se/romstage.c
===================================================================
--- src/mainboard/asus/a8v-e_se/romstage.c	(revision 5336)
+++ src/mainboard/asus/a8v-e_se/romstage.c	(working copy)
@@ -47,7 +47,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/mainboard/asus/p2b-ds/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ds/romstage.c	(revision 5336)
+++ src/mainboard/asus/p2b-ds/romstage.c	(working copy)
@@ -27,7 +27,7 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/p3b-f/romstage.c
===================================================================
--- src/mainboard/asus/p3b-f/romstage.c	(revision 5336)
+++ src/mainboard/asus/p3b-f/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Index: src/mainboard/asus/mew-vm/romstage.c
===================================================================
--- src/mainboard/asus/mew-vm/romstage.c	(revision 5336)
+++ src/mainboard/asus/mew-vm/romstage.c	(working copy)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
Index: src/mainboard/asus/a8n_e/romstage.c
===================================================================
--- src/mainboard/asus/a8n_e/romstage.c	(revision 5336)
+++ src/mainboard/asus/a8n_e/romstage.c	(working copy)
@@ -49,7 +49,7 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
Index: src/mainboard/asus/m2v-mx_se/romstage.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/romstage.c	(revision 5336)
+++ src/mainboard/asus/m2v-mx_se/romstage.c	(working copy)
@@ -52,7 +52,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
Index: src/console/console.c
===================================================================
--- src/console/console.c	(revision 5336)
+++ src/console/console.c	(working copy)
@@ -2,8 +2,12 @@
  * Bootstrap code for the INTEL 
  */
 
+#include <console/console.h>
+#include <build.h>
+#include <arch/hlt.h>
+
+#ifndef __PRE_RAM__
 #include <arch/io.h>
-#include <console/console.h>
 #include <string.h>
 #include <pc80/mc146818rtc.h>
 
@@ -86,6 +90,42 @@
 void __attribute__((noreturn)) die(const char *msg)
 {
 	printk(BIOS_EMERG, "%s", msg);
-	post_code(0xff);
-	while (1);		/* Halt */
+	//post_code(0xff);
+ 	for (;;)
+		hlt();		/* Halt */
 }
+
+#else
+
+void console_init(void)
+{
+	static const char console_test[] = 
+		"\r\n\r\ncoreboot-"
+		COREBOOT_VERSION
+		COREBOOT_EXTRA_VERSION
+		" "
+		COREBOOT_BUILD
+		" starting...\r\n";
+	print_info(console_test);
+}
+
+void post_code(u8 value)
+{
+#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
+#if CONFIG_SERIAL_POST==1
+	print_emerg("POST: 0x");
+	print_emerg_hex8(value);
+	print_emerg("\r\n");
+#endif
+	outb(value, 0x80);
+#endif
+}
+
+void die(const char *str)
+{
+	print_emerg(str);
+	do {
+		hlt();
+	} while(1);
+}
+#endif
Index: src/console/Makefile.inc
===================================================================
--- src/console/Makefile.inc	(revision 5336)
+++ src/console/Makefile.inc	(working copy)
@@ -14,3 +14,5 @@
 driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o
 driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o
 driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o
+
+$(obj)/console/console.o : $(obj)/build.h
Index: src/northbridge/via/vx800/examples/romstage.c
===================================================================
--- src/northbridge/via/vx800/examples/romstage.c	(revision 5336)
+++ src/northbridge/via/vx800/examples/romstage.c	(working copy)
@@ -31,16 +31,14 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/vx800/vx800.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
 #include "lib/memcpy.c"
-#endif
 #include "cpu/x86/lapic/boot_cpu.c"
 
 #include "driving_clk_phase_data.c"
@@ -573,7 +571,7 @@
 		unsigned v_esp;
 		__asm__ volatile ("movl   %%esp, %0\n\t":"=a" (v_esp)
 		    );
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 		printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
 #else
 		print_debug("v_esp=");
@@ -589,7 +587,7 @@
 // it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy 
 //stack
 	cpu_reset = 0;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 	printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
 #else
 	print_debug("cpu_reset = ");
@@ -641,7 +639,7 @@
 		} else {
 			print_debug("Use Ram as Stack now - \r\n");
 		}
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 		printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
 #else
 		print_debug("new_cpu_reset = ");
Index: src/northbridge/amd/amdk8/raminit_test.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_test.c	(revision 5336)
+++ src/northbridge/amd/amdk8/raminit_test.c	(working copy)
@@ -124,7 +124,7 @@
 {
 	longjmp(end_buf, 2);
 }
-#include "../../../arch/i386/lib/console.c"
+#include "console/console.c"
 
 unsigned long log2(unsigned long x)
 {
Index: src/northbridge/intel/e7520/raminit.c
===================================================================
--- src/northbridge/intel/e7520/raminit.c	(revision 5336)
+++ src/northbridge/intel/e7520/raminit.c	(working copy)
@@ -67,7 +67,7 @@
 		device_t dev;
 		unsigned where;
 		unsigned long reg;
-		dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
+		dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + PCI_DEV(0, 0x00, 0);
 		where = register_values[i] & 0xff;
 		reg = pci_read_config32(dev, where);
 		reg &= register_values[i+1];
@@ -181,27 +181,27 @@
 			sz.side1 -= 29;
 			cum += (1 << sz.side1);
 			/* DRB = 0x60 */
-			pci_write_config8(ctrl->f0, DRB + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
 			if( sz.side2 > 28) {
 				sz.side2 -= 29;
 				cum += (1 << sz.side2);
 			}
-			pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
 		}
 		else {
-			pci_write_config8(ctrl->f0, DRB + (i*2), cum);
-			pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
+			pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
 		}
 	}
 	/* set TOM top of memory 0xcc */
-	pci_write_config16(ctrl->f0, TOM, cum);
+	pci_write_config16(PCI_DEV(0, 0x00, 0), TOM, cum);
 	/* set TOLM top of low memory */
 	if(cum > 0x18) {
 		cum = 0x18;
 	}
 	cum <<= 11;
 	/* 0xc4 TOLM */
-	pci_write_config16(ctrl->f0, TOLM, cum);
+	pci_write_config16(PCI_DEV(0, 0x00, 0), TOLM, cum);
 	return 0;
 }
 
@@ -279,7 +279,7 @@
 	}
 
 	/* 0x70 DRA */
-	pci_write_config32(ctrl->f0, DRA, dra);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra);	
 	goto out;
 
  val_err:
@@ -309,7 +309,7 @@
 	static const int latency_indicies[] = { 26, 23, 9 };
 
 	/* 0x78 DRT */
-	drt = pci_read_config32(ctrl->f0, DRT);
+	drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT);
 	drt &= 3;  /* save bits 1:0 */
 	
 	for(first_dimm = 0; first_dimm < 4; first_dimm++) {
@@ -542,7 +542,7 @@
 	}
 
 	/* 0x78 DRT */
-	pci_write_config32(ctrl->f0, DRT, drt);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRT, drt);
 
 	return(cas_latency);
 }
@@ -563,7 +563,7 @@
 	static const unsigned char fsb_conversion[4] = {3,1,3,2};
 
 	/* 0x7c DRC */
-	drc = pci_read_config32(ctrl->f0, DRC);	
+	drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC);	
 	for(cnt=0; cnt < 4; cnt++) {
 		if (!(dimm_mask & (1 << cnt))) {
 			continue;
@@ -727,12 +727,12 @@
  
 	/* Set up northbridge values */
 	/* ODT enable */
-  	pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
+  	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180);
 	/* Figure out which slots are Empty, Single, or Double sided */
 	for(i=0,t4=0,c2=0;i<8;i+=2) {
-		c1 = pci_read_config8(ctrl->f0, DRB+i);
+		c1 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+i);
 		if(c1 == c2) continue;
-		c2 = pci_read_config8(ctrl->f0, DRB+1+i);
+		c2 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+1+i);
 		if(c1 == c2)
 			t4 |= (1 << (i*4));
 		else
@@ -778,7 +778,7 @@
 	print_debug_hex32(data32);
 	print_debug("\r\n");
 
-  	pci_write_config32(ctrl->f0, 0xb0, data32);
+  	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32);
 
 	for(dimm=0;dimm<8;dimm+=1) {
 
@@ -1079,10 +1079,10 @@
 
 	/* 0x80 */
 #ifdef DIMM_MAP_LOGICAL
-	pci_write_config32(ctrl->f0, DRM,
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRM,
 		0x00210000 | DIMM_MAP_LOGICAL);
 #else
-	pci_write_config32(ctrl->f0, DRM, 0x00211248);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248);
 #endif
 	/* set dram type and Front Side Bus freq. */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
@@ -1097,20 +1097,20 @@
   	/* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
   	for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
 			cnt<4;cnt++) {
-  		pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
+  		pci_write_config32(PCI_DEV(0, 0x00, 0), 0xa0+(cnt*4), iptr[cnt]);
 	}
 	/* 0x7c DRC */
-  	pci_write_config32(ctrl->f0, DRC, data32);
+  	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
 	
 		/* turn the clocks on */
 	/* 0x8c CKDIS */
-  	pci_write_config16(ctrl->f0, CKDIS, 0x0000);
+  	pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000);
 	
 		/* 0x9a DDRCSR Take subsystem out of idle */
-  	data16 = pci_read_config16(ctrl->f0, DDRCSR);
+  	data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR);
 	data16 &= ~(7 << 12);
 	data16 |= (3 << 12);   /* use dual channel lock step */
-  	pci_write_config16(ctrl->f0, DDRCSR, data16);
+  	pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16);
 	
 		/* program row size DRB */
 	spd_set_ram_size(ctrl, mask);
@@ -1287,23 +1287,23 @@
 		set_on_dimm_termination_enable(ctrl);
 	}
 	else { /* ddr */
-                pci_write_config32(ctrl->f0, 0x88, 0xa0000000 );
+                pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 );
         }
 
 	/* receive enable calibration */
 	set_receive_enable(ctrl);
 	
 	/* DQS */
-	pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); 
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); 
 	for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
 		write32(cnt, dqs_data[i]);
 	}
-	pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
 
 	/* Enable refresh */
 	/* 0x7c DRC */
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
-	pci_write_config32(ctrl->f0, DRC, data32);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);	
 	write32(BAR+DCALCSR, 0x0008000f);
 
 	/* clear memory and init ECC */
@@ -1320,13 +1320,13 @@
 	}
 
 	/* Bring memory subsystem on line */
-	data32 = pci_read_config32(ctrl->f0, 0x98);
+	data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
 	data32 |= (1 << 31);
-	pci_write_config32(ctrl->f0, 0x98, data32);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
 	/* wait for completion */
 	print_debug("Waiting for mem complete\r\n");
 	while(1) {
-		data32 = pci_read_config32(ctrl->f0, 0x98);
+		data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
 		if( (data32 & (1<<31)) == 0)
 			break;
 	}
@@ -1336,17 +1336,17 @@
 	/* 0x7c DRC */
 	drc |= (1 << 29);
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
-	pci_write_config32(ctrl->f0, DRC, data32);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);	
 
 	/* Set the ecc mode */
-	pci_write_config32(ctrl->f0, DRC, drc);	
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc);	
 
 	/* Enable memory scrubbing */
 	/* 0x52 MCHSCRB */	
-	data16 = pci_read_config16(ctrl->f0, MCHSCRB);
+	data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB);
 	data16 &= ~0x0f;
 	data16 |= ((2 << 2) | (2 << 0));
-	pci_write_config16(ctrl->f0, MCHSCRB, data16);	
+	pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16);	
 
 	/* The memory is now setup, use it */
 	cache_lbmem(MTRR_TYPE_WRBACK);
Index: src/northbridge/intel/e7520/raminit.h
===================================================================
--- src/northbridge/intel/e7520/raminit.h	(revision 5336)
+++ src/northbridge/intel/e7520/raminit.h	(working copy)
@@ -4,9 +4,9 @@
 #define DIMM_SOCKETS 4
 struct mem_controller {
 	unsigned node_id;
-	device_t f0, f1, f2, f3;
-	uint16_t channel0[DIMM_SOCKETS];
-	uint16_t channel1[DIMM_SOCKETS];
+	// device_t f0, f1, f2, f3;
+	u16 channel0[DIMM_SOCKETS];
+	u16 channel1[DIMM_SOCKETS];
 };
 
 #endif /* RAMINIT_H */
Index: src/arch/i386/lib/console.c
===================================================================
--- src/arch/i386/lib/console.c	(revision 5330)
+++ src/arch/i386/lib/console.c	(working copy)
@@ -1,41 +0,0 @@
-#include <build.h>
-#include <console/loglevel.h>
-
-#if CONFIG_USE_PRINTK_IN_CAR == 0
-#include "console_print.c"
-#else  /* CONFIG_USE_PRINTK_IN_CAR == 1 */
-#include <console/console.h>
-#endif /* CONFIG_USE_PRINTK_IN_CAR */
-
-void console_init(void)
-{
-	static const char console_test[] = 
-		"\r\n\r\ncoreboot-"
-		COREBOOT_VERSION
-		COREBOOT_EXTRA_VERSION
-		" "
-		COREBOOT_BUILD
-		" starting...\r\n";
-	print_info(console_test);
-}
-
-
-void post_code(u8 value)
-{
-#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
-#if CONFIG_SERIAL_POST==1
-	print_emerg("POST: 0x");
-	print_emerg_hex8(value);
-	print_emerg("\r\n");
-#endif
-	outb(value, 0x80);
-#endif
-}
-
-void die(const char *str)
-{
-	print_emerg(str);
-	do {
-		hlt();
-	} while(1);
-}
Index: src/arch/i386/lib/console_print.c
===================================================================
--- src/arch/i386/lib/console_print.c	(revision 5330)
+++ src/arch/i386/lib/console_print.c	(working copy)
@@ -1,124 +0,0 @@
-static void __console_tx_byte(unsigned char byte)
-{
-	uart_tx_byte(byte);
-}
-
-static void __console_tx_nibble(unsigned nibble)
-{
-	unsigned char digit;
-	digit = nibble + '0';
-	if (digit > '9') {
-		digit += 39;
-	}
-	__console_tx_byte(digit);
-}
-
-static void __console_tx_char(int loglevel, unsigned char byte)
-{
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
-		uart_tx_byte(byte);
-	}
-}
-
-static void __console_tx_hex8(int loglevel, unsigned char value)
-{
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
-		__console_tx_nibble((value >>  4U) & 0x0fU);
-		__console_tx_nibble(value & 0x0fU);
-	}
-}
-
-static void __console_tx_hex16(int loglevel, unsigned short value)
-{
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
-		__console_tx_nibble((value >> 12U) & 0x0fU);
-		__console_tx_nibble((value >>  8U) & 0x0fU);
-		__console_tx_nibble((value >>  4U) & 0x0fU);
-		__console_tx_nibble(value & 0x0fU);
-	}
-}
-
-static void __console_tx_hex32(int loglevel, unsigned int value)
-{
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
-		__console_tx_nibble((value >> 28U) & 0x0fU);
-		__console_tx_nibble((value >> 24U) & 0x0fU);
-		__console_tx_nibble((value >> 20U) & 0x0fU);
-		__console_tx_nibble((value >> 16U) & 0x0fU);
-		__console_tx_nibble((value >> 12U) & 0x0fU);
-		__console_tx_nibble((value >>  8U) & 0x0fU);
-		__console_tx_nibble((value >>  4U) & 0x0fU);
-		__console_tx_nibble(value & 0x0fU);
-	}
-}
-
-static void __console_tx_string(int loglevel, const char *str)
-{
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
-		unsigned char ch;
-		while((ch = *str++) != '\0') {
-			__console_tx_byte(ch);
-		}
-	}
-}
-
-#if defined (__ROMCC__)
-#define STATIC
-#else
-#define STATIC static
-#endif
-
-STATIC void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
-STATIC void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
-STATIC void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
-STATIC void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
-STATIC void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
-
-STATIC void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
-STATIC void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
-STATIC void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
-STATIC void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
-STATIC void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
-
-STATIC void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
-STATIC void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
-STATIC void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
-STATIC void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
-STATIC void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
-
-STATIC void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
-STATIC void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
-STATIC void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
-STATIC void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
-STATIC void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
-
-STATIC void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
-STATIC void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
-STATIC void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
-STATIC void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
-STATIC void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
-
-STATIC void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
-STATIC void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
-STATIC void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
-STATIC void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
-STATIC void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
-
-STATIC void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
-STATIC void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
-STATIC void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
-STATIC void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
-STATIC void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
-
-STATIC void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
-STATIC void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
-STATIC void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
-STATIC void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
-STATIC void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
-
-STATIC void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
-STATIC void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
-STATIC void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
-STATIC void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
-STATIC void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
-
