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On 13/04/2010 11:56 PM, Stefan Reinauer wrote:
<blockquote cite="mid:4BC56722.8000709@coresystems.de" type="cite">
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On 4/14/10 4:18 AM, Dustin Harrison wrote:<br>
<br>
<blockquote cite="mid:4BC525E1.6010802@sutus.com" type="cite">
<div class="moz-text-flowed"
style="font-family: -moz-fixed; font-size: 13px;" lang="x-western">I've
put
several print_info statements in romstage.c and narrowed it
down to the following line in i3100_early_lpc.c: <br>
<br>
pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1
<< 7)); <br>
<br>
Further debug shows that in general I can not read a value and then use
the value. If I just perfrom a read operation it executes the
instruction and contiues. But if I do a read and try to use a
print_info_hexXX function it just hangs. <br>
</div>
</blockquote>
<br>
Can you try this patch please? <br>
<br>
</blockquote>
Hi Stefan,<br>
<br>
I applied your patch and was able to reproduce the same results as
before -- I can move past the TCO initialization, but then I get stuck
the next time a variable is referenced. In the EP80579 case that is
spd_dump_registers:<br>
<br>
void dump_spd_registers(void)<br>
{<br>
unsigned device;<br>
device = SMBUS_MEM_DEVICE_START;<br>
while(device <= SMBUS_MEM_DEVICE_END) {<br>
int status = 0;<br>
int i;<br>
print_debug("\n");<br>
print_debug("dimm ");<br>
print_debug_hex8(device);<br>
<br>
The print_debug_hex8(device) hangs now. I can re-create this behaviour
simply be doing any sort of read or variable assignment and then try to
use a print_XXX function on the data. For example if I change the
above function to the following:<br>
<br>
Index: src/mainboard/intel/jarrell/debug.c<br>
===================================================================<br>
--- src/mainboard/intel/jarrell/debug.c (revision 5430)<br>
+++ src/mainboard/intel/jarrell/debug.c (working copy)<br>
@@ -275,12 +275,9 @@<br>
while(device <= SMBUS_MEM_DEVICE_END) {<br>
int status = 0;<br>
int i;<br>
- print_debug("\n");<br>
- print_debug("dimm ");<br>
- print_debug_hex8(device);<br>
<br>
for(i = 0; (i < 256) ; i++) {<br>
- unsigned char byte;<br>
+ print_debug("here now.\n");<br>
if ((i % 16) == 0) {<br>
print_debug("\n");<br>
print_debug_hex8(i);<br>
<br>
<br>
I now get stuck on the for loop (I never see "here now"). <br>
I have switched to using the coreboot toolchain and it doesn't seem to
make a difference.<br>
<br>
These are the last few lines of assembly before the jump to the
print_debug_hex8(i) section:<br>
<br>
ffff0aaf: 66 0f 6e c7 movd %edi,%xmm0<br>
ffff0ab3: bc 00 00 00 00 mov $0x0,%esp<br>
ffff0ab8: e9 a8 05 00 00 jmp ffff1065 <L1496><br>
ffff1065 <L1496>:<br>
ffff1065: 66 0f 7e c7 movd %xmm0,%edi<br>
ffff1069: 81 fc 00 01 00 00 cmp $0x100,%esp<br>
ffff106f: 0f 8c 48 fa ff ff jl ffff0abd <L1368><br>
ffff0abd <L1368>: /* At this point we are working on
print_debug_hex8(i) now */<br>
ffff0abd: bd 6a d0 ff ff mov $0xffffd06a,%ebp<br>
<br>
I am also in the process of trying my BIOS in the truxton platform, but
it will take me a while to get things up and going. In the meantime
I'm out of ideas on how to narrow this down any further.<br>
<br>
Cheers<br>
Dustin<br>
<br>
<br>
<br>
<blockquote cite="mid:4BC56722.8000709@coresystems.de" type="cite">
Index: src/southbridge/intel/i3100/i3100_early_lpc.c<br>
===================================================================<br>
--- src/southbridge/intel/i3100/i3100_early_lpc.c (revision 5413)<br>
+++ src/southbridge/intel/i3100/i3100_early_lpc.c (working copy)<br>
@@ -34,13 +34,14 @@<br>
{<br>
device_t dev = PCI_DEV(0x0, 0x1f, 0x0);<br>
<br>
- /* Temporarily enable the ACPI I/O range at 0x4000 */<br>
- pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));<br>
- pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1
<< 7));<br>
+#define ABASE 0x400<br>
+ /* Temporarily enable the ACPI I/O range at ABASE */<br>
+ pci_write_config32(dev, 0x40, ABASE | (1 << 0));<br>
+ pci_write_config8(dev, 0x44, (1 << 7));<br>
<br>
/* Halt the TCO timer, preventing SMI and automatic reboot */<br>
- outw(inw(0x4068) | (1 << 11), 0x4068);<br>
+ outw(inw(ABASE + 0x68) | (1 << 11), ABASE + 0x68);<br>
<br>
/* Disable the ACPI I/O range */<br>
- pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) &
~(1 << 7));<br>
+ pci_write_config8(dev, 0x44, 0);<br>
}<br>
<br>
<br>
<blockquote cite="mid:4BC525E1.6010802@sutus.com" type="cite">
<div class="moz-text-flowed"
style="font-family: -moz-fixed; font-size: 13px;" lang="x-western"><br>
Any ideas on what to try next? Is there a recommended toolchain? <br>
</div>
</blockquote>
Yes, you can compile it with <br>
$ cd coreboot/util/crossgcc<br>
$ sh buildgcc<br>
<br>
coreboot will automatically pick it up. You might have to delete
coreboot/.xcompile in order to have coreboot pick it up.<br>
<br>
Stefan<br>
</blockquote>
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