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On 4/14/10 4:18 AM, Dustin Harrison wrote:<br>
<br>
<blockquote cite="mid:4BC525E1.6010802@sutus.com" type="cite">
<div class="moz-text-flowed"
style="font-family: -moz-fixed; font-size: 13px;" lang="x-western">I've
put several print_info statements in romstage.c and narrowed it
down to the following line in i3100_early_lpc.c:
<br>
<br>
pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1
<< 7));
<br>
<br>
Further debug shows that in general I can not read a value and then use
the value. If I just perfrom a read operation it executes the
instruction and contiues. But if I do a read and try to use a
print_info_hexXX function it just hangs.
<br>
</div>
</blockquote>
<br>
Can you try this patch please? <br>
<br>
Index: src/southbridge/intel/i3100/i3100_early_lpc.c<br>
===================================================================<br>
--- src/southbridge/intel/i3100/i3100_early_lpc.c (revision 5413)<br>
+++ src/southbridge/intel/i3100/i3100_early_lpc.c (working copy)<br>
@@ -34,13 +34,14 @@<br>
{<br>
device_t dev = PCI_DEV(0x0, 0x1f, 0x0);<br>
<br>
- /* Temporarily enable the ACPI I/O range at 0x4000 */<br>
- pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));<br>
- pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1
<< 7));<br>
+#define ABASE 0x400<br>
+ /* Temporarily enable the ACPI I/O range at ABASE */<br>
+ pci_write_config32(dev, 0x40, ABASE | (1 << 0));<br>
+ pci_write_config8(dev, 0x44, (1 << 7));<br>
<br>
/* Halt the TCO timer, preventing SMI and automatic reboot */<br>
- outw(inw(0x4068) | (1 << 11), 0x4068);<br>
+ outw(inw(ABASE + 0x68) | (1 << 11), ABASE + 0x68);<br>
<br>
/* Disable the ACPI I/O range */<br>
- pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) &
~(1 << 7));<br>
+ pci_write_config8(dev, 0x44, 0);<br>
}<br>
<br>
<br>
<blockquote cite="mid:4BC525E1.6010802@sutus.com" type="cite">
<div class="moz-text-flowed"
style="font-family: -moz-fixed; font-size: 13px;" lang="x-western"><br>
Any ideas on what to try next? Is there a recommended toolchain?
<br>
</div>
</blockquote>
Yes, you can compile it with <br>
$ cd coreboot/util/crossgcc<br>
$ sh buildgcc<br>
<br>
coreboot will automatically pick it up. You might have to delete
coreboot/.xcompile in order to have coreboot pick it up.<br>
<br>
Stefan<br>
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