€ coreboot-4.0-r5527 Tue May 11 23:33:46 CEST 2010 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset - coreboot-4.0-r5527 Tue May 11 23:33:46 CEST 2010 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz Interleaved RAM end at 0x00200000 kB Lower RAM end at 0x00200000 kB Ram2.01 Enabling dual channel memory Registered 166Mhz Interleaved RAM end at 0x00400000 kB Adjusting lower RAM end Lower RAM end at 0x003f0000 kB Ram3 ECC enabled ECC enabled Initializing memory: done Initializing memory: done Ram4 v_esp=000cee28 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (409600 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r5527 Tue May 11 23:33:46 CEST 2010 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 0, 0 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 0, 0 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.3 siblings=0 malloc Enter, size 1092, free_mem_ptr 00160000 malloc 00160000 CPU: APIC: 01 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] bus ops PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled PCI: Using configuration type 1 Capability: type 0x07 @ 0xa0 Capability: type 0x08 @ 0xb8 flags: 0x8000 Capability: type 0x07 @ 0xa0 Capability: type 0x08 @ 0xb8 Capability: type 0x08 @ 0xc0 flags: 0x0041 Collapsing PCI: 00:01.0 [1022/7450] Capability: type 0x08 @ 0xc0 flags: 0x0083 Collapsing PCI: 00:03.0 [1022/7460] Capability: type 0x08 @ 0x80 flags: 0x2101 Capability: type 0x08 @ 0x80 Capability: type 0x08 @ 0xa0 flags: 0x2101 Capability: type 0x08 @ 0x80 Capability: type 0x08 @ 0xa0 Capability: type 0x08 @ 0xc0 flags: 0x2101 Capability: type 0x08 @ 0x80 Capability: type 0x08 @ 0xa0 Capability: type 0x08 @ 0xc0 Capability: type 0x08 @ 0x80 flags: 0x2101 Capability: type 0x08 @ 0x80 Capability: type 0x08 @ 0xa0 flags: 0x2101 Capability: type 0x08 @ 0x80 Capability: type 0x08 @ 0xa0 Capability: type 0x08 @ 0xc0 flags: 0x2101 Capability: type 0x08 @ 0x80 Capability: type 0x08 @ 0xa0 Capability: type 0x08 @ 0xc0 PCI: 00:00.0 [1022/7450] bus ops PCI: 00:00.0 [1022/7450] enabled Capability: type 0x07 @ 0xa0 Capability: type 0x08 @ 0xb8 flags: 0x8000 Capability: type 0x07 @ 0xa0 Capability: type 0x08 @ 0xb8 Capability: type 0x08 @ 0xc0 flags: 0x0040 PCI: 00:01.0 count: 0002 static_count: 0002 PCI: 00:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 00:00.0 [1022/7460] bus ops PCI: 00:00.0 [1022/7460] enabled Capability: type 0x08 @ 0xc0 flags: 0x0080 PCI: 00:03.0 count: 0004 static_count: 0002 PCI: 00:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [1022/7450] enabled PCI: 00:01.1 [1022/7451] ops PCI: 00:01.1 [1022/7451] enabled PCI: 00:02.0 [1022/7450] bus ops PCI: 00:02.0 [1022/7450] enabled PCI: 00:02.1 [1022/7451] ops PCI: 00:02.1 [1022/7451] enabled PCI: 00:03.0 [1022/7460] enabled PCI: 00:04.0 [1022/7468] bus ops PCI: 00:04.0 [1022/7468] enabled PCI: 00:04.1 [1022/7469] ops PCI: 00:04.1 [1022/7469] enabled PCI: 00:04.2 [1022/746a] bus ops PCI: 00:04.2 [1022/746a] enabled PCI: 00:04.3 [1022/746b] bus ops PCI: 00:04.3 [1022/746b] enabled PCI: 00:04.4, bad id 0x0 PCI: 00:04.6 [1022/746e] ops PCI: 00:04.6 [1022/746e] enabled PCI: 00:04.7, bad id 0x0 do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 malloc Enter, size 1092, free_mem_ptr 00160444 malloc 00160444 PCI: 01:03.0 [14e4/16a6] enabled malloc Enter, size 1092, free_mem_ptr 00160888 malloc 00160888 PCI: 01:04.0 [14e4/16a6] enabled malloc Enter, size 1092, free_mem_ptr 00160ccc malloc 00160ccc PCI: 01:05.0 [1095/3114] enabled PCI: pci_scan_bus returning with max=001 Capability: type 0x07 @ 0xa0 PCI: 01: Conventional PCI do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 Capability: type 0x07 @ 0xa0 PCI: 02: 133MHz PCI-X do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [1022/7464] bus ops PCI: 03:00.0 [1022/7464] enabled PCI: 03:00.1 [1022/7464] bus ops PCI: 03:00.1 [1022/7464] enabled PCI: 03:06.0 [1002/4752] enabled scan_static_bus for PCI: 03:00.0 scan_static_bus for PCI: 03:00.0 done scan_static_bus for PCI: 03:00.1 scan_static_bus for PCI: 03:00.1 done PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 scan_static_bus for PCI: 00:04.0 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 disabled PNP: 002e.5 disabled PNP: 002e.6 enabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:04.0 done scan_static_bus for PCI: 00:04.2 scan_static_bus for PCI: 00:04.2 done scan_static_bus for PCI: 00:04.3 smbus: PCI: 00:04.3[0]->I2C: 01:70 enabled smbus: PCI: 00:04.3[0]->I2C: 01:50 enabled smbus: PCI: 00:04.3[0]->I2C: 01:51 enabled smbus: PCI: 00:04.3[0]->I2C: 01:52 enabled smbus: PCI: 00:04.3[0]->I2C: 01:53 enabled smbus: PCI: 00:04.3[0]->I2C: 01:54 enabled smbus: PCI: 00:04.3[0]->I2C: 01:55 enabled smbus: PCI: 00:04.3[0]->I2C: 01:56 enabled smbus: PCI: 00:04.3[0]->I2C: 01:57 enabled scan_static_bus for PCI: 00:04.3 done PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus returning with max=003 PCI_DOMAIN: 0000 passpw: enabled PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 03:06.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:03.0 read_resources bus 3 link: 0 PCI: 00:03.0 read_resources bus 3 link: 0 done PCI: 00:04.0 read_resources bus 0 link: 0 PCI: 00:04.0 read_resources bus 0 link: 0 done PCI: 00:04.3 read_resources bus 1 link: 0 I2C: 01:70 missing read_resources I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources I2C: 01:54 missing read_resources I2C: 01:55 missing read_resources I2C: 01:56 missing read_resources I2C: 01:57 missing read_resources PCI: 00:04.3 read_resources bus 1 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:19.0 read_resources bus 0 link: 0 PCI: 00:19.0 read_resources bus 0 link: 0 done PCI: 00:19.0 read_resources bus 0 link: 1 PCI: 00:19.0 read_resources bus 0 link: 1 done PCI: 00:19.0 read_resources bus 0 link: 2 PCI: 00:19.0 read_resources bus 0 link: 2 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL APIC: 01 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 links 3 child on link 0 PCI: 00:01.0 PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8 PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:01.0 links 1 child on link 0 PCI: 01:03.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:03.0 links 0 child on link 0 NULL PCI: 01:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 01:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 01:04.0 links 0 child on link 0 NULL PCI: 01:04.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 01:04.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 01:05.0 links 0 child on link 0 NULL PCI: 01:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 01:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 01:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 01:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 01:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 01:05.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 01:05.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 links 1 child on link 0 NULL PCI: 00:02.1 links 0 child on link 0 NULL PCI: 00:02.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:03.0 links 1 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 links 0 child on link 0 NULL PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 03:00.1 links 0 child on link 0 NULL PCI: 03:00.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 03:00.2 links 0 child on link 0 NULL PCI: 03:01.0 links 0 child on link 0 NULL PCI: 03:06.0 links 0 child on link 0 NULL PCI: 03:06.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 03:06.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 03:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18 PCI: 03:06.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:04.0 links 1 child on link 0 PNP: 002e.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 378 size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.4 links 0 child on link 0 NULL PNP: 002e.4 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.5 links 0 child on link 0 NULL PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base 60 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.6 resource base 64 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62 PNP: 002e.6 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.9 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a links 0 child on link 0 NULL PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 links 0 child on link 0 NULL PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:04.2 links 0 child on link 0 NULL PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10 PCI: 00:04.3 links 1 child on link 0 I2C: 01:70 PCI: 00:04.3 resource base 0 size 100 align 8 gran 8 limit 10000 flags 100 index 58 I2C: 01:70 links 4 child on link 0 I2C: 00:2c I2C: 00:2c links 0 child on link 0 NULL I2C: 01:50 links 0 child on link 0 NULL I2C: 01:51 links 0 child on link 0 NULL I2C: 01:52 links 0 child on link 0 NULL I2C: 01:53 links 0 child on link 0 NULL I2C: 01:54 links 0 child on link 0 NULL I2C: 01:55 links 0 child on link 0 NULL I2C: 01:56 links 0 child on link 0 NULL I2C: 01:57 links 0 child on link 0 NULL PCI: 00:04.5 links 0 child on link 0 NULL PCI: 00:04.6 links 0 child on link 0 NULL PCI: 00:04.6 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:04.6 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 14 PCI: 00:18.1 links 0 child on link 0 NULL PCI: 00:18.2 links 0 child on link 0 NULL PCI: 00:18.3 links 0 child on link 0 NULL PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:19.0 links 3 child on link 0 NULL PCI: 00:19.1 links 0 child on link 0 NULL PCI: 00:19.2 links 0 child on link 0 NULL PCI: 00:19.3 links 0 child on link 0 NULL PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 01:05.0 20 * [0x0 - 0xf] io PCI: 01:05.0 10 * [0x10 - 0x17] io PCI: 01:05.0 18 * [0x18 - 0x1f] io PCI: 01:05.0 14 * [0x20 - 0x23] io PCI: 01:05.0 1c * [0x24 - 0x27] io PCI: 00:01.0 compute_resources_io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 03:06.0 14 * [0x0 - 0xff] io PCI: 00:03.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:01.0 1c * [0x0 - 0xfff] io PCI: 00:03.0 1c * [0x1000 - 0x1fff] io PCI: 00:04.3 58 * [0x2000 - 0x20ff] io PCI: 00:04.6 10 * [0x2400 - 0x24ff] io PCI: 00:04.6 14 * [0x2800 - 0x287f] io PCI: 00:04.2 10 * [0x2880 - 0x289f] io PCI: 00:04.1 20 * [0x28a0 - 0x28af] io PCI: 00:18.0 compute_resources_io: base: 28b0 size: 3000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 00 * [0x0 - 0x2fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:05.0 30 * [0x0 - 0x7ffff] mem PCI: 01:03.0 10 * [0x80000 - 0x8ffff] mem PCI: 01:03.0 30 * [0x90000 - 0x9ffff] mem PCI: 01:04.0 10 * [0xa0000 - 0xaffff] mem PCI: 01:04.0 30 * [0xb0000 - 0xbffff] mem PCI: 01:05.0 24 * [0xc0000 - 0xc03ff] mem PCI: 00:01.0 compute_resources_mem: base: c0400 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:06.0 10 * [0x0 - 0xffffff] mem PCI: 03:06.0 30 * [0x1000000 - 0x101ffff] mem PCI: 03:00.0 10 * [0x1020000 - 0x1020fff] mem PCI: 03:00.1 10 * [0x1021000 - 0x1021fff] mem PCI: 03:06.0 18 * [0x1022000 - 0x1022fff] mem PCI: 00:03.0 compute_resources_mem: base: 1023000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:03.0 20 * [0x0 - 0x10fffff] mem PCI: 00:01.0 20 * [0x1100000 - 0x11fffff] mem PCI: 00:01.1 10 * [0x1200000 - 0x1200fff] mem PCI: 00:02.1 10 * [0x1201000 - 0x1201fff] mem PCI: 00:18.0 compute_resources_mem: base: 1202000 size: 1300000 align: 24 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:18.0 01 * [0x4000000 - 0x52fffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 5300000 size: 5300000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:03.0 constrain_resources: PCI: 01:04.0 constrain_resources: PCI: 01:05.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:03.0 constrain_resources: PCI: 03:00.0 constrain_resources: PCI: 03:00.1 constrain_resources: PCI: 03:06.0 constrain_resources: PCI: 00:04.0 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.6 constrain_resources: PCI: 00:04.1 constrain_resources: PCI: 00:04.2 constrain_resources: PCI: 00:04.3 constrain_resources: I2C: 01:70 constrain_resources: I2C: 00:2c constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: I2C: 01:54 constrain_resources: I2C: 01:55 constrain_resources: I2C: 01:56 constrain_resources: I2C: 01:57 constrain_resources: PCI: 00:04.6 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:19.0 constrain_resources: PCI: 00:19.1 constrain_resources: PCI: 00:19.2 constrain_resources: PCI: 00:19.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 00 * [0x1000 - 0x3fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12 limit:ffff Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:03.0 1c * [0x2000 - 0x2fff] io Assigned: PCI: 00:04.3 58 * [0x3000 - 0x30ff] io Assigned: PCI: 00:04.6 10 * [0x3400 - 0x34ff] io Assigned: PCI: 00:04.6 14 * [0x3800 - 0x387f] io Assigned: PCI: 00:04.2 10 * [0x3880 - 0x389f] io Assigned: PCI: 00:04.1 20 * [0x38a0 - 0x38af] io PCI: 00:18.0 allocate_resources_io: next_base: 38b0 size: 3000 align: 12 gran: 12 done PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 01:05.0 20 * [0x1000 - 0x100f] io Assigned: PCI: 01:05.0 10 * [0x1010 - 0x1017] io Assigned: PCI: 01:05.0 18 * [0x1018 - 0x101f] io Assigned: PCI: 01:05.0 14 * [0x1020 - 0x1023] io Assigned: PCI: 01:05.0 1c * [0x1024 - 0x1027] io PCI: 00:01.0 allocate_resources_io: next_base: 1028 size: 1000 align: 12 gran: 12 done PCI: 00:03.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 03:06.0 14 * [0x2000 - 0x20ff] io PCI: 00:03.0 allocate_resources_io: next_base: 2100 size: 1000 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:f8000000 size:5300000 align:26 gran:0 limit:febfffff Assigned: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem Assigned: PCI: 00:18.0 01 * [0xfc000000 - 0xfd2fffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fd300000 size: 5300000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:18.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:01.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:01.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:1300000 align:24 gran:20 limit:febfffff Assigned: PCI: 00:03.0 20 * [0xfc000000 - 0xfd0fffff] mem Assigned: PCI: 00:01.0 20 * [0xfd100000 - 0xfd1fffff] mem Assigned: PCI: 00:01.1 10 * [0xfd200000 - 0xfd200fff] mem Assigned: PCI: 00:02.1 10 * [0xfd201000 - 0xfd201fff] mem PCI: 00:18.0 allocate_resources_mem: next_base: fd202000 size: 1300000 align: 24 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:fd100000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 01:05.0 30 * [0xfd100000 - 0xfd17ffff] mem Assigned: PCI: 01:03.0 10 * [0xfd180000 - 0xfd18ffff] mem Assigned: PCI: 01:03.0 30 * [0xfd190000 - 0xfd19ffff] mem Assigned: PCI: 01:04.0 10 * [0xfd1a0000 - 0xfd1affff] mem Assigned: PCI: 01:04.0 30 * [0xfd1b0000 - 0xfd1bffff] mem Assigned: PCI: 01:05.0 24 * [0xfd1c0000 - 0xfd1c03ff] mem PCI: 00:01.0 allocate_resources_mem: next_base: fd1c0400 size: 100000 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_mem: base:fc000000 size:1100000 align:24 gran:20 limit:febfffff Assigned: PCI: 03:06.0 10 * [0xfc000000 - 0xfcffffff] mem Assigned: PCI: 03:06.0 30 * [0xfd000000 - 0xfd01ffff] mem Assigned: PCI: 03:00.0 10 * [0xfd020000 - 0xfd020fff] mem Assigned: PCI: 03:00.1 10 * [0xfd021000 - 0xfd021fff] mem Assigned: PCI: 03:06.0 18 * [0xfd022000 - 0xfd022fff] mem PCI: 00:03.0 allocate_resources_mem: next_base: fd023000 size: 1100000 align: 24 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=003e0000, basek=00000300, limitk=00200000 1: mmio_basek=003e0000, basek=003e0000, limitk=00400000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fd2fffff] size 0x01300000 gran 0x14 mem PCI: 00:18.0 1b0 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00fd100000 - 0x00fd1fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:03.0 10 <- [0x00fd180000 - 0x00fd18ffff] size 0x00010000 gran 0x10 mem64 PCI: 01:03.0 30 <- [0x00fd190000 - 0x00fd19ffff] size 0x00010000 gran 0x10 romem PCI: 01:04.0 10 <- [0x00fd1a0000 - 0x00fd1affff] size 0x00010000 gran 0x10 mem64 PCI: 01:04.0 30 <- [0x00fd1b0000 - 0x00fd1bffff] size 0x00010000 gran 0x10 romem PCI: 01:05.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io PCI: 01:05.0 14 <- [0x0000001020 - 0x0000001023] size 0x00000004 gran 0x02 io PCI: 01:05.0 18 <- [0x0000001018 - 0x000000101f] size 0x00000008 gran 0x03 io PCI: 01:05.0 1c <- [0x0000001024 - 0x0000001027] size 0x00000004 gran 0x02 io PCI: 01:05.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io PCI: 01:05.0 24 <- [0x00fd1c0000 - 0x00fd1c03ff] size 0x00000400 gran 0x0a mem PCI: 01:05.0 30 <- [0x00fd100000 - 0x00fd17ffff] size 0x00080000 gran 0x13 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:01.1 10 <- [0x00fd200000 - 0x00fd200fff] size 0x00001000 gran 0x0c mem64 PCI: 00:02.1 10 <- [0x00fd201000 - 0x00fd201fff] size 0x00001000 gran 0x0c mem64 PCI: 00:03.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:03.0 20 <- [0x00fc000000 - 0x00fd0fffff] size 0x01100000 gran 0x14 bus 03 mem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00fd020000 - 0x00fd020fff] size 0x00001000 gran 0x0c mem PCI: 03:00.1 10 <- [0x00fd021000 - 0x00fd021fff] size 0x00001000 gran 0x0c mem PCI: 03:06.0 10 <- [0x00fc000000 - 0x00fcffffff] size 0x01000000 gran 0x18 mem PCI: 03:06.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 03:06.0 18 <- [0x00fd022000 - 0x00fd022fff] size 0x00001000 gran 0x0c mem PCI: 03:06.0 30 <- [0x00fd000000 - 0x00fd01ffff] size 0x00020000 gran 0x11 romem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 00:04.0 assign_resources, bus 0 link: 0 PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.6 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io PNP: 002e.6 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io PNP: 002e.6 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PCI: 00:04.0 assign_resources, bus 0 link: 0 PCI: 00:04.1 20 <- [0x00000038a0 - 0x00000038af] size 0x00000010 gran 0x04 io PCI: 00:04.2 10 <- [0x0000003880 - 0x000000389f] size 0x00000020 gran 0x05 io PCI: 00:04.3 58 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io PCI: 00:04.3 assign_resources, bus 1 link: 0 PCI: 00:04.3 assign_resources, bus 1 link: 0 PCI: 00:04.6 10 <- [0x0000003400 - 0x00000034ff] size 0x00000100 gran 0x08 io PCI: 00:04.6 14 <- [0x0000003800 - 0x000000387f] size 0x00000080 gran 0x07 io PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL APIC: 01 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base f8000000 size 5300000 align 26 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 80000000 size 78000000 align 0 gran 0 limit 0 flags e0004200 index 31 PCI: 00:18.0 links 3 child on link 0 PCI: 00:01.0 PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff flags 60080100 index 1c0 PCI: 00:18.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 40081200 index 2 PCI: 00:18.0 resource base fc000000 size 1300000 align 24 gran 20 limit febfffff flags 60080200 index 1b8 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1b0 PCI: 00:01.0 links 1 child on link 0 PCI: 01:03.0 PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base fd100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:03.0 links 0 child on link 0 NULL PCI: 01:03.0 resource base fd180000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 10 PCI: 01:03.0 resource base fd190000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 01:04.0 links 0 child on link 0 NULL PCI: 01:04.0 resource base fd1a0000 size 10000 align 16 gran 16 limit febfffff flags 60000201 index 10 PCI: 01:04.0 resource base fd1b0000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 01:05.0 links 0 child on link 0 NULL PCI: 01:05.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 01:05.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 01:05.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 01:05.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 01:05.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 01:05.0 resource base fd1c0000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24 PCI: 01:05.0 resource base fd100000 size 80000 align 19 gran 19 limit febfffff flags 60002200 index 30 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base fd200000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 10 PCI: 00:02.0 links 1 child on link 0 NULL PCI: 00:02.1 links 0 child on link 0 NULL PCI: 00:02.1 resource base fd201000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 10 PCI: 00:03.0 links 1 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:03.0 resource base fc000000 size 1100000 align 24 gran 20 limit febfffff flags 60080202 index 20 PCI: 03:00.0 links 0 child on link 0 NULL PCI: 03:00.0 resource base fd020000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 03:00.1 links 0 child on link 0 NULL PCI: 03:00.1 resource base fd021000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 03:00.2 links 0 child on link 0 NULL PCI: 03:01.0 links 0 child on link 0 NULL PCI: 03:06.0 links 0 child on link 0 NULL PCI: 03:06.0 resource base fc000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10 PCI: 03:06.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 03:06.0 resource base fd022000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 18 PCI: 03:06.0 resource base fd000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30 PCI: 00:04.0 links 1 child on link 0 PNP: 002e.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 378 size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.4 links 0 child on link 0 NULL PNP: 002e.4 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.5 links 0 child on link 0 NULL PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base 60 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.6 resource base 64 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62 PNP: 002e.6 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.9 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a links 0 child on link 0 NULL PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 links 0 child on link 0 NULL PCI: 00:04.1 resource base 38a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:04.2 links 0 child on link 0 NULL PCI: 00:04.2 resource base 3880 size 20 align 5 gran 5 limit ffff flags 60000100 index 10 PCI: 00:04.3 links 1 child on link 0 I2C: 01:70 PCI: 00:04.3 resource base 3000 size 100 align 8 gran 8 limit ffff flags 60000100 index 58 I2C: 01:70 links 4 child on link 0 I2C: 00:2c I2C: 00:2c links 0 child on link 0 NULL I2C: 01:50 links 0 child on link 0 NULL I2C: 01:51 links 0 child on link 0 NULL I2C: 01:52 links 0 child on link 0 NULL I2C: 01:53 links 0 child on link 0 NULL I2C: 01:54 links 0 child on link 0 NULL I2C: 01:55 links 0 child on link 0 NULL I2C: 01:56 links 0 child on link 0 NULL I2C: 01:57 links 0 child on link 0 NULL PCI: 00:04.5 links 0 child on link 0 NULL PCI: 00:04.6 links 0 child on link 0 NULL PCI: 00:04.6 resource base 3400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:04.6 resource base 3800 size 80 align 7 gran 7 limit ffff flags 60000100 index 14 PCI: 00:18.1 links 0 child on link 0 NULL PCI: 00:18.2 links 0 child on link 0 NULL PCI: 00:18.3 links 0 child on link 0 NULL PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94 PCI: 00:19.0 links 3 child on link 0 NULL PCI: 00:19.1 links 0 child on link 0 NULL PCI: 00:19.2 links 0 child on link 0 NULL PCI: 00:19.3 links 0 child on link 0 NULL Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 07 PCI: 01:03.0 cmd <- 02 PCI: 01:04.0 cmd <- 02 PCI: 01:05.0 cmd <- 03 PCI: 00:01.1 subsystem <- 161f/3016 PCI: 00:01.1 cmd <- 06 PCI: 00:02.1 subsystem <- 161f/3016 PCI: 00:02.1 cmd <- 06 PCI: 00:03.0 bridge ctrl <- 000b PCI: 00:03.0 cmd <- 07 PCI: 03:00.0 subsystem <- 161f/3016 PCI: 03:00.0 cmd <- 02 PCI: 03:00.1 subsystem <- 161f/3016 PCI: 03:00.1 cmd <- 02 PCI: 03:06.0 subsystem <- 161f/3016 PCI: 03:06.0 cmd <- 83 PCI: 00:04.0 subsystem <- 161f/3016 PCI: 00:04.0 cmd <- 0f PCI: 00:04.1 subsystem <- 161f/3016 PCI: 00:04.1 cmd <- 01 PCI: 00:04.2 subsystem <- 161f/3016 PCI: 00:04.2 cmd <- 01 PCI: 00:04.3 subsystem <- 161f/3016 PCI: 00:04.3 cmd <- 01 PCI: 00:04.6 subsystem <- 161f/3016 PCI: 00:04.6 cmd <- 01 PCI: 00:18.1 subsystem <- 161f/3016 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 161f/3016 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 subsystem <- 161f/3016 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 subsystem <- 161f/3016 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000c000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device f51 CPU: family 0f, model 05, stepping 01 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 3072MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 3, base: 3584MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 4, base: 3840MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xff Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Opteron(tm) Processor 242 Setting up local apic... apic_id: 0x00 done. Clearing memory 2048K - 2097152K: ------------------------------- done CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device f51 CPU: family 0f, model 05, stepping 01 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 3072MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 3, base: 3584MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 4, base: 3840MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xff Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Opteron(tm) Processor 242 Setting up local apic... apic_id: 0x01 done. Clearing memory 2097152K - 4194304K: -------------------------------- done CPU #1 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:01.0 init PCI: 00:03.0 init PCI: 03:06.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom In cbfs, rom address for PCI: 03:06.0 = fff925b8 PCI Expansion ROM, signature 0xaa55, INIT size 0x9000, data ptr 0x017c PCI ROM Image, Vendor 1002, Device 4752, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from fff925b8 to 0xc0000, 0x9000 bytes Real mode stub @00000600: 422 bytes Calling Option ROM... oprom: INT# 0x1a oprom: eax: 0000b109 ebx: 00000330 ecx: 00000330 edx: 00000300 oprom: ebp: 0015ff30 esp: 00000fd6 edi: 0011002e esi: 00001900 oprom: ip: 02b6 cs: c000 flags: 00000046 0xb109: bus 3 devfn 0x30 reg 0x2e val 0x0 oprom: INT# 0x1a oprom: eax: 0000b10d ebx: 00000330 ecx: 80081002 edx: 00000300 oprom: ebp: 0015ff30 esp: 00000fd6 edi: 0011004c esi: 00001900 oprom: ip: 02c8 cs: c000 flags: 00000046 0xb10d: bus 3 devfn 0x30 reg 0x4c val 0x80081002 oprom: INT# 0x1a oprom: eax: 0000b109 ebx: 00000330 ecx: 80081002 edx: 00000300 oprom: ebp: 0015ff30 esp: 00000fd6 edi: 00110014 esi: 00001900 oprom: ip: 0322 cs: c000 flags: 00000046 0xb109: bus 3 devfn 0x30 reg 0x14 val 0x2001 oprom: INT# 0x1a oprom: eax: 0000b10a ebx: 00000330 ecx: 0000dfff edx: 00000300 oprom: ebp: 0015ff30 esp: 00000fd6 edi: 00110018 esi: 00001900 oprom: ip: 0347 cs: c000 flags: 00000006 0xb10a: bus 3 devfn 0x30 reg 0x18 val 0xfd022000 oprom: INT# 0x1a oprom: eax: 0000b108 ebx: 00000330 ecx: 00000084 edx: 0000b108 oprom: ebp: 00150fa4 esp: 00000f96 edi: 00110004 esi: 000001c9 oprom: ip: 84c9 cs: c000 flags: 00000046 0xb108: bus 3 devfn 0x30 reg 0x4 val 0x83 oprom: INT# 0x1a oprom: eax: 0000b10b ebx: 00000330 ecx: 00000087 edx: 0000b10b oprom: ebp: 00150fa4 esp: 00000f9a edi: 00110004 esi: 000001ca oprom: ip: 83fb cs: c000 flags: 00000046 0xb10b: bus 3 devfn 0x30 reg 0x4 val 0x87 oprom: INT# 0x1a oprom: eax: 0000b10a ebx: 00000000 ecx: 00005884 edx: 0000b10a oprom: ebp: 00150fa4 esp: 00000f96 edi: 00110003 esi: 00000273 oprom: ip: 84c9 cs: c000 flags: 00000016 0xb10a: BAD DEVICE bus 0 devfn 0x0 int1a call returned error. oprom: INT# 0x42 oprom: eax: 00000007 ebx: 00001004 ecx: 00000000 edx: 000003c2 oprom: ebp: 00150000 esp: 00000fdc edi: 0011efff esi: 00000000 oprom: ip: 4302 cs: c000 flags: 00000006 Unsupported software interrupt #0x42 int42 call returned error. ... Option ROM returned. PCI: 00:04.0 init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 00 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 RTC Init Invalid CMOS LB checksum enabling HPET @0xfed00000 PNP: 002e.3 init PNP: 002e.6 init Keyboard init... Keyboard controller output buffer result timeout PCI: 00:04.1 init IDE1 IDE0 PCI: 00:04.3 init set power on after power fail PCI: 00:18.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom CBFS: follow chain: fff92580 + 38 + 9000 + align -> fff9b5c0 Check CBFS: follow chain: fff9b5c0 + 28 + 549f8 + align -> ffff0000 CBFS: Could not find file pci1022,1101.rom PCI: 00:18.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom CBFS: follow chain: fff92580 + 38 + 9000 + align -> fff9b5c0 Check CBFS: follow chain: fff9b5c0 + 28 + 549f8 + align -> ffff0000 CBFS: Could not find file pci1022,1102.rom PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.0 init PCI: 00:19.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom CBFS: follow chain: fff92580 + 38 + 9000 + align -> fff9b5c0 Check CBFS: follow chain: fff9b5c0 + 28 + 549f8 + align -> ffff0000 CBFS: Could not find file pci1022,1101.rom PCI: 00:19.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom CBFS: follow chain: fff92580 + 38 + 9000 + align -> fff9b5c0 Check CBFS: follow chain: fff9b5c0 + 28 + 549f8 + align -> ffff0000 CBFS: Could not find file pci1022,1102.rom PCI: 00:19.3 init NB: Function 3 Misc Control.. done. PCI: 01:03.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom CBFS: follow chain: fff92580 + 38 + 9000 + align -> fff9b5c0 Check CBFS: follow chain: fff9b5c0 + 28 + 549f8 + align -> ffff0000 CBFS: Could not find file pci14e4,16a6.rom On card, rom address for PCI: 01:03.0 = fd190000 PCI Expansion ROM, signature 0xffff, INIT size 0x1fe00, data ptr 0xffff Incorrect Expansion ROM Header Signature ffff PCI: 01:04.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom CBFS: follow chain: fff92580 + 38 + 9000 + align -> fff9b5c0 Check CBFS: follow chain: fff9b5c0 + 28 + 549f8 + align -> ffff0000 CBFS: Could not find file pci14e4,16a6.rom On card, rom address for PCI: 01:04.0 = fd1b0000 PCI Expansion ROM, signature 0xffff, INIT size 0x1fe00, data ptr 0xffff Incorrect Expansion ROM Header Signature ffff PCI: 01:05.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload CBFS: follow chain: fff8adc0 + 38 + 7759 + align -> fff92580 Check pci1002,4752.rom CBFS: follow chain: fff92580 + 38 + 9000 + align -> fff9b5c0 Check CBFS: follow chain: fff9b5c0 + 28 + 549f8 + align -> ffff0000 CBFS: Could not find file pci1095,3114.rom On card, rom address for PCI: 01:05.0 = fd100000 PCI Expansion ROM, signature 0xffff, INIT size 0x1fe00, data ptr 0xffff Incorrect Expansion ROM Header Signature ffff Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 5 resources PCI: 00:18.0: enabled 1, 4 resources PCI: 00:01.0: enabled 1, 3 resources PCI: 00:01.1: enabled 1, 1 resources PCI: 00:02.0: enabled 0, 0 resources PCI: 00:02.1: enabled 1, 1 resources PCI: 00:03.0: enabled 1, 3 resources PCI: 03:00.0: enabled 1, 1 resources PCI: 03:00.1: enabled 1, 1 resources PCI: 03:00.2: enabled 0, 0 resources PCI: 03:01.0: enabled 0, 0 resources PCI: 03:06.0: enabled 1, 4 resources PCI: 00:04.0: enabled 1, 3 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 0, 4 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 2 resources PNP: 002e.5: enabled 0, 1 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 2 resources PNP: 002e.8: enabled 0, 2 resources PNP: 002e.9: enabled 0, 2 resources PNP: 002e.a: enabled 0, 2 resources PCI: 00:04.1: enabled 1, 1 resources PCI: 00:04.2: enabled 1, 1 resources PCI: 00:04.3: enabled 1, 1 resources I2C: 01:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 01:50: enabled 1, 0 resources I2C: 01:51: enabled 1, 0 resources I2C: 01:52: enabled 1, 0 resources I2C: 01:53: enabled 1, 0 resources I2C: 01:54: enabled 1, 0 resources I2C: 01:55: enabled 1, 0 resources I2C: 01:56: enabled 1, 0 resources I2C: 01:57: enabled 1, 0 resources PCI: 00:04.5: enabled 0, 0 resources PCI: 00:04.6: enabled 1, 2 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 1 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources APIC: 01: enabled 1, 0 resources PCI: 01:03.0: enabled 1, 2 resources PCI: 01:04.0: enabled 1, 2 resources PCI: 01:05.0: enabled 1, 7 resources Initializing CBMEM area to 0x7fff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 7fff0200...ok High Tables Base is 7fff0000. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x7fff0400... done. PIRQ table: 176 bytes. Looking for bad PCIX MHz input Looking for bad Hot Swap Enable OK 133MHz & Hot Swap is off Wrote the mp table end at: 000f0410 - 000f060c Adding CBMEM entry as no. 3 Looking for bad PCIX MHz input Looking for bad Hot Swap Enable OK 133MHz & Hot Swap is off Wrote the mp table end at: 7fff1410 - 7fff160c MP table: 524 bytes. Multiboot Information structure has been written. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 5bdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x7fff2400 rom_table_end = 0x7fff2400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x7fff2400 to 0x80000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000007ffeffff: RAM 3. 000000007fff0000-000000007fffffff: CONFIGURATION TABLES 4. 0000000080000000-00000000f7ffffff: RAM Wrote coreboot table at: 7fff2400 - 7fff2cd8 checksum 7e7a coreboot table: 2264 bytes. 0. FREE SPACE 7fff4400 0000bc00 1. GDT 7fff0200 00000200 2. IRQ TABLE 7fff0400 00001000 3. SMP TABLE 7fff1400 00001000 4. COREBOOT 7fff2400 00002000 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + ad86 + align -> fff8adc0 Check fallback/payload Got a payload Loading segment from rom address 0xfff8adf8 data (compression=1) malloc Enter, size 36, free_mem_ptr 00161110 malloc 00161110 New segment dstaddr 0x100000 memsize 0x36660 srcaddr 0xfff8ae4c filesize 0x76d7 (cleaned up) New segment addr 0x100000 size 0x36660 offset 0xfff8ae4c filesize 0x76d7 Loading segment from rom address 0xfff8ae14 data (compression=1) malloc Enter, size 36, free_mem_ptr 00161134 malloc 00161134 New segment dstaddr 0x136660 memsize 0x48 srcaddr 0xfff92523 filesize 0x2e (cleaned up) New segment addr 0x136660 size 0x48 offset 0xfff92523 filesize 0x2e Loading segment from rom address 0xfff8ae30 Entry Point 0x00100080 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036660 filesz: 0x00000000000076d7 lb: [0x0000000000100000, 0x0000000000164000) segment: [0x0000000000100000, 0x00000000001076d7, 0x0000000000136660) bounce: [0x00000000f7f38000, 0x00000000f7f3f6d7, 0x00000000f7f6e660) Post relocation: addr: 0x00000000f7f38000 memsz: 0x0000000000036660 filesz: 0x00000000000076d7 using LZMA [ 0x00000000f7f38000, 00000000f7f4534c, 0x00000000f7f6e660) <- 00000000fff8ae4c Clearing Segment: addr: 0x00000000f7f4534c memsz: 0x0000000000029314 dest f7f38000, end f7f6e660, bouncebuffer f7f38000 Loading Segment: addr: 0x0000000000136660 memsz: 0x0000000000000048 filesz: 0x000000000000002e lb: [0x0000000000100000, 0x0000000000164000) segment: [0x0000000000136660, 0x000000000013668e, 0x00000000001366a8) bounce: [0x00000000f7f6e660, 0x00000000f7f6e68e, 0x00000000f7f6e6a8) Post relocation: addr: 0x00000000f7f6e660 memsz: 0x0000000000000048 filesz: 0x000000000000002e using LZMA [ 0x00000000f7f6e660, 00000000f7f6e6a8, 0x00000000f7f6e6a8) <- 00000000fff92523 dest f7f6e660, end f7f6e6a8, bouncebuffer f7f38000 Loaded segments Jumping to boot code at 100080 entry = 0x00100080 lb_start = 0x00100000 lb_size = 0x00064000 adjust = 0xf7e9c000 buffer = 0xf7f38000 elf_boot_notes = 0x00114b74 adjusted_boot_notes = 0xf7fb0b74 FILO version 0.5.6 (jboonen@phenomII) Tue May 11 23:31:03 CEST 2010 Can't get memory map from firmware. Using hardcoded default. pci_init: Scanning PCI: found 24 devices pci_init: 00:01.0 1022:7450 0604 00 pci_init: 00:01.1 1022:7451 0800 10 pci_init: 00:02.0 1022:7450 0604 00 pci_init: 00:02.1 1022:7451 0800 10 pci_init: 00:03.0 1022:7460 0604 00 pci_init: 00:04.0 1022:7468 0601 00 pci_init: 00:04.1 1022:7469 0101 8a pci_init: 00:04.2 1022:746a 0c05 00 pci_init: 00:04.3 1022:746b 0680 00 pci_init: 00:04.6 1022:746e 0703 00 pci_init: 00:18.0 1022:1100 0600 00 pci_init: 00:18.1 1022:1101 0600 00 pci_init: 00:18.2 1022:1102 0600 00 pci_init: 00:18.3 1022:1103 0600 00 pci_init: 00:19.0 1022:1100 0600 00 pci_init: 00:19.1 1022:1101 0600 00 pci_init: 00:19.2 1022:1102 0600 00 pci_init: 00:19.3 1022:1103 0600 00 pci_init: 01:03.0 14e4:16a6 0200 00 pci_init: 01:04.0 14e4:16a6 0200 00 pci_init: 01:05.0 1095:3114 0180 00 pci_init: 03:00.0 1022:7464 0c03 10 pci_init: 03:00.1 1022:7464 0c03 10 pci_init: 03:06.0 1002:4752 0300 00 Press for default boot, or for boot prompt... 2 1 timed out boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 find_ide_controller: found PCI IDE controller 1095:3114 prog_if=0x0 find_ide_controller: primary channel: native PCI mode find_ide_controller: cmd_base=0x1010 ctrl_base=0x1020 init_controller: init_controller: drive 0 ide_software_reset: Waiting for ide0 to become ready for reset... ok ide_software_reset: Resetting ide0... IDE time out reset failed, but slave maybe exist ide_software_reset: ok init_drive: Testing for hda init_drive: Testing for hda init_controller: MASTER CHECK: master no init_controller: /*slave */ -- drive is 0 init_controller: NO MASTER -- check slave! init_drive: Testing for hda init_drive: Testing for hda init_controller: SLAVE ONLY CHECK: slave no Drive 0 does not exist devopen: failed to open ide boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 Drive 0 does not exist devopen: failed to open ide boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200^                                                            5:/vmlinux z Drive 0 does not exist devopen: failed to open ide boot: hda5:/vmlinuz          5 6  e1/ :/vmlinuz find_ide_controller: PCI IDE #1 not found IDE channel 2 not found devopen: failed to open ide boot: hde1:/vmlinuz           c:/vmlinu\ z find_ide_controller: found PCI IDE controller 1095:3114 prog_if=0x0 find_ide_controller: secondary channel: native PCI mode find_ide_controller: cmd_base=0x1018 ctrl_base=0x1024 init_controller: init_controller: drive 2 ide_software_reset: Waiting for ide1 to become ready for reset... ok ide_software_reset: Resetting ide1... IDE time out reset failed, but slave maybe exist ide_software_reset: ok init_drive: Testing for hdc init_drive: Testing for hdc init_controller: MASTER CHECK: master no init_controller: /*slave */ -- drive is 2 init_controller: NO MASTER -- check slave! init_drive: Testing for hdc init_drive: Testing for hdc init_controller: SLAVE ONLY CHECK: slave no Drive 2 does not exist devopen: failed to open ide boot: hdc:/vmlinuz         1/vmlinuz Can't parse device name devopen: failed to parse device name: hdc1/vmlinuz boot: hdc1/vmlinuz        :/vmlinuz Drive 2 does not exist devopen: failed to open ide boot: hdc1:/vmlinuz           d1:/vmlinuz Drive 3 does not exist devopen: failed to open ide boot: hdd1:/vmlinuz           b1:/vmlinuz Drive 1 does not exist devopen: failed to open ide boot: hdb1:/vmlinuz           a1:/vmlinuz Drive 0 does not exist devopen: failed to open ide boot: hda1:/vmlinuz