

coreboot-4.0-r5692M Mon Aug 
coherent_ht_finalize
done
corde|link=00
devices_por_init()
sb700_device: LPC Device, BDF:0-20-3
sb700__max: 0xc
Requested fid_new: 0xred freq_cap=0x8075
pos=0x8a, fx0, freq=0x6, needs_reset=0x1
wdth=0x11
dev2 input|output widt0_htinit: HT1 mode
needs_reset=23 00:28:10 CEST 2010 starting..
coherent_ht_finalize
done
corde|link=00
nit
sb700_early_setup()
sb700_devices_por_init()
sb700_device0-20-1
sb700_devices_por_init()c0c0c
end msr fid, vid: hi=0x12xd2, unfiltered freq_cap=0x1e750
width_cap1=0x11, width_cap2=0width=0x11
old dev2 input|outpuset=0x0
sysinfo->nodes:  1  sys166Mhz
 0x00300000 (default)
Ram4
v_eDone
Loading stage image.
Chec image.
POST: 0x80
POST: 0x39OST: 0x40
Enumerating buses...
APIC: 00: enabled 1
PCI_DOMAIN
PCI: 00:06.0: enabled 0
PCI: 1
PCI: 00:13.0: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.e.9: enabled 1
PNP: 002e.109: e18.1: enabled 1
PCI: 00:18.2: e PCI: 00:00.0: enabled 1
   PCI PCI: 00:08.0: enabled 0
   PCI PCI: 00:13.1: enabled 1
   PCI: 00:14.2: enabled 1
   PCI: 00PNP: 002e.8: enabled 1
    PNP:
   PCI: 00:14.4: enabled 1
  0000, msr.hi = 0x00000000
mb_enenabled
APIC_CLUSTER: 0 scanninr bus 00
POST: 0x24
PCI: 00:18ST: 0x25
PCI: Using configuratiPCI_REG4C = 52042.
PCI: 00:00.0
POST: 0x24
rs780_enable: dev=0.0 [1022/9601] enabled
rs780_ety: type 0x08 @ 0x44
Capability1
rs780_gfx_init, nb_dev=0x0011le_port_configuration.
PcieLinkTraining port=2:lc curre
rs780_enable: dev=0011d094, VIev-4,5,6,7, Fun-0. enable=0
rs70, VID_DID=0x960a1022
Bus-0, DePcieLinkTraining port=9:lc curre 0xb8
Capability: type 0x01 @ 0ity: type 0x05 @ 0xa0
Capabilit_enable: dev=0011d490, VID_DID=0nt state=a0b0f10
addr=e0000000,b0
Capability: type 0x08 @ 0xb8: type 0x10 @ 0x58
Capability:  [1022/9609] enabled
sb700_enabps
PCI: 00:12.1 [1002/4398] ena.1 [1002/4398] ops
PCI: 00:13.1enable()
PCI: 00:14.1 [1002/43939d] enabled
sb700_enable()
PCem_ptr 00190044
malloc 001900440011cc10.
sysmem = 0_20000000
, free_mem_ptr 001900a0
malloc loc Enter, size 24, free_mem_ptr0d0
PCI: 03:00.0 [10ec/8168] enabled
POST: 0x25
PCI: pci_scan:14.0
smbus: PCI: 00:14.0[0]->Ian_static_bus for PCI: 00:14.3
APIC_CLUSTER: 0 init
start_eip=(0-88) type: UC
Setting fixed Metting variable MTRR 1, base:  5K_HIGH=0xff
DONE variable MTRRs
Clear out the extra MTRR's
ca id = 0x00000000
microcode: revrocode: patch id to apply = 0x00
CPU #0 initialized
Asserting s: 2.
Sending STARTUP #1 to 1.g CPU #1
Waiting for 1 CPUS to etting fixed MTRRs(24-88) Type: S_MASK_HIGH=0xff
Setting variabcheck
Fixed MTRRs   : Enabled
rocode_updates[] 
microcode: remodel AMD Athlon(tm) 64 X2 Dual CI: 00:18.2 init
PCI: 00:18.3 istatus = 23
0x6=a0, 0x7=80
dri0x6=a0, 0x7=80
drive detection 0x6=a0, 0x7=80
[snip]
not yet completed, waiting...
s ready after 2 tries
SATA port
PCI: 00:13.1 init
PCI: 00:13.00001 value 0x00000000 0x0001000000000 0x00010000
IOAPIC: reg 00
IOAPIC: reg 0x0000000a value x0000000e value 0x00000000 0x0000x00000000 0x00010000
IOAPIC: r10000
set power on after power 
PCI: 00:14.4 init
PCI: 00:14.e.2 init
PNP: 002e.3 init
PNP: 002e.8 init
PNP: 002e.9 init
 00:18.0: enabled 1
PCI: 00:00..0: enabled 1
PCI: 00:0a.0: ena4.0: enabled 1
I2C: 01:50: enabled 0
PNP: 002e.2: enabled 1
Pled 0
PNP: 002e.a: enabled 0
P
PCI: 01:05.0: enabled 1
PCI: 000.
POST: 0x9a
Writing IRQ rou9b
Wrote the mp table end at: 0 added table 1/32 Length now 40ported
ACPI: added table 3/32 Lbytes.
POST: 0x9d
Multiboot Inlow_table_end: 0x00000518
Now ggh table area
uma_memory_start=00000017feffff: RAM
 3. 0000000: 0x9e
 0. FREE SPACE 18000000 4243
Found CBFS header at fffefression=1)
malloc Enter, size 3770 filesize 0xc3cd
Loading seg0194000)
Post relocation: addr:00) <- fff0e770
dest 000e7270, fer   = 0x17ec8000
     elf_booreboot table forwarder.
Now att2
Add to e820 map: 00000000 0000000000 high)
malloc setup
AddFound 2 cpu(s) max supported 2 c=0x17fdfee0)
Copying PIR from 0e=20 align=10 ret=0x000fdb50 (delloc zone=0x000f5304 handle=ffffx17fdfe50)
Scan for VGA option 8@0xfff1ab78 to 160368@0x000c0005 size 119)
Running option rom 
