

coreboot-4.0-r5692M Mon Aug 
coherent_ht_finalize
done
corde|link=00
devices_por_init()
sb700_device: LPC Device, BDF:0-20-3
sb700_c0c0c
Current fid_cur: 0xc, fidoptimize_link
pos=0x8a, unfilteneeds_reset=0x1
dev2 old_freq=0dth=0x11
dev2 input|output widts780_htinit cpu_ht_freq=6.
rs7823 00:28:10 CEST 2010 starting..e0 started: 
* AP 01started
SBLink=00
NC node|link=00
devices_por_init()
sb700_devicedevices_por_init(): P2P Bridge, c0c0c
end msr fid, vid: hi=0x12xd2, unfiltered freq_cap=0x1e750
width_cap1=0x11, width_cap2=0width=0x11
old dev2 input|outpuset=0x0
sysinfo->nodes:  1  sys166Mhz
 0x00300000 (default)
Ram4
v_eDone
Loading stage image.
Chec image.
POST: 0x80
POST: 0x39
APIC: 00: enabled 1
PCI_DOMAIN
PCI: 00:06.0: enabled 0
PCI: 1
PCI: 00:13.0: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.e.9: enabled 1
PNP: 002e.109: e18.1: enabled 1
PCI: 00:18.2: e PCI: 00:00.0: enabled 1
   PCI PCI: 00:08.0: enabled 0
   PCI PCI: 00:13.1: enabled 1
   PCI: 00:14.2: enabled 1
   PCI: 00PNP: 002e.8: enabled 1
    PNP:
   PCI: 00:14.4: enabled 1
  0000, msr.hi = 0x00000000
mb_enenabled
APIC_CLUSTER: 0 scanninr bus 00
POST: 0x24
PCI: 00:18ST: 0x25
PCI: Using configuratiPCI_REG4C = 52042.
PCI: 00:00.0
POST: 0x24
rs780_enable: dev=0.0 [1022/9601] enabled
rs780_ety: type 0x08 @ 0x44
Capability1
rs780_gfx_init, nb_dev=0x0011le_port_configuration.
PcieLinkTraining port=2:lc curre
rs780_enable: dev=0011d094, VIev-4,5,6,7, Fun-0. enable=0
rs70, VID_DID=0x960a1022
Bus-0, DePcieLinkTraining port=9:lc curre 0xb8
Capability: type 0x01 @ 0ity: type 0x05 @ 0xa0
Capabilit_enable: dev=0011d490, VID_DID=0nt state=a0b0f10
addr=e0000000,b0
Capability: type 0x08 @ 0xb8: type 0x10 @ 0x58
Capability:  [1022/9609] enabled
sb700_enabps
PCI: 00:12.1 [1002/4398] ena.1 [1002/4398] ops
PCI: 00:13.1enable()
PCI: 00:14.1 [1002/43939d] enabled
sb700_enable()
PC0
malloc Enter, size 24, free_mle dev = 0x0019005c, nb_dev = 0x: 00:09.0
malloc Enter, size 24can_bridge for PCI: 00:0a.0
malloc Enter, size 24, free_mem_ptr 001900b8
malloc 001900b8
PCI:abled
POST: 0x25
PCI: pci_scan:14.0
smbus: PCI: 00:14.0[0]->Ian_static_bus for PCI: 00:14.3
APIC_CLUSTER: 0 init
start_eip=(0-88) type: UC
Setting fixed Metting variable MTRR 1, base:  5ll enable_var_mtrr()
Leave x86_ id (4a) does not match this pat00004d
microcode: updated to paINIT.
Waiting for send to finis
After apic_write.
Startup poinstop
CPU: vendor AMD device 20fWB, RdMEM, WrMEM
DONE fixed MTR 128MB, type UC
ADDRESS_MASK_HI 0x93
microcode: equivalent revix microcode_updates[] 
microcoe.
POST: 0x9b
CPU #1 initializsata_bar1=3040
sata_bar2=3028
not yet completed, waiting...
not yet completed, waiting...
0x6=a0, 0x7=80
drive detection 0x6=a0, 0x7=80
[snip]
drive detection 0x6=0, 0x7=50
drive no longer s device is ready after 1 tries
PIC: Clearing IOAPIC at 0xfec000eg 0x00000003 value 0x00000000 0lue 0x00000000 0x00010000
IOAPIx00010000
IOAPIC: reg 0x0000000C: reg 0x00000010 value 0x000000x00010000
IOAPIC: reg 0x0000001
RTC Init
sm_init() end
PCI: 0nal_gfx_pci_dev_init device=9710No PS/2 keyboard detected.
PNP:CI_DOMAIN: 0000: enabled 1
PCI: 0
PCI: 00:07.0: enabled 0
PCId 1
PCI: 00:13.1: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e2e.109: enabled 1
PNP: 002e.2090:18.2: enabled 1
PCI: 00:18.3:s no. 1
Moving GDT to 17ff0200..write_pirq_routing_table done.c
Adding CBMEM entry as no. 4
lon(tm) 64 X2 Dual Core Processo * FADT
pm_base: 0x0800
ACPI: le forward entry at 0x00000500
d from 0x00000518 to 0x00001000  0000000000001000-000000000009ffe000 - 17ffe19c  checksum e6a1
7ff2400 0000bc00
 5. COREBOOT  Check fallback/payload
Got a pa 0xfff0e770 filesize 0xc3cd
  (filesz: 0x000000000000c3cd
lb: 00) <- fff0e770
dest 000e7270, fer   = 0x17ec8000
     elf_booreboot table forwarder.
Now att2
Add to e820 map: 00000000 0000000000 high)
malloc setup
Addpu(s)
init bios32
init PMM
inloc zone=0x000f5304 handle=ffffftail=0x17fdfe80)
Copying ACPI Rdb30 (detail=0x17fd7e20)
pmm_ma01:05.0 (vd 1002:9710)
Searchin5 size 119)
Running option rom 
