

coreboot-4.0-r5692M Mon Aug 
coherent_ht_finalize
done
corde|link=00
s_por_init(): SMBus Device, BDF:devices_por_init(): P2P Bridge, 06, lo=0x60c0c0c
entering optim=0xd2, filtered freq_cap=0x1e75idth_cap1=0x11, width_cap2=0x11h=0x11
old dev2 input|output wi0x1
ht reset -


coreboot-4.0-r5692M Mon Aug 
coherent_ht_finalize
done
corde|link=00
nit
sb700_early_setup()
sb700_devices_por_init()
sb700_device: LPC Device, BDF:0-20-3
sb700_060806, lo=0x60c0c0c
entering o
pos=0xd2, filtered freq_cap=0x1n_width2=0x4
dev1 input width=0link for link pair 0, reset_needffff6ee8
Ram1.00
setting up CPInterleaved
RAM end at 0x000800opying data from cache to RAM --ader at fffeffe0
magic is 4f524Stage: done loading.
Jumping to
APIC: 00: enabled 1
PCI_DOMAIN
PCI: 00:06.0: enabled 0
PCI: 1
PCI: 00:13.0: enabled 1
PCI:3: enabled 1
PNP: 002e.0: enablnabled 1
PNP: 002e.209: enablednabled 1
PCI: 00:18.3: enabled : 00:01.0: enabled 1
   PCI: 00: 00:09.0: enabled 1
   PCI: 00: 00:13.2: enabled 1
   PCI: 00:14.3: enabled 1
    PNP: 002e. 002e.9: enabled 1
    PNP: 002 PCI: 00:14.5: enabled 1
  PCI:able, TOP MEM2: msr2.lo = 0x0000g...
  PCI: 00:18.3 siblings=1.0 [1022/1100] bus ops
PCI: 00:on type 1
rs780_enable: dev=001 [1022/9601] enabled
Capability0011cc10, VID_DID=0x96011022
Bunable: dev=0011cda8, VID_DID=0x9: type 0x0d @ 0xb0
Capability: cc10, dev=0x0011cf40, port=0x2.le_port_configuration.
PcieLinkTraining port=2:lc curre
rs780_enable: dev=0011d094, VIev-4,5,6,7, Fun-0. enable=0
rs70, VID_DID=0x960a1022
Bus-0, DePcieLinkTraining port=9:lc curre0x10 @ 0x58
Capability: type 0x 0xb8
Capability: type 0x01 @ 0ity: type 0x05 @ 0xa0
Capabilit_enable: dev=0011d490, VID_DID=0nt state=a0b0f10
addr=e0000000,b0
Capability: type 0x08 @ 0xb8: type 0x10 @ 0x58
Capability:  [1022/9609] enabled
sb700_enabps
PCI: 00:12.1 [1002/4398] ena.1 [1002/4398] ops
PCI: 00:13.1enable()
PCI: 00:14.1 [1002/43939d] enabled
sb700_enable()
PC0
malloc Enter, size 24, free_mle dev = 0x0019005c, nb_dev = 0x: 00:09.0
malloc Enter, size 24can_bridge for PCI: 00:0a.0
malabled
POST: 0x25
PCI: pci_scan:14.0
smbus: PCI: 00:14.0[0]->Ian_static_bus for PCI: 00:14.3
APIC_CLUSTER: 0 init
start_eip=(0-88) type: UC
Setting fixed Metting variable MTRR 1, base:  5ll enable_var_mtrr()
Leave x86_ rev id  = 0x0210, current patch id = 0x00000000
microcode: revd! Fix microcode_updates[] 
mic done.
POST: 0x9b
ECC Disabledend to finish...
+#startup loop..
+After Startup.
Initializin(0-16) Type: WB, RdMEM, WrMEM
S, range:  128MB, type WB
ADDRESp_var_mtrrs
POST: 0x6a

MTRR 
microcode: Not updated! Fix micid = 0x0000004d  success

CPU CI: 00:18.2 init
PCI: 00:18.3 istatus = 23
0x6=a0, 0x7=80
dri0x6=a0, 0x7=80
drive detection 0x6=a0, 0x7=80
[snip]
drive detection not yet completed, waiting...
not yet completed, waiting...
not yet completed, waiting...
s ready after 2 tries
SATA port
PCI: 00:13.1 init
PCI: 00:13.00001 value 0x00000000 0x0001000000000 0x00010000
IOAPIC: reg 00
IOAPIC: reg 0x0000000a value x0000000e value 0x00000000 0x0000x00000000 0x00010000
IOAPIC: r10000
set power on after power 
PCI: 00:14.4 init
PCI: 00:14.e.2 init
PNP: 002e.3 init
PNP: 002e.8 init
PNP: 002e.9 init
 00:18.0: enabled 1
PCI: 00:00.: 00:08.0: enabled 0
PCI: 00:09I: 00:13.2: enabled 1
PCI: 00:1.0: enabled 0
PNP: 002e.1: enab: enabled 1
PNP: 002e.309: enab enabled 1
APIC: 01: enabled 1..ok
High Tables Base is 17ff00
PIRQ table: 48 bytes.
POST: 0xACPI: Writing ACPI tables at 17fr 3800+
Pstates Algorithm ...
added table 4/32 Length now 52
Wrote coreboot table at: 0000050
Adjust rom_table_end from 0x17 0000000000001000-000000000009ffe000 - 17ffe19c  checksum 38d3
7ff2400 0000bc00
 5. COREBOOT  Check fallback/payload
Got a pa 0xfff0e770 filesize 0xc3cd
  (e7270 memsz: 0x0000000000018d90 00) <- fff0e770
dest 000e7270, fer   = 0x17ec8000
     elf_booreboot table forwarder.
Now att2
Add to e820 map: 00000000 0000000000 high)
malloc setup
AddFound 2 cpu(s) max supported 2 c align=10 ret=0x000fdcc0 (detail10 to 0x000fdb70
pmm_malloc zon7e50 (detail=0x17fdfe50)
pmm_ma0
pmm_free 0x17fd7e50 (detail=01002,9710.rom
Copying data 60925 size 119)
Running option rom 
