Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,
CS5536, ITE IT8712F).  Board support is based on the SpaceRunner-LX
(with tiny bits from the RoadRunner-LX) even though the hardware really
was the ancestor of our three other -LX boards and in fact among the
earliest Geode-LX boards on the market.  (Might even have been the first
Geode-LX EPIC?)

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
---

--- src/mainboard/lippert/Kconfig	(rev 5796)
+++ src/mainboard/lippert/Kconfig	(working copy)
@@ -5,6 +5,8 @@
 
 config BOARD_LIPPERT_FRONTRUNNER
 	bool "Cool Frontrunner"
+config BOARD_LIPPERT_HURRICANE_LX
+	bool "Hurricane-LX"
 config BOARD_LIPPERT_LITERUNNER_LX
 	bool "Cool LiteRunner-LX"
 config BOARD_LIPPERT_ROADRUNNER_LX
@@ -15,6 +17,7 @@
 endchoice
 
 source "src/mainboard/lippert/frontrunner/Kconfig"
+source "src/mainboard/lippert/hurricane-lx/Kconfig"
 source "src/mainboard/lippert/literunner-lx/Kconfig"
 source "src/mainboard/lippert/roadrunner-lx/Kconfig"
 source "src/mainboard/lippert/spacerunner-lx/Kconfig"
--- src/mainboard/lippert/hurricane-lx/Kconfig	(rev 5796)
+++ src/mainboard/lippert/hurricane-lx/Kconfig	(working copy)
@@ -1,4 +1,4 @@
-if BOARD_LIPPERT_SPACERUNNER_LX
+if BOARD_LIPPERT_HURRICANE_LX
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -7,7 +7,6 @@
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F
-	select HAVE_DEBUG_SMBUS
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
@@ -18,15 +17,23 @@
 
 config MAINBOARD_DIR
 	string
-	default lippert/spacerunner-lx
+	default lippert/hurricane-lx
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "Cool SpaceRunner-LX"
+	default "Hurricane-LX"
 
 config IRQ_SLOT_COUNT
 	int
-	default 7
+	default 8
+
+config BOARD_OLD_REVISION
+	bool "Board is old pre-3.0 revision"
+	default n
+	help
+	  Look on the bottom side for a number like 406-0001-30.  The last 2
+	  digits state the PCB revision (3.0 in this example).  For 2.0 or older
+	  boards choose Y, for 3.0 and newer say N.
 
 config ONBOARD_UARTS_RS485
 	bool "Switch on-board serial ports to RS485"
@@ -35,10 +42,4 @@
 	  If selected, both on-board serial ports will operate in RS485 mode
 	  instead of RS232.
 
-config ONBOARD_IDE_SLAVE
-	bool "Make on-board SSD act as Slave"
-	default n
-	help
-	  If selected, the on-board SSD will act as IDE Slave instead of Master.
-
-endif # BOARD_LIPPERT_SPACERUNNER_LX
+endif # BOARD_LIPPERT_HURRICANE_LX
--- src/mainboard/lippert/hurricane-lx/chip.h	(rev 5796)
+++ src/mainboard/lippert/hurricane-lx/chip.h	(working copy)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
+ * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
--- src/mainboard/lippert/hurricane-lx/devicetree.cb	(rev 5796)
+++ src/mainboard/lippert/hurricane-lx/devicetree.cb	(working copy)
@@ -21,17 +21,17 @@
       register "com2_enable"              = "0"
       register "com2_address"             = "0x2E8"
       register "com2_irq"                 = "6"
-      register "unwanted_vpci[0]"         = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8
-      register "unwanted_vpci[1]"         = "0" # End of list has a zero
+      register "unwanted_vpci[0]"         = "0" # End of list has a zero
       device pci 8.0 on end		# Slot4
       device pci 9.0 on end		# Slot3
       device pci a.0 on end		# Slot2
       device pci b.0 on end		# Slot1
       device pci c.0 on end		# IT8888
+      device pci d.0 on end		# Mini-PCI
       device pci e.0 on end		# Ethernet
       device pci f.0 on			# ISA Bridge
         chip superio/ite/it8712f
-          device pnp 2e.0 off		# Floppy
+          device pnp 2e.0 on		# Floppy
             io 0x60 = 0x3f0
             irq 0x70 = 6
             drq 0x74 = 2
@@ -76,7 +76,7 @@
         end
       end
       device pci f.2 on end		# IDE
-      device pci f.3 off end		# Audio
+      device pci f.3 on end		# Audio
       device pci f.4 on end		# OHCI
       device pci f.5 on end		# EHCI
     end
--- src/mainboard/lippert/hurricane-lx/irq_tables.c	(rev 5796)
+++ src/mainboard/lippert/hurricane-lx/irq_tables.c	(working copy)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
+ * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* Based on irq_tables.c from AMD's DB800 mainboard. */
+/* Based on irq_tables.c from the SpaceRunner-LX mainboard. */
 
 #include <arch/pirq_routing.h>
 #include <console/console.h>
@@ -55,17 +55,18 @@
 	0x002B,			/* Device */
 	0,			/* Crap (miniport) */
 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
-	0xE0,			/* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	0x36,			/* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
 		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* CPU */
 		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
-		{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* ethernet */
+		{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* ethernet */
 		{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},	/* slot1 */
 		{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0},	/* slot2 */
 		{0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0},	/* slot3 */
 		{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0},	/* slot4 */
+		{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00}},       0x5, 0x0},	/* Mini-PCI */
 	}
 };
 
--- src/mainboard/lippert/hurricane-lx/mainboard.c	(rev 5796)
+++ src/mainboard/lippert/hurricane-lx/mainboard.c	(working copy)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
+ * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* Based on mainboard.c from AMD's DB800 mainboard. */
+/* Based on mainboard.c from the SpaceRunner-LX mainboard. */
 
 #include <stdlib.h>
 #include <stdint.h>
@@ -29,16 +29,15 @@
 #include <device/pci_ids.h>
 #include "chip.h"
 
-/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
+/* Bit1 switches Com1 to RS485, bit2 same for Com2. */
 #if CONFIG_ONBOARD_UARTS_RS485
-	#define SIO_GP1X_CONFIG 0x07
+	#define SIO_GP1X_CONFIG 0x06
 #else
-	#define SIO_GP1X_CONFIG 0x01
+	#define SIO_GP1X_CONFIG 0x00
 #endif
 
 static const u16 ec_init_table[] = { /* hi=data, lo=index */
 	0x1900,		/* Enable monitoring */
-	0x3050,		/* VIN4,5 enabled */
 	0x0351,		/* TMPIN1,2 diode mode, TMPIN3 off */
 	0x805C,		/* Unlock zero adjust */
 	0x7056, 0x3C57,	/* Zero adjust TMPIN1,2 */
@@ -49,20 +48,22 @@
 static void init(struct device *dev)
 {
 	unsigned int gpio_base, i;
-	printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "LiPPERT Hurricane-LX ENTER %s\n", __func__);
 
 	/* Init CS5536 GPIOs */
 	gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
 		    PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
 
 	outl(0x00000040, gpio_base + 0x00); // GPIO6  value      1 - LAN_PD#
+	outl(0x00000040, gpio_base + 0x08); // GPIO6  open drain 1 - LAN_PD# (jumpered GPIO per default)
 	outl(0x00000040, gpio_base + 0x04); // GPIO6  output     1 - LAN_PD#
-	outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up    0 - THRM_ALRM#
 	outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1    1 - THRM_ALRM#
 	outl(0x00000400, gpio_base + 0x20); // GPIO10 input      1 - THRM_ALRM#
+#if !CONFIG_BOARD_OLD_REVISION
 	outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2   1 - 32kHz
 	outl(0x00000800, gpio_base + 0x84); // GPIO27 output     1 - 32kHz
-	outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up    0 - 32kHz
+#endif
+	outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up    0 - 32kHz (new) / PM-LED (old)
 
 	/* Init Environment Controller. */
 	for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
@@ -71,10 +72,10 @@
 		outb(val >> 8, 0x0296);
 	}
 
-	/* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
+	/* bit2 = RS485_EN2, bit1 = RS485_EN1 */
 	outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
 
-	printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__);
+	printk(BIOS_DEBUG, "LiPPERT Hurricane-LX EXIT %s\n", __func__);
 }
 
 static void enable_dev(struct device *dev)
@@ -83,6 +84,6 @@
 }
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("LiPPERT SpaceRunner-LX Mainboard")
+	CHIP_NAME("LiPPERT Hurricane-LX Mainboard")
 	.enable_dev = enable_dev,
 };
--- src/mainboard/lippert/hurricane-lx/romstage.c	(rev 5796)
+++ src/mainboard/lippert/hurricane-lx/romstage.c	(working copy)
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
+ * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,11 +19,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */
+/* Based on romstage.c from the SpaceRunner-LX mainboard. */
 
 #include <stdlib.h>
 #include <stdint.h>
-#include <spd.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
@@ -40,66 +39,24 @@
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
-#if CONFIG_ONBOARD_IDE_SLAVE
-	#define SMC_CONFIG	0x03
-#else
-	#define SMC_CONFIG	0x01
-#endif
+/* Bit0 enables Spread Spectrum. */
+#define SMC_CONFIG	0x01
 
 #define ManualConf 1		/* No automatic strapped PLL config */
-#define PLLMSRhi 0x0000059C	/* Manual settings for the PLL */
+#define PLLMSRhi 0x0000049C	/* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
 #define DIMM0 0xA0
 #define DIMM1 0xA2
 
-static const unsigned char spdbytes[] = {	// 4x Promos V58C2512164SA-J5I
-	0xFF, 0xFF,				// only values used by Geode-LX raminit.c are set
-	[SPD_MEMORY_TYPE]		= SPD_MEMORY_TYPE_SDRAM_DDR,	// (Fundamental) memory type
-	[SPD_NUM_ROWS]			= 0x0D,	// Number of row address bits [13]
-	[SPD_NUM_COLUMNS]		= 0x0A,	// Number of column address bits [10]
-	[SPD_NUM_DIMM_BANKS]		= 1,	// Number of module rows (banks)
-	0xFF, 0xFF, 0xFF,
-	[SPD_MIN_CYCLE_TIME_AT_CAS_MAX]	= 0x50,	// SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [5.0 ns in BCD]
-	0xFF, 0xFF,
-	[SPD_REFRESH]			= 0x82,	// Refresh rate/type [Self Refresh, 7.8 us]
-	[SPD_PRIMARY_SDRAM_WIDTH]	= 64,	// SDRAM width (primary SDRAM) [64 bits]
-	0xFF, 0xFF, 0xFF,
-	[SPD_NUM_BANKS_PER_SDRAM]	= 4,	// SDRAM device attributes, number of banks on SDRAM device
-	[SPD_ACCEPTABLE_CAS_LATENCIES]	= 0x1C,	// SDRAM device attributes, CAS latency [3, 2.5, 2]
-	0xFF, 0xFF,
-	[SPD_MODULE_ATTRIBUTES]		= 0x20,	// SDRAM module attributes [differential clk]
-	[SPD_DEVICE_ATTRIBUTES_GENERAL]	= 0x40,	// SDRAM device attributes, general [Concurrent AP]
-	[SPD_SDRAM_CYCLE_TIME_2ND]	= 0x60,	// SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD]
-	0xFF,
-	[SPD_SDRAM_CYCLE_TIME_3RD]	= 0x75,	// SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD]
-	0xFF,
-	[SPD_tRP]			= 60,	// Min. row precharge time [15 ns in units of 0.25 ns]
-	[SPD_tRRD]			= 40,	// Min. row active to row active [10 ns in units of 0.25 ns]
-	[SPD_tRCD]			= 60,	// Min. RAS to CAS delay [15 ns in units of 0.25 ns]
-	[SPD_tRAS]			= 40,	// Min. RAS pulse width = active to precharge delay [40 ns]
-	[SPD_BANK_DENSITY]		= 0x40,	// Density of each row on module [256 MB]
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	[SPD_tRFC]			= 70	// SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [70 ns]
-};
-
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
 	if (device != DIMM0)
 		return 0xFF;	/* No DIMM1, don't even try. */
 
-#if CONFIG_DEBUG_SMBUS
-	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
-		print_err("ERROR: spd_read_byte(DIMM0, 0x");
-		print_err_hex8(address);
-		print_err(") returns 0xff\n");
-	}
-#endif
-
-	/* Fake SPD ROM value */
-	return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
+	return smbus_read_byte(device, address);
 }
 
+#if !CONFIG_BOARD_OLD_REVISION
 /* Send config data to System Management Controller via SMB. */
 static int smc_send_config(unsigned char config_data)
 {
@@ -118,6 +75,7 @@
 	smbus_stop_condition(SMBUS_IO_BASE);
 	return 0;
 }
+#endif
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
@@ -129,19 +87,21 @@
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
-	0x072C,		// VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
+	0x042C,		// disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
 	0x1423,		// don't delay PoWeROK1/2
 	0x9072,		// watchdog triggers PWROK, counts seconds
 #if !CONFIG_USE_WATCHDOG_ON_BOOT
 	0x0073, 0x0074,	// disarm watchdog by changing 56 s timeout to 0
 #endif
 	0xBF25, 0x172A, 0xF326,	// select GPIO function for most pins
-	0xFF27, 0xDF28, 0x2729,	// (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1)
+	0xBF27, 0xFF28, 0x2D29,	// (GP36=FAN_CTL3 (PWM), GP23,22,16,15=SPI, GP13=PWROK1)
 	0x66B8, 0x0CB9,	// enable pullups on SPI, RS485_EN
-	0x07C0,		// enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
-	0x07C8,		// config GP12-10 as output
+	0x07C0,		// enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE
+	0x06C8,		// config GP12,11 as output, GP10 as input
 	0x2DF5,		// map Hw Monitor Thermal Output to GP55
-	0x08F8,		// map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use)
+#if CONFIG_BOARD_OLD_REVISION
+	0x1F2A, 0xC072,	// switch GP13 to GPIO, WDT output from PWROK to KRST
+#endif
 };
 
 /* Early mainboard specific GPIO setup. */
@@ -161,7 +121,6 @@
 
 void main(unsigned long bist)
 {
-	int err;
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
@@ -189,12 +148,22 @@
 
 	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
-	/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
+#if CONFIG_BOARD_OLD_REVISION
+	/*
+	 * Old revision boards need a jumper shorting the power button to power
+	 * on automatically. So we must disable the button's fail-safe function,
+	 * or the board will shut down after 4 s.
+	 */
+	outl(0, PMS_IO_BASE + PM_FSD); // Fail-Save Delay register
+#else
+	int err;
+	/* bit0 = Spread Spectrum */
 	if ((err = smc_send_config(SMC_CONFIG))) {
 		print_err("ERROR ");
 		print_err_char('0'+err);
 		print_err(" sending config data to SMC\n");
 	}
+#endif
 
 	sdram_initialize(1, memctrl);
 
_
