diff -urb coreboot.patchtarget.r5756/src/devices/pci_device.c coreboot.r5756/src/devices/pci_device.c
--- coreboot.patchtarget.r5756/src/devices/pci_device.c	2010-09-10 00:10:14.189810151 +0300
+++ coreboot.r5756/src/devices/pci_device.c	2010-08-31 05:15:29.000000000 +0300
@@ -1017,6 +1017,14 @@
 		     bus->secondary >> 8, bus->secondary & 0xff);
 #else
 	printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
+	printk(BIOS_DEBUG, "PCI: pci_scan_bus limits devfn %x - devfn %x\n",
+	       min_devfn, max_devfn );
+
+	// Maximum sane devfn is 0xFF
+	if (max_devfn > 0xff) {
+	  printk(BIOS_DEBUG, "PCI: pci_scan_bus upper limit too big. Using 0xff.\n");
+	  max_devfn=0xff;
+	}
 #endif
 
 	old_devices = bus->children;
diff -urb coreboot.patchtarget.r5756/src/southbridge/amd/sb700/sb700_lpc.c coreboot.r5756/src/southbridge/amd/sb700/sb700_lpc.c
--- coreboot.patchtarget.r5756/src/southbridge/amd/sb700/sb700_lpc.c	2010-09-10 00:10:15.741812123 +0300
+++ coreboot.r5756/src/southbridge/amd/sb700/sb700_lpc.c	2010-08-31 05:15:29.000000000 +0300
@@ -29,12 +29,18 @@
 #include <arch/io.h>
 #include "sb700.h"
 
+#ifdef CONFIG_BOARD_ASUS_M4A785M
+#include <uart8250.h>
+#endif
+
+
 static void lpc_init(device_t dev)
 {
 	u8 byte;
 	u32 dword;
 	device_t sm_dev;
 
+	printk(BIOS_DEBUG, "sb700 entering lpc_init\n");
 	/* Enable the LPC Controller */
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 	dword = pci_read_config32(sm_dev, 0x64);
@@ -42,22 +48,33 @@
 	pci_write_config32(sm_dev, 0x64, dword);
 
 	/* Initialize isa dma */
+	printk(BIOS_DEBUG, "sb700 initializing isa dma\n");
+
+#ifdef CONFIG_BOARD_ASUS_M4A785M
+	printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
+#else
 	isa_dma_init();
+#endif
+
+	printk(BIOS_DEBUG, "sb700 isa dma initialized\n");
 
 	/* Enable DMA transaction on the LPC bus */
 	byte = pci_read_config8(dev, 0x40);
 	byte |= (1 << 2);
 	pci_write_config8(dev, 0x40, byte);
+	//printk(BIOS_DEBUG, "sb700 DMA enabled on LPC bus\n");
 
 	/* Disable the timeout mechanism on LPC */
 	byte = pci_read_config8(dev, 0x48);
 	byte &= ~(1 << 7);
 	pci_write_config8(dev, 0x48, byte);
+	//printk(BIOS_DEBUG, "sb700 LPC Timeout disabled\n");
 
 	/* Disable LPC MSI Capability */
 	byte = pci_read_config8(dev, 0x78);
 	byte &= ~(1 << 1);
 	pci_write_config8(dev, 0x78, byte);
+	printk(BIOS_DEBUG, "sb700 exiting lpc_init\n");
 }
 
 static void sb700_lpc_read_resources(device_t dev)
diff -urb coreboot.patchtarget.r5756/src/superio/ite/it8712f/it8712f_early_serial.c coreboot.r5756/src/superio/ite/it8712f/it8712f_early_serial.c
--- coreboot.patchtarget.r5756/src/superio/ite/it8712f/it8712f_early_serial.c	2010-09-10 00:10:14.853811296 +0300
+++ coreboot.r5756/src/superio/ite/it8712f/it8712f_early_serial.c	2010-08-31 05:15:29.000000000 +0300
@@ -47,6 +47,15 @@
 	outb(value, SIO_DATA);
 }
 
+static uint8_t it8712f_sio_read(uint8_t ldn, uint8_t index)
+{
+	outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	return inb(SIO_DATA);
+}
+
+
 static void it8712f_enter_conf(void)
 {
 	/*  Enter the configuration state (MB PnP mode). */
@@ -91,14 +100,18 @@
 	it8712f_exit_conf();
 }
 
-void it8712f_kill_watchdog(void)
+uint8_t it8712f_kill_watchdog(void)
 {
+        uint8_t prev_config;
 	it8712f_enter_conf();
 
+        prev_config = it8712f_sio_read(0x07, IT8712F_CONFIG_REG_WATCHDOG);
+
 	/* Kill the Watchdog */
 	it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
 
 	it8712f_exit_conf();
+	return prev_config;
 }
 
 /* Enable the peripheral devices on the IT8712F Super I/O chip. */
diff -urb coreboot.patchtarget.r5756/src/superio/ite/it8712f/it8712f.h coreboot.r5756/src/superio/ite/it8712f/it8712f.h
--- coreboot.patchtarget.r5756/src/superio/ite/it8712f/it8712f.h	2010-09-10 00:10:14.857811876 +0300
+++ coreboot.r5756/src/superio/ite/it8712f/it8712f.h	2010-08-31 05:15:29.000000000 +0300
@@ -34,7 +34,7 @@
 #define IT8712F_IR   0x0a /* Consumer IR */
 
 #ifndef __ROMCC__
-void it8712f_kill_watchdog(void);
+uint8_t it8712f_kill_watchdog(void);
 void it8712f_enable_serial(device_t dev, unsigned iobase);
 void it8712f_24mhz_clkin(void);
 void it8712f_enable_3vsbsw(void);
