Index: src/mainboard/supermicro/x6dai_g/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/romstage.c	(Revision 5893)
+++ src/mainboard/supermicro/x6dai_g/romstage.c	(Arbeitskopie)
@@ -21,9 +21,6 @@
 #include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -36,9 +33,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
Index: src/mainboard/supermicro/x6dhe_g/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/romstage.c	(Revision 5893)
+++ src/mainboard/supermicro/x6dhe_g/romstage.c	(Arbeitskopie)
@@ -22,9 +22,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -37,9 +34,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
Index: src/mainboard/supermicro/x6dhe_g2/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/romstage.c	(Revision 5893)
+++ src/mainboard/supermicro/x6dhe_g2/romstage.c	(Arbeitskopie)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
 
@@ -35,9 +32,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0708090a
-#define RECVENB_CONFIG  0x0708090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
Index: src/mainboard/supermicro/x6dhr_ig/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/romstage.c	(Revision 5893)
+++ src/mainboard/supermicro/x6dhr_ig/romstage.c	(Arbeitskopie)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -36,9 +33,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
Index: src/mainboard/supermicro/x6dhr_ig2/romstage.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/romstage.c	(Revision 5893)
+++ src/mainboard/supermicro/x6dhr_ig2/romstage.c	(Arbeitskopie)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
 
@@ -36,9 +33,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
Index: src/mainboard/dell/s1850/romstage.c
===================================================================
--- src/mainboard/dell/s1850/romstage.c	(Revision 5893)
+++ src/mainboard/dell/s1850/romstage.c	(Arbeitskopie)
@@ -20,9 +20,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
 
 #define DEVPRES_CONFIG  ( \
@@ -35,9 +32,6 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-#define RECVENA_CONFIG  0x0808090a
-#define RECVENB_CONFIG  0x0808090a
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
Index: src/mainboard/intel/truxton/romstage.c
===================================================================
--- src/mainboard/intel/truxton/romstage.c	(Revision 5893)
+++ src/mainboard/intel/truxton/romstage.c	(Arbeitskopie)
@@ -40,9 +40,6 @@
 #include "cpu/x86/bist.h"
 #include "spd.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
 static inline int spd_read_byte(u16 device, u8 address)
Index: src/mainboard/intel/mtarvon/romstage.c
===================================================================
--- src/mainboard/intel/mtarvon/romstage.c	(Revision 5893)
+++ src/mainboard/intel/mtarvon/romstage.c	(Arbeitskopie)
@@ -38,9 +38,6 @@
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
Index: src/mainboard/intel/eagleheights/romstage.c
===================================================================
--- src/mainboard/intel/eagleheights/romstage.c	(Revision 5893)
+++ src/mainboard/intel/eagleheights/romstage.c	(Arbeitskopie)
@@ -59,9 +59,6 @@
 #define UART_MSR 0x06
 #define UART_SCR 0x07
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
Index: src/mainboard/intel/jarrell/romstage.c
===================================================================
--- src/mainboard/intel/jarrell/romstage.c	(Revision 5893)
+++ src/mainboard/intel/jarrell/romstage.c	(Arbeitskopie)
@@ -29,10 +29,6 @@
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-/* Beta values:         0x00090800 */
-/* Silver values:       0x000a0900 */
-#define RECVENA_CONFIG  0x000a090a
-#define RECVENB_CONFIG  0x000a090a
 #define DIMM_MAP_LOGICAL 0x0124
 
 static inline int spd_read_byte(unsigned device, unsigned address)
