Contempt? Whatever.<div><br clear="all">Mark Beihoffer<br>Dragonfly Networks<br><a href="mailto:mbeihoffer@gmail.com">mbeihoffer@gmail.com</a><br><a href="mailto:mark@dragonfly-networks.com">mark@dragonfly-networks.com</a><br>
(612)508-5128<br>
<br><br><div class="gmail_quote">On Wed, Oct 20, 2010 at 12:31 AM, <span dir="ltr"><<a href="mailto:coreboot-request@coreboot.org">coreboot-request@coreboot.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
Send coreboot mailing list submissions to<br>
<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
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To subscribe or unsubscribe via the World Wide Web, visit<br>
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or, via email, send a message with subject or body 'help' to<br>
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You can reach the person managing the list at<br>
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<br>
When replying, please edit your Subject line so it is more specific<br>
than "Re: Contents of coreboot digest..."<br>
<br>
<br>
Today's Topics:<br>
<br>
1. [commit] r5976 - trunk/src/cpu/amd/car (repository service)<br>
2. Re: [PATCH] AMD F10h: set MMCONF bus count according<br>
toconfigured value (Peter Stuge)<br>
3. Re: [PATCH] fix cpu ht speed display in rs780_gfx.c (Liu Tao)<br>
4. Extension to inteltool and a request (Keith Hui)<br>
5. Re: coreboot Digest, Vol 68, Issue 108 (Mark Beihoffer)<br>
<br>
<br>
----------------------------------------------------------------------<br>
<br>
Message: 1<br>
Date: Tue, 19 Oct 2010 23:08:12 +0200<br>
From: repository service <<a href="mailto:svn@coreboot.org">svn@coreboot.org</a>><br>
To: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
Subject: [coreboot] [commit] r5976 - trunk/src/cpu/amd/car<br>
Message-ID: <<a href="mailto:E1P8JPo-0008L5-HC@ra.coresystems.de">E1P8JPo-0008L5-HC@ra.coresystems.de</a>><br>
Content-Type: text/plain; charset=UTF-8<br>
<br>
Author: sduplichan<br>
Date: Tue Oct 19 23:08:11 2010<br>
New Revision: 5976<br>
URL: <a href="https://tracker.coreboot.org/trac/coreboot/changeset/5976" target="_blank">https://tracker.coreboot.org/trac/coreboot/changeset/5976</a><br>
<br>
Log:<br>
For AMD family 10h processors, msr c0010058 is always programmed<br>
for 256 buses, even if fewer are configured. This patch lets msr<br>
c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER.<br>
<br>
Signed-off-by: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
Acked-by: Myles Watson <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br>
<br>
Modified:<br>
trunk/src/cpu/amd/car/cache_as_ram.inc<br>
<br>
Modified: trunk/src/cpu/amd/car/cache_as_ram.inc<br>
==============================================================================<br>
--- trunk/src/cpu/amd/car/cache_as_ram.inc Tue Oct 19 17:25:06 2010 (r5975)<br>
+++ trunk/src/cpu/amd/car/cache_as_ram.inc Tue Oct 19 23:08:11 2010 (r5976)<br>
@@ -132,14 +132,34 @@<br>
wrmsr<br>
<br>
#if CONFIG_MMCONF_SUPPORT<br>
- /* Set MMIO config space BAR. */<br>
- movl $MSR_MCFG_BASE, %ecx<br>
- rdmsr<br>
- andl $(~(0xfff00000 | (0xf << 2))), %eax<br>
- orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000)), %eax<br>
- orl $((8 << 2) | (1 << 0)), %eax<br>
- andl $(~(0x0000ffff)), %edx<br>
- orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx<br>
+ #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)<br>
+ #error "MMCONF_BASE_ADDRESS too big"<br>
+ #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)<br>
+ #error "MMCONF_BASE_ADDRESS not 1MB aligned"<br>
+ #endif<br>
+ movl $0, %edx<br>
+ movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax<br>
+ #if (CONFIG_MMCONF_BUS_NUMBER == 1)<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 2)<br>
+ orl $(1 << 2), %eax<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 4)<br>
+ orl $(2 << 2), %eax<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 8)<br>
+ orl $(3 << 2), %eax<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 16)<br>
+ orl $(4 << 2), %eax<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 32)<br>
+ orl $(5 << 2), %eax<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 64)<br>
+ orl $(6 << 2), %eax<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 128)<br>
+ orl $(7 << 2), %eax<br>
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 256)<br>
+ orl $(8 << 2), %eax<br>
+ #else<br>
+ #error "bad MMCONF_BUS_NUMBER value"<br>
+ #endif<br>
+ movl $(0xc0010058), %ecx<br>
wrmsr<br>
#endif<br>
<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 2<br>
Date: Wed, 20 Oct 2010 00:17:31 +0200<br>
From: Peter Stuge <<a href="mailto:peter@stuge.se">peter@stuge.se</a>><br>
To: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
according toconfigured value<br>
Message-ID: <<a href="mailto:20101019221731.1550.qmail@stuge.se">20101019221731.1550.qmail@stuge.se</a>><br>
Content-Type: text/plain; charset=us-ascii<br>
<br>
Scott Duplichan wrote:<br>
> back to inlined code with the extra error checks:<br>
><br>
> Signed-off-by: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a><br>
<br>
Acked-by: Peter Stuge <<a href="mailto:peter@stuge.se">peter@stuge.se</a>><br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 3<br>
Date: Wed, 20 Oct 2010 09:13:17 +0800<br>
From: Liu Tao <<a href="mailto:liutao1980@gmail.com">liutao1980@gmail.com</a>><br>
To: Uwe Hermann <<a href="mailto:uwe@hermann-uwe.de">uwe@hermann-uwe.de</a>><br>
Cc: Myles Watson <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>>, <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
Subject: Re: [coreboot] [PATCH] fix cpu ht speed display in<br>
rs780_gfx.c<br>
Message-ID:<br>
<<a href="mailto:AANLkTinGdeiSayFcuGp5dffa1qL6eq2uLCFOpwNx1280@mail.gmail.com">AANLkTinGdeiSayFcuGp5dffa1qL6eq2uLCFOpwNx1280@mail.gmail.com</a>><br>
Content-Type: text/plain; charset=ISO-8859-1<br>
<br>
The name of sblink seems more clear, but for most cases, the name of sblk<br>
only appears in K8/Fam10 codes, so it didn't cause much confusions.<br>
<br>
A more consistent way to get HT southbridge link in sb700 chipset is to include<br>
the <cpu/amd/amdk8_sysconf.h> or <cpu/amd/amdfam10_sysconf.h>, and<br>
use global variable sysconf.sblk. For now, fam10 codes set sysconf.sblk during<br>
early romstage, but K8 codes didn't. Maybe we should fix K8 coeds to set<br>
sysconf.sblk earlyer, and use it in later device drivers.<br>
<br>
On Mon, Oct 18, 2010 at 6:01 AM, Uwe Hermann <<a href="mailto:uwe@hermann-uwe.de">uwe@hermann-uwe.de</a>> wrote:<br>
> On Sun, Oct 17, 2010 at 11:39:46PM +0200, Uwe Hermann wrote:<br>
>> ?- Renamed sblk to sblink (the name of the register bits as per<br>
>> ? ?BIOS + Kernel Developer's Guide for AMD Athlon 64 & AMD Opteron Processors,<br>
>> ? ?chapter 3.3.8.<br>
><br>
> Hm, I noticed that the K8/Fam10h code uses "sblk" as function/variable name<br>
> pretty consistently, but I can't seem to find that spelling in any of<br>
> the AMD manuals. Should we rename "sblk" to "sblink" in the whole tree?<br>
<br>
--<br>
Regards,<br>
Liu Tao<br>
<br>
<br>
<br>
------------------------------<br>
<br>
Message: 4<br>
Date: Wed, 20 Oct 2010 00:57:21 -0400<br>
From: Keith Hui <<a href="mailto:buurin@gmail.com">buurin@gmail.com</a>><br>
To: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
Subject: [coreboot] Extension to inteltool and a request<br>
Message-ID:<br>
<<a href="mailto:AANLkTimCnR9RdDSMpNYk72DrP6rHvemX41R-f3ZZVCVk@mail.gmail.com">AANLkTimCnR9RdDSMpNYk72DrP6rHvemX41R-f3ZZVCVk@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="iso-8859-1"<br>
<br>
Hi all,<br>
<br>
This patch extends inteltool's MSR dumping to all Slot 1 Intel CPUs.<br>
<br>
I made this an attempt to gather some information for an updated L2<br>
patch, so I have a request to all,<br>
<br>
Can anyone with a Slot 1 CPU apply the attached patch, compile<br>
inteltool, and post the output together with some information on your<br>
CPU?<br>
<br>
Thanks.<br>
<br>
Patch is Signed-off-by: Keith Hui <<a href="mailto:buurin@gmail.com">buurin@gmail.com</a>><br>
if it's useful for the future and worth committing.<br>
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<br>
------------------------------<br>
<br>
Message: 5<br>
Date: Wed, 20 Oct 2010 00:03:51 -0500<br>
From: Mark Beihoffer <<a href="mailto:mbeihoffer@gmail.com">mbeihoffer@gmail.com</a>><br>
To: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
Subject: Re: [coreboot] coreboot Digest, Vol 68, Issue 108<br>
Message-ID:<br>
<<a href="mailto:AANLkTim3vkJMKTPAkdASPn_oHp1c4aocpkR94287tpcx@mail.gmail.com">AANLkTim3vkJMKTPAkdASPn_oHp1c4aocpkR94287tpcx@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
I tried that and it worked! Thants!<br>
<br>
Mark Beihoffer<br>
Dragonfly Networks<br>
<a href="mailto:mbeihoffer@gmail.com">mbeihoffer@gmail.com</a><br>
<a href="mailto:mark@dragonfly-networks.com">mark@dragonfly-networks.com</a><br>
(612)508-5128<br>
<br>
<br>
On Tue, Oct 19, 2010 at 2:03 PM, <<a href="mailto:coreboot-request@coreboot.org">coreboot-request@coreboot.org</a>> wrote:<br>
<br>
> Send coreboot mailing list submissions to<br>
> <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
><br>
> To subscribe or unsubscribe via the World Wide Web, visit<br>
> <a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
> or, via email, send a message with subject or body 'help' to<br>
> <a href="mailto:coreboot-request@coreboot.org">coreboot-request@coreboot.org</a><br>
><br>
> You can reach the person managing the list at<br>
> <a href="mailto:coreboot-owner@coreboot.org">coreboot-owner@coreboot.org</a><br>
><br>
> When replying, please edit your Subject line so it is more specific<br>
> than "Re: Contents of coreboot digest..."<br>
><br>
><br>
> Today's Topics:<br>
><br>
> 1. Re: [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value (Scott Duplichan)<br>
> 2. Re: [PATCH] AMD F10h: set MMCONF bus count<br>
> accordingtoconfigured value (Myles Watson)<br>
> 3. Re: [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value (Carl-Daniel Hailfinger)<br>
> 4. Re: [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value (Scott Duplichan)<br>
> 5. Re: [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value (Myles Watson)<br>
> 6. Re: [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value (Scott Duplichan)<br>
> 7. Re: [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value (Myles Watson)<br>
><br>
><br>
> ----------------------------------------------------------------------<br>
><br>
> Message: 1<br>
> Date: Tue, 19 Oct 2010 12:47:08 -0500<br>
> From: "Scott Duplichan" <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> To: "'Arne Georg Gleditsch'" <<a href="mailto:arne.gleditsch@numascale.com">arne.gleditsch@numascale.com</a>><br>
> Cc: 'Coreboot' <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
> according toconfigured value<br>
> Message-ID: <51AC17B3FD284FE6BA8547D65AC3C0C5@m3a78><br>
> Content-Type: text/plain; charset="us-ascii"<br>
><br>
> -----Original Message-----<br>
> From: <a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a> [mailto:<a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a>]<br>
> On Behalf Of Arne Georg Gleditsch<br>
> Sent: Tuesday, October 19, 2010 01:51 AM<br>
> To: Scott Duplichan<br>
> Cc: 'Coreboot'<br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value<br>
><br>
> ]"Scott Duplichan" <<a href="mailto:scott@notabs.org">scott@notabs.org</a>> writes:<br>
> ]<br>
> ]> For AMD family 10h processors, msr c0010058 is always programmed<br>
> ]> for 256 buses, even if fewer are configured. This patch lets msr<br>
> ]> c0010058 programming use the configured bus count,<br>
> CONFIG_MMCONF_BUS_NUMBER.<br>
> ]<br>
> ]How about just renaming CONFIG_MMCONF_BUS_NUMBER to ...BUS_BITS?<br>
> ]There's only 8 discrete values it can take anyway, and this would also<br>
> ]make it harder to pick an unsupported value for BUS_NUMBER.<br>
> ]<br>
> ]--<br>
> ] Arne.<br>
><br>
> Hello Arne,<br>
><br>
> Thanks for the suggestion. It would certainly eliminate the awkward<br>
> logic. On the other hand, if anyone is overriding the kconfig<br>
> value CONFIG_MMCONF_BUS_NUMBER locally, they would have to update<br>
> their override.<br>
><br>
> Last night, I thought I would just learn about gas macros and do it<br>
> that way. It was more difficult than I thought. I cannot even find<br>
> examples of gas macros that use arguments. A C style macro seemed<br>
> possible, but I found when gas processes it the needed ?: does not<br>
> work. So I ended up with a gas macro that does not use arguments.<br>
> The macro allows the awkwark logic and additional error checking to<br>
> be placed in an existing include file. The new error checking was<br>
> tested by forcing a few failing cases:<br>
><br>
><br>
> Signed-off-by: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
><br>
> Index: src/include/cpu/amd/mtrr.h<br>
> ===================================================================<br>
> --- src/include/cpu/amd/mtrr.h (revision 5975)<br>
> +++ src/include/cpu/amd/mtrr.h (working copy)<br>
> @@ -32,6 +32,44 @@<br>
> #define TOP_MEM_MASK 0x007fffff<br>
> #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)<br>
><br>
> +<br>
> +#if defined(ASSEMBLY)<br>
> +<br>
> +.macro SET_C0010058<br>
> + #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)<br>
> + #error MMCONF_BASE_ADDRESS too big<br>
> + #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)<br>
> + #error MMCONF_BASE_ADDRESS not 1MB aligned<br>
> + #endif<br>
> + movl $0, %edx<br>
> + movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax<br>
> + #if (CONFIG_MMCONF_BUS_NUMBER == 1)<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 2)<br>
> + orl $(1 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 4)<br>
> + orl $(2 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 8)<br>
> + orl $(3 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 16)<br>
> + orl $(4 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 32)<br>
> + orl $(5 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 64)<br>
> + orl $(6 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 128)<br>
> + orl $(7 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 256)<br>
> + orl $(8 << 2), %eax<br>
> + #else<br>
> + #error "bad MMCONF_BUS_NUMBER value"<br>
> + #endif<br>
> + movl $(0xc0010058), %ecx<br>
> + wrmsr<br>
> +.endm<br>
> +<br>
> +#endif<br>
> +<br>
> +<br>
> #if !defined(__PRE_RAM__) && !defined(ASSEMBLY)<br>
> void amd_setup_mtrrs(void);<br>
> #endif<br>
> Index: src/cpu/amd/car/cache_as_ram.inc<br>
> ===================================================================<br>
> --- src/cpu/amd/car/cache_as_ram.inc (revision 5975)<br>
> +++ src/cpu/amd/car/cache_as_ram.inc (working copy)<br>
> @@ -132,15 +132,7 @@<br>
> wrmsr<br>
><br>
> #if CONFIG_MMCONF_SUPPORT<br>
> - /* Set MMIO config space BAR. */<br>
> - movl $MSR_MCFG_BASE, %ecx<br>
> - rdmsr<br>
> - andl $(~(0xfff00000 | (0xf << 2))), %eax<br>
> - orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000)), %eax<br>
> - orl $((8 << 2) | (1 << 0)), %eax<br>
> - andl $(~(0x0000ffff)), %edx<br>
> - orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx<br>
> - wrmsr<br>
> + SET_C0010058<br>
> #endif<br>
><br>
> CAR_FAM10_out_post_errata:<br>
><br>
><br>
><br>
><br>
><br>
> ------------------------------<br>
><br>
> Message: 2<br>
> Date: Tue, 19 Oct 2010 12:05:48 -0600<br>
> From: "Myles Watson" <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br>
> To: "'Scott Duplichan'" <<a href="mailto:scott@notabs.org">scott@notabs.org</a>>, "'Arne Georg Gleditsch'"<br>
> <<a href="mailto:arne.gleditsch@numascale.com">arne.gleditsch@numascale.com</a>><br>
> Cc: 'Coreboot' <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
> accordingtoconfigured value<br>
> Message-ID: <7ABE7F9D18144867B79B98A8C6407C8A@chimp><br>
> Content-Type: text/plain; charset="us-ascii"<br>
><br>
> > Last night, I thought I would just learn about gas macros and do it<br>
> > that way. It was more difficult than I thought. I cannot even find<br>
> > examples of gas macros that use arguments. A C style macro seemed<br>
> > possible, but I found when gas processes it the needed ?: does not<br>
> > work. So I ended up with a gas macro that does not use arguments.<br>
> > The macro allows the awkwark logic and additional error checking to<br>
> > be placed in an existing include file. The new error checking was<br>
> > tested by forcing a few failing cases:<br>
> ><br>
> ><br>
> > Signed-off-by: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> I'm sorry that I wasn't more clear. I think it was better before. The<br>
> code<br>
> looks exactly the same, but it's in a different file, which wasn't my<br>
> intent<br>
> at all.<br>
><br>
> I like the other version much better. I hope that your new knowledge of<br>
> gas<br>
> macros will come in handy in the future :)<br>
><br>
> Thanks,<br>
> Myles<br>
><br>
><br>
><br>
><br>
> ------------------------------<br>
><br>
> Message: 3<br>
> Date: Tue, 19 Oct 2010 20:24:38 +0200<br>
> From: Carl-Daniel Hailfinger <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>><br>
> To: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> Cc: 'Arne Georg Gleditsch' <<a href="mailto:arne.gleditsch@numascale.com">arne.gleditsch@numascale.com</a>>, 'Coreboot'<br>
> <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
> according toconfigured value<br>
> Message-ID: <<a href="mailto:4CBDE266.2050604@gmx.net">4CBDE266.2050604@gmx.net</a>><br>
> Content-Type: text/plain; charset=ISO-8859-1<br>
><br>
> Hi Scott,<br>
><br>
> On 19.10.2010 19:47, Scott Duplichan wrote:<br>
> > Last night, I thought I would just learn about gas macros and do it<br>
> > that way. It was more difficult than I thought. I cannot even find<br>
> > examples of gas macros that use arguments.<br>
><br>
> Take a look at src/cpu/amd/car/cache_as_ram.inc, specifically<br>
> extractmask and simplemask.<br>
><br>
> Regards,<br>
> Carl-Daniel<br>
><br>
> --<br>
> <a href="http://www.hailfinger.org/" target="_blank">http://www.hailfinger.org/</a><br>
><br>
><br>
><br>
><br>
> ------------------------------<br>
><br>
> Message: 4<br>
> Date: Tue, 19 Oct 2010 13:34:20 -0500<br>
> From: "Scott Duplichan" <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> To: "'Carl-Daniel Hailfinger'" <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>><br>
> Cc: 'Arne Georg Gleditsch' <<a href="mailto:arne.gleditsch@numascale.com">arne.gleditsch@numascale.com</a>>, 'Coreboot'<br>
> <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
> according toconfigured value<br>
> Message-ID: <E22BFE2842734C9D87B56FB2388A7CC4@m3a78><br>
> Content-Type: text/plain; charset="us-ascii"<br>
><br>
> -----Original Message-----<br>
> From: <a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a> [mailto:<a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a>]<br>
> On Behalf Of Carl-Daniel Hailfinger<br>
> Sent: Tuesday, October 19, 2010 01:25 PM<br>
> To: Scott Duplichan<br>
> Cc: 'Arne Georg Gleditsch'; 'Coreboot'<br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value<br>
><br>
> ]Hi Scott,<br>
> ]<br>
> ]On 19.10.2010 19:47, Scott Duplichan wrote:<br>
> ]> Last night, I thought I would just learn about gas macros and do it<br>
> ]> that way. It was more difficult than I thought. I cannot even find<br>
> ]> examples of gas macros that use arguments.<br>
> ]<br>
> ]Take a look at src/cpu/amd/car/cache_as_ram.inc, specifically<br>
> ]extractmask and simplemask.<br>
> ]<br>
> ]Regards,<br>
> ]Carl-Daniel<br>
> ]<br>
> ]--<br>
> ]<a href="http://www.hailfinger.org/" target="_blank">http://www.hailfinger.org/</a><br>
><br>
><br>
><br>
> Thanks Carl-Daniel.<br>
><br>
> Hello Myles,<br>
><br>
> I am not so happy with the new one either. What I really wanted was a<br>
> macro called highestSetBit. That way, the reader can guess what macro<br>
> invocation highestSetBit (CONFIG_MMCONF_BUS_NUMBER) does without<br>
> actually digging it out. But I could not find a way to make that work.<br>
> Another idea was to find highestSetBit at runtime, if it could be done<br>
> a short and readable code sequence. This would be possible with family<br>
> 15h, where instructions such as lzcnt are supported. But family 10h<br>
> does not have this instruction.<br>
><br>
> Now that Carl-Daniel has showed how to do gas macros, how about I add a<br>
> highestSetBit macro to amd/mtrr.h? Then everything else can be inlined?<br>
><br>
> Thanks,<br>
> Scott<br>
><br>
><br>
><br>
><br>
> ------------------------------<br>
><br>
> Message: 5<br>
> Date: Tue, 19 Oct 2010 12:39:47 -0600<br>
> From: Myles Watson <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br>
> To: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> Cc: Coreboot <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
> according toconfigured value<br>
> Message-ID:<br>
> <AANLkTin0CEA+NtTi_owW6ux=<a href="mailto:5bBkr2-QhSGawEwDqFx0@mail.gmail.com">5bBkr2-QhSGawEwDqFx0@mail.gmail.com</a>><br>
> Content-Type: text/plain; charset=ISO-8859-1<br>
><br>
> On Tue, Oct 19, 2010 at 12:34 PM, Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> wrote:<br>
> > -----Original Message-----<br>
> > From: <a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a> [mailto:<br>
> <a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a>] On Behalf Of Carl-Daniel Hailfinger<br>
> > Sent: Tuesday, October 19, 2010 01:25 PM<br>
> > To: Scott Duplichan<br>
> > Cc: 'Arne Georg Gleditsch'; 'Coreboot'<br>
> > Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count according<br>
> toconfigured value<br>
> ><br>
> > ]Hi Scott,<br>
> > ]<br>
> > ]On 19.10.2010 19:47, Scott Duplichan wrote:<br>
> > ]> Last night, I thought I would just learn about gas macros and do it<br>
> > ]> that way. It was more difficult than I thought. I cannot even find<br>
> > ]> examples of gas macros that use arguments.<br>
> > ]<br>
> > ]Take a look at src/cpu/amd/car/cache_as_ram.inc, specifically<br>
> > ]extractmask and simplemask.<br>
> > ]<br>
> > ]Regards,<br>
> > ]Carl-Daniel<br>
> > ]<br>
> > ]--<br>
> > ]<a href="http://www.hailfinger.org/" target="_blank">http://www.hailfinger.org/</a><br>
> ><br>
> ><br>
> ><br>
> > Thanks Carl-Daniel.<br>
> ><br>
> > Hello Myles,<br>
> ><br>
> > I am not so happy with the new one either. What I really wanted was a<br>
> > macro called highestSetBit. That way, the reader can guess what macro<br>
> > invocation highestSetBit (CONFIG_MMCONF_BUS_NUMBER) does without<br>
> > actually digging it out. But I could not find a way to make that work.<br>
> > Another idea was to find highestSetBit at runtime, if it could be done<br>
> > a short and readable code sequence. This would be possible with family<br>
> > 15h, where instructions such as lzcnt are supported. But family 10h<br>
> > does not have this instruction.<br>
> ><br>
> > Now that Carl-Daniel has showed how to do gas macros, how about I add a<br>
> > highestSetBit macro to amd/mtrr.h? Then everything else can be inlined?<br>
><br>
> I would say it isn't worth the effort, but it's up to you. The<br>
> problem with macros in assembly is that it's unclear which registers<br>
> they clobber. That was why I suggested a pre-processor macro, but<br>
> it's not that important.<br>
><br>
> Thanks,<br>
> Myles<br>
><br>
><br>
><br>
> ------------------------------<br>
><br>
> Message: 6<br>
> Date: Tue, 19 Oct 2010 13:56:14 -0500<br>
> From: "Scott Duplichan" <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> To: "'Myles Watson'" <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br>
> Cc: 'Coreboot' <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
> according toconfigured value<br>
> Message-ID: <6D1AD5ECCB184C52B72A0F9A7CE30587@m3a78><br>
> Content-Type: text/plain; charset="us-ascii"<br>
><br>
> ]I would say it isn't worth the effort, but it's up to you. The<br>
> ]problem with macros in assembly is that it's unclear which registers<br>
> ]they clobber. That was why I suggested a pre-processor macro, but<br>
> ]it's not that important.<br>
> ]<br>
> ]Thanks,<br>
> ]Myles<br>
><br>
> Hello Myles,<br>
><br>
> Good point. Best would be a 'macro' that allows writing:<br>
> movl highestSetBit (busn), %eax<br>
> But that is not possible apparently. How about then, back<br>
> to inlined code with the extra error checks:<br>
><br>
> Signed-off-by: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a><br>
><br>
> Index: src/cpu/amd/car/cache_as_ram.inc<br>
> ===================================================================<br>
> --- src/cpu/amd/car/cache_as_ram.inc (revision 5975)<br>
> +++ src/cpu/amd/car/cache_as_ram.inc (working copy)<br>
> @@ -132,15 +132,35 @@<br>
> wrmsr<br>
><br>
> #if CONFIG_MMCONF_SUPPORT<br>
> - /* Set MMIO config space BAR. */<br>
> - movl $MSR_MCFG_BASE, %ecx<br>
> - rdmsr<br>
> - andl $(~(0xfff00000 | (0xf << 2))), %eax<br>
> - orl $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000)), %eax<br>
> - orl $((8 << 2) | (1 << 0)), %eax<br>
> - andl $(~(0x0000ffff)), %edx<br>
> - orl $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx<br>
> - wrmsr<br>
> + #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)<br>
> + #error "MMCONF_BASE_ADDRESS too big"<br>
> + #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)<br>
> + #error "MMCONF_BASE_ADDRESS not 1MB aligned"<br>
> + #endif<br>
> + movl $0, %edx<br>
> + movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax<br>
> + #if (CONFIG_MMCONF_BUS_NUMBER == 1)<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 2)<br>
> + orl $(1 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 4)<br>
> + orl $(2 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 8)<br>
> + orl $(3 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 16)<br>
> + orl $(4 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 32)<br>
> + orl $(5 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 64)<br>
> + orl $(6 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 128)<br>
> + orl $(7 << 2), %eax<br>
> + #elif (CONFIG_MMCONF_BUS_NUMBER == 256)<br>
> + orl $(8 << 2), %eax<br>
> + #else<br>
> + #error "bad MMCONF_BUS_NUMBER value"<br>
> + #endif<br>
> + movl $(0xc0010058), %ecx<br>
> + wrmsr<br>
> #endif<br>
><br>
> CAR_FAM10_out_post_errata:<br>
><br>
> -------------- next part --------------<br>
> An embedded and charset-unspecified text was scrubbed...<br>
> Name: mmconf-patch-1.txt<br>
> URL: <<br>
> <a href="http://www.coreboot.org/pipermail/coreboot/attachments/20101019/1122fa41/attachment-0001.txt" target="_blank">http://www.coreboot.org/pipermail/coreboot/attachments/20101019/1122fa41/attachment-0001.txt</a><br>
> ><br>
><br>
> ------------------------------<br>
><br>
> Message: 7<br>
> Date: Tue, 19 Oct 2010 13:03:13 -0600<br>
> From: "Myles Watson" <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br>
> To: "'Scott Duplichan'" <<a href="mailto:scott@notabs.org">scott@notabs.org</a>><br>
> Cc: 'Coreboot' <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count<br>
> according toconfigured value<br>
> Message-ID: <07F0B79D477647709F8349C9B2053647@chimp><br>
> Content-Type: text/plain; charset="us-ascii"<br>
><br>
> > Good point. Best would be a 'macro' that allows writing:<br>
> > movl highestSetBit (busn), %eax<br>
> > But that is not possible apparently. How about then, back<br>
> > to inlined code with the extra error checks:<br>
> ><br>
> > Signed-off-by: Scott Duplichan <<a href="mailto:scott@notabs.org">scott@notabs.org</a><br>
> Acked-by: Myles Watson <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br>
><br>
> Thanks,<br>
> Myles<br>
><br>
><br>
><br>
><br>
><br>
> ------------------------------<br>
><br>
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><br>
> End of coreboot Digest, Vol 68, Issue 108<br>
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</blockquote></div><br></div>