hi, <div> i would like to suggest that put all of the log into the attachment.</div><div>Put the patch into another attachment too. </div><div><br><div class="gmail_quote">2010/10/21 Tobias Diedrich <span dir="ltr"><<a href="mailto:ranma%2Bcoreboot@tdiedrich.de">ranma+coreboot@tdiedrich.de</a>></span><br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Hi,<br>
<br>
did you get somewhere with your M2V?<br>
I'm looking into it right now, but I don't have the vt8237a docs.<br>
Coreboot starts initializing HW, but it hangs during the bus scan...<br>
Looks like it hangs while trying to scan the pcie bridge 00:02.0<br>
<br>
<br>
<br>
coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 starting...<br>
now booting...<br>
Enabling routing table for node 00 done.<br>
Enabling UP settings<br>
Disabling read/write/fill probes for UP... done.<br>
coherent_ht_finalize<br>
done<br>
core0 started:<br>
now booting... All core 0 started<br>
started ap apicid:<br>
SBLink=00<br>
NC node|link=00<br>
00entering optimize_link_incoherent_ht<br>
sysinfo->link_pair_num=0x1<br>
entering ht_optimize_link<br>
pos=0x8a, unfiltered freq_cap=0x8075<br>
pos=0x8a, filtered freq_cap=0x75<br>
pos=0x6e, unfiltered freq_cap=0x75<br>
pos=0x6e, filtered freq_cap=0x75<br>
freq_cap1=0x75, freq_cap2=0x75<br>
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1<br>
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1<br>
width_cap1=0x11, width_cap2=0x11<br>
dev1 input ln_width1=0x4, ln_width2=0x4<br>
dev1 input width=0x1<br>
dev1 output ln_width1=0x4, ln_width2=0x4<br>
dev1 input|output width=0x11<br>
old dev1 input|output width=0x11<br>
dev2 input|output width=0x11<br>
old dev2 input|output width=0x11<br>
after ht_optimize_link for link pair 0, reset_needed=0x1<br>
after optimize_link_read_pointers_chain, reset_needed=0x1<br>
01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075<br>
01ht reset -<br>
soft reset<br>
<br>
<br>
coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 starting...<br>
now booting...<br>
Enabling routing table for node 00 done.<br>
Enabling UP settings<br>
Disabling read/write/fill probes for UP... done.<br>
coherent_ht_finalize<br>
done<br>
core0 started:<br>
now booting... All core 0 started<br>
started ap apicid:<br>
SBLink=00<br>
NC node|link=00<br>
00entering optimize_link_incoherent_ht<br>
sysinfo->link_pair_num=0x1<br>
entering ht_optimize_link<br>
pos=0x8a, unfiltered freq_cap=0x8075<br>
pos=0x8a, filtered freq_cap=0x75<br>
pos=0x6e, unfiltered freq_cap=0x75<br>
pos=0x6e, filtered freq_cap=0x75<br>
freq_cap1=0x75, freq_cap2=0x75<br>
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0<br>
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0<br>
width_cap1=0x11, width_cap2=0x11<br>
dev1 input ln_width1=0x4, ln_width2=0x4<br>
dev1 input width=0x1<br>
dev1 output ln_width1=0x4, ln_width2=0x4<br>
dev1 input|output width=0x11<br>
old dev1 input|output width=0x11<br>
dev2 input|output width=0x11<br>
old dev2 input|output width=0x11<br>
after ht_optimize_link for link pair 0, reset_needed=0x0<br>
after optimize_link_read_pointers_chain, reset_needed=0x0<br>
00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075<br>
00after enable_fid_change<br>
toggle LDTSTP#<br>
done<br>
Current fid_cur: 0x2, fid_max: 0xc<br>
Requested fid_new: 0xc<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
FidVid table step fidvid: 0xc<br>
toggle LDTSTP#<br>
done<br>
toggle LDTSTP#<br>
done<br>
set vid failed for apicid =00<br>
set fid failed for apicid =00<br>
enable_smbus()<br>
Ram1.00<br>
setting up CPU 00 northbridge registers<br>
done.<br>
Ram2.00<br>
sdram_set_spd_registers: paramx :000ceee8<br>
Enabling dual channel memory<br>
Unbuffered<br>
266MHz<br>
266MHz<br>
Interleaved<br>
RAM end at 0x00800000 kB<br>
Ram3<br>
Initializing memory: done<br>
Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB<br>
Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB<br>
Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB<br>
Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB<br>
Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB<br>
Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB<br>
DQS Training:RcvrEn:Pass1: 00<br>
CTLRMaxDelay=06<br>
done<br>
DQS Training:DQSPos: 00<br>
TrainDQSRdWrPos: buf_a:000ce950<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
TrainDQSPos: MutualCSPassW[48] :000ce828<br>
done<br>
DQS Training:RcvrEn:Pass2: 00<br>
CTLRMaxDelay=38<br>
done<br>
DQS SAVE NVRAM: c2000<br>
Writing 111322 of size 4 to nvram pos: 0<br>
Writing 17181717 of size 4 to nvram pos: 4<br>
Writing 17181817 of size 4 to nvram pos: 8<br>
Writing 17 of size 1 to nvram pos: 12<br>
Writing 342f00 of size 4 to nvram pos: 13<br>
Writing 16161717 of size 4 to nvram pos: 17<br>
Writing 17161717 of size 4 to nvram pos: 21<br>
Writing 17 of size 1 to nvram pos: 25<br>
Writing 35 of size 1 to nvram pos: 26<br>
Writing 38 of size 1 to nvram pos: 27<br>
Writing 0 of size 1 to nvram pos: 28<br>
Writing 0 of size 1 to nvram pos: 29<br>
Writing 111322 of size 4 to nvram pos: 30<br>
Writing 17161617 of size 4 to nvram pos: 34<br>
Writing 17171818 of size 4 to nvram pos: 38<br>
Writing 18 of size 1 to nvram pos: 42<br>
Writing 342f00 of size 4 to nvram pos: 43<br>
Writing 16161615 of size 4 to nvram pos: 47<br>
Writing 18161616 of size 4 to nvram pos: 51<br>
Writing 16 of size 1 to nvram pos: 55<br>
Writing 35 of size 1 to nvram pos: 56<br>
Writing 38 of size 1 to nvram pos: 57<br>
Writing 0 of size 1 to nvram pos: 58<br>
Writing 0 of size 1 to nvram pos: 59<br>
Writing 34108099 of size 4 to nvram pos: 60<br>
DQS Training:tsc[00]=000000006852302d<br>
DQS Training:tsc[01]=0000000069705232<br>
DQS Training:tsc[02]=000000006970523b<br>
DQS Training:tsc[03]=00000000f0113e95<br>
DQS Training:tsc[04]=00000001021a6006<br>
Ram4<br>
v_esp=000cef28<br>
testx = 5a5a5a5a<br>
Copying data from cache to RAM -- switching to use RAM as stack... Done<br>
testx = 5a5a5a5a<br>
Disabling cache as ram now<br>
Clearing initial memory region: Done<br>
Loading stage image.<br>
Check CBFS header at fffffc6e<br>
magic is 4f524243<br>
Found CBFS header at fffffc6e<br>
Check fallback/romstage<br>
CBFS: follow chain: fffc0000 + 38 + b461 + align -> fffcb4c0<br>
Check fallback/coreboot_ram<br>
Stage: loading fallback/coreboot_ram @ 0x100000 (491520 bytes), entry @ 0x100000<br>
Stage: done loading.<br>
Jumping to image.<br>
coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 booting...<br>
Enumerating buses...<br>
Show all devs...Before Device Enumeration.<br>
Root Device: enabled 1<br>
APIC_CLUSTER: 0: enabled 1<br>
APIC: 00: enabled 1<br>
PCI_DOMAIN: 0000: enabled 1<br>
PCI: 00:18.0: enabled 1<br>
PCI: 00:00.0: enabled 1<br>
PCI: 00:0f.1: enabled 1<br>
PCI: 00:11.0: enabled 1<br>
I2C: 00:50: enabled 1<br>
I2C: 00:51: enabled 1<br>
I2C: 00:52: enabled 1<br>
I2C: 00:53: enabled 1<br>
PNP: 002e.0: enabled 1<br>
PNP: 002e.1: enabled 1<br>
PNP: 002e.2: enabled 1<br>
PNP: 002e.3: enabled 0<br>
PNP: 002e.4: enabled 1<br>
PNP: 002e.5: enabled 0<br>
PNP: 002e.6: enabled 0<br>
PNP: 002e.7: enabled 0<br>
PNP: 002e.8: enabled 0<br>
PNP: 002e.9: enabled 0<br>
PNP: 002e.a: enabled 0<br>
PCI: 00:12.0: enabled 0<br>
PCI: 00:18.1: enabled 1<br>
PCI: 00:18.2: enabled 1<br>
PCI: 00:18.3: enabled 1<br>
Compare with tree...<br>
Root Device: enabled 1<br>
APIC_CLUSTER: 0: enabled 1<br>
APIC: 00: enabled 1<br>
PCI_DOMAIN: 0000: enabled 1<br>
PCI: 00:18.0: enabled 1<br>
PCI: 00:00.0: enabled 1<br>
PCI: 00:0f.1: enabled 1<br>
PCI: 00:11.0: enabled 1<br>
I2C: 00:50: enabled 1<br>
I2C: 00:51: enabled 1<br>
I2C: 00:52: enabled 1<br>
I2C: 00:53: enabled 1<br>
PNP: 002e.0: enabled 1<br>
PNP: 002e.1: enabled 1<br>
PNP: 002e.2: enabled 1<br>
PNP: 002e.3: enabled 0<br>
PNP: 002e.4: enabled 1<br>
PNP: 002e.5: enabled 0<br>
PNP: 002e.6: enabled 0<br>
PNP: 002e.7: enabled 0<br>
PNP: 002e.8: enabled 0<br>
PNP: 002e.9: enabled 0<br>
PNP: 002e.a: enabled 0<br>
PCI: 00:12.0: enabled 0<br>
PCI: 00:18.1: enabled 1<br>
PCI: 00:18.2: enabled 1<br>
PCI: 00:18.3: enabled 1<br>
scan_static_bus for Root Device<br>
APIC_CLUSTER: 0 enabled<br>
PCI_DOMAIN: 0000 enabled<br>
APIC_CLUSTER: 0 scanning...<br>
PCI: 00:18.3 siblings=0<br>
Found Rev E or Rev F later single core<br>
CPU: APIC: 00 enabled<br>
PCI_DOMAIN: 0000 scanning...<br>
PCI: pci_scan_bus for bus 00<br>
PCI: 00:18.0 [1022/1100] bus ops<br>
PCI: 00:18.0 [1022/1100] enabled<br>
PCI: 00:18.1 [1022/1101] enabled<br>
PCI: 00:18.2 [1022/1102] enabled<br>
PCI: 00:18.3 [1022/1103] ops<br>
PCI: 00:18.3 [1022/1103] enabled<br>
PCI: Using configuration type 1<br>
PCI: 00:00.0 [1106/0351] enabled<br>
Capability: type 0x01 @ 0x50<br>
Capability: type 0x08 @ 0x60<br>
flags: 0x0060<br>
PCI: 00:00.0 count: 0003 static_count: 0013<br>
PCI: 00:00.0 [1106/0351] enabled next_unitid: 0013<br>
PCI: pci_scan_bus for bus 00<br>
PCI: 00:00.0 [1106/0351] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138000<br>
malloc 00138000<br>
PCI: 00:00.1 [1106/1351] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138044<br>
malloc 00138044<br>
PCI: 00:00.2 [1106/2351] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138088<br>
malloc 00138088<br>
PCI: 00:00.3 [1106/3351] enabled<br>
malloc Enter, size 68, free_mem_ptr 001380cc<br>
malloc 001380cc<br>
PCI: 00:00.4 [1106/4351] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138110<br>
malloc 00138110<br>
PCI: 00:00.5 [1106/5351] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138154<br>
malloc 00138154<br>
PCI: 00:00.6 [1106/6238] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138198<br>
malloc 00138198<br>
PCI: 00:00.7 [1106/7351] enabled<br>
malloc Enter, size 68, free_mem_ptr 001381dc<br>
malloc 001381dc<br>
PCI: 00:01.0 [1106/b188] bus ops<br>
B188 device dump<br>
00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02<br>
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00<br>
40: 91 40 00 44 31 3a 88 b1 00 00 00 00 00 00 00 00<br>
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 0e 70 35 00 07 02 00 1f 00 00 00 00 28 00 00 00<br>
90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00<br>
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
b0: bf 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00<br>
c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00<br>
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
PCI: 00:01.0 [1106/b188] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138220<br>
malloc 00138220<br>
PCI: 00:02.0 [1106/a238] bus ops<br>
Configuring PCIe PEG<br>
00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00<br>
40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 18 00<br>
50: 00 00 20 00 60 00 00 00 00 00 00 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 0c 12 c0 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 43 02 27 8a 44 44 44 44 44 44 44 44 00 00 00 00<br>
d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 04 84 50 c2 00 00 00 8f 00 97 00 00 00 00 00<br>
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00<br>
00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00<br>
40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 18 00<br>
50: 00 00 20 00 60 00 00 00 00 00 00 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 7c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 0c f0 c0 81 00 00 03 00 01 00 00 00 00 00 00 00<br>
c0: 43 02 27 8a 44 44 44 44 44 44 44 44 00 00 00 00<br>
d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 0b 84 50 c2 00 00 00 8f 00 97 00 00 00 00 00<br>
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00<br>
PCI: 00:02.0 [1106/a238] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138264<br>
malloc 00138264<br>
PCI: 00:03.0 [1106/c238] bus ops<br>
Configuring PCIe PEXs<br>
00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00<br>
40: 10 68 41 01 c1 0e 00 00 00 00 10 00 41 0c 18 01<br>
50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 43 4a 27 8a 44 44 00 00 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 00 00 22 28 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00<br>
00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00<br>
40: 10 68 41 01 c1 0e 00 00 00 00 10 00 41 0c 18 01<br>
50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 43 4a 27 8a 44 44 00 00 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 0b 00 22 28 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00<br>
PCI: 00:03.0 [1106/c238] enabled<br>
malloc Enter, size 68, free_mem_ptr 001382a8<br>
malloc 001382a8<br>
PCI: 00:03.1 [1106/d238] bus ops<br>
Configuring PCIe PEXs<br>
00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00<br>
40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 02<br>
50: 10 00 00 00 60 00 00 00 00 00 48 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 03 18 00 8a 44 44 44 44 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 0f 00 02 00 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00<br>
00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00<br>
40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 02<br>
50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 03 18 00 8a 44 44 44 44 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00<br>
PCI: 00:03.1 [1106/d238] enabled<br>
malloc Enter, size 68, free_mem_ptr 001382ec<br>
malloc 001382ec<br>
PCI: 00:03.2 [1106/e238] bus ops<br>
Configuring PCIe PEXs<br>
00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00<br>
40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 03<br>
50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 0c 00 02 00 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00<br>
40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 03<br>
50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
PCI: 00:03.2 [1106/e238] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138330<br>
malloc 00138330<br>
PCI: 00:03.3 [1106/f238] bus ops<br>
Configuring PCIe PEXs<br>
00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00<br>
40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 18 04<br>
50: 10 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 09 00 02 00 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00<br>
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00<br>
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00<br>
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00<br>
40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 18 04<br>
50: 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00<br>
60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00<br>
70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00<br>
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00<br>
b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00<br>
c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00<br>
d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8<br>
e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00<br>
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
PCI: 00:03.3 [1106/f238] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138374<br>
malloc 00138374<br>
PCI: 00:0b.0 [102b/0519] enabled<br>
malloc Enter, size 68, free_mem_ptr 001383b8<br>
malloc 001383b8<br>
PCI: 00:0f.0 [1106/0591] enabled<br>
PCI: 00:0f.1 [1106/0571] ops<br>
PCI: 00:0f.1 [1106/0571] enabled<br>
malloc Enter, size 68, free_mem_ptr 001383fc<br>
malloc 001383fc<br>
PCI: 00:10.0 [1106/3038] ops<br>
PCI: 00:10.0 [1106/3038] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138440<br>
malloc 00138440<br>
PCI: 00:10.1 [1106/3038] ops<br>
PCI: 00:10.1 [1106/3038] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138484<br>
malloc 00138484<br>
PCI: 00:10.2 [1106/3038] ops<br>
PCI: 00:10.2 [1106/3038] enabled<br>
malloc Enter, size 68, free_mem_ptr 001384c8<br>
malloc 001384c8<br>
PCI: 00:10.3 [1106/3038] ops<br>
PCI: 00:10.3 [1106/3038] enabled<br>
malloc Enter, size 68, free_mem_ptr 0013850c<br>
malloc 0013850c<br>
PCI: 00:10.4 [1106/3104] ops<br>
PCI: 00:10.4 [1106/3104] enabled<br>
PCI: 00:11.0 [1106/3337] enabled<br>
malloc Enter, size 68, free_mem_ptr 00138550<br>
malloc 00138550<br>
PCI: 00:11.7 [1106/287e] ops<br>
PCI: 00:11.7 [1106/287e] enabled<br>
do_pci_scan_bridge for PCI: 00:01.0<br>
malloc Enter, size 24, free_mem_ptr 00138594<br>
malloc 00138594<br>
PCI: pci_scan_bus for bus 01<br>
PCI: pci_scan_bus returning with max=001<br>
do_pci_scan_bridge returns max 1<br>
do_pci_scan_bridge for PCI: 00:02.0<br>
malloc Enter, size 24, free_mem_ptr 001385ac<br>
malloc 001385ac<br>
PCI: pci_scan_bus for bus 02<br>
[hangs here]<br>
<br>
<br>
Patch so far (mostly copied from a8v-e_se and m2v-mx_se):<br>
<br>
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c<br>
===================================================================<br>
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 5976)<br>
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (working copy)<br>
@@ -142,6 +142,7 @@<br>
device_t dev;<br>
int loops;<br>
<br>
+ print_debug("enable_smbus()\n");<br>
/* Power management controller */<br>
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);<br>
@@ -149,8 +150,13 @@<br>
/* Power management controller */<br>
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);<br>
- if (dev == PCI_DEV_INVALID)<br>
- die("Power management controller not found\n");<br>
+ if (dev == PCI_DEV_INVALID) {<br>
+ /* Power management controller */<br>
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
+ PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);<br>
+ if (dev == PCI_DEV_INVALID)<br>
+ die("Power management controller not found\n");<br>
+ }<br>
}<br>
<br>
/* Make sure the RTC power well is up before touching smbus. */<br>
@@ -242,15 +248,20 @@<br>
if (dev == PCI_DEV_INVALID) {<br>
/* Power management controller */<br>
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
+ PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);<br>
+ }<br>
+ if (dev == PCI_DEV_INVALID) {<br>
+ /* Power management controller */<br>
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);<br>
- if (dev == PCI_DEV_INVALID)<br>
- return;<br>
<br>
devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);<br>
<br>
- if (devctl == PCI_DEV_INVALID)<br>
+ if (devctl == PCI_DEV_INVALID) {<br>
+ print_err("vt8237_sb_enable_fid_vid() failed\n");<br>
return;<br>
+ }<br>
<br>
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */<br>
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);<br>
@@ -297,7 +308,7 @@<br>
if (dev == PCI_DEV_INVALID) {<br>
/* Power management controller */<br>
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
- PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);<br>
+ PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);<br>
if (dev == PCI_DEV_INVALID)<br>
return;<br>
}<br>
@@ -321,7 +332,7 @@<br>
if (dev == PCI_DEV_INVALID) {<br>
/* Power management controller */<br>
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,<br>
- PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);<br>
+ PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);<br>
if (dev == PCI_DEV_INVALID)<br>
die("Power management controller not found\n");<br>
}<br>
Index: src/include/device/pci_ids.h<br>
===================================================================<br>
--- src/include/device/pci_ids.h (revision 5976)<br>
+++ src/include/device/pci_ids.h (working copy)<br>
@@ -1219,6 +1219,7 @@<br>
#define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188<br>
#define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149<br>
#define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227<br>
+#define PCI_DEVICE_ID_VIA_VT8237A_LPC 0x3337<br>
#define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372<br>
#define PCI_DEVICE_ID_VIA_VT8237_SATA 0x5372<br>
#define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e<br>
Index: src/mainboard/asus/Kconfig<br>
===================================================================<br>
--- src/mainboard/asus/Kconfig (revision 5976)<br>
+++ src/mainboard/asus/Kconfig (working copy)<br>
@@ -25,6 +25,8 @@<br>
bool "A8N-E"<br>
config BOARD_ASUS_A8V_E_SE<br>
bool "A8V-E SE"<br>
+config BOARD_ASUS_M2V<br>
+ bool "M2V"<br>
config BOARD_ASUS_M2V_MX_SE<br>
bool "M2V-MX SE"<br>
config BOARD_ASUS_M4A785M<br>
@@ -50,6 +52,7 @@<br>
<br>
source "src/mainboard/asus/a8n_e/Kconfig"<br>
source "src/mainboard/asus/a8v-e_se/Kconfig"<br>
+source "src/mainboard/asus/m2v/Kconfig"<br>
source "src/mainboard/asus/m2v-mx_se/Kconfig"<br>
source "src/mainboard/asus/m4a785-m/Kconfig"<br>
source "src/mainboard/asus/mew-am/Kconfig"<br>
diff -Naru src/mainboard/asus/m2v.none/acpi_tables.c src/mainboard/asus/m2v/acpi_tables.c<br>
--- src/mainboard/asus/m2v.none/acpi_tables.c 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/acpi_tables.c 2010-10-20 19:17:51.000000000 +0200<br>
@@ -0,0 +1,156 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Written by Stefan Reinauer <<a href="mailto:stepan@openbios.org">stepan@openbios.org</a>>.<br>
+ * ACPI FADT, FACS, and DSDT table support added by<br>
+ *<br>
+ * Copyright (C) 2004 Stefan Reinauer <<a href="mailto:stepan@openbios.org">stepan@openbios.org</a>><br>
+ * Copyright (C) 2005 Nick Barker <<a href="mailto:nick.barker9@btinternet.com">nick.barker9@btinternet.com</a>><br>
+ * Copyright (C) 2007 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; version 2 of the License.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+#include <console/console.h><br>
+#include <string.h><br>
+#include <arch/acpi.h><br>
+#include <arch/smp/mpspec.h><br>
+#include <arch/ioapic.h><br>
+#include <device/device.h><br>
+#include <device/pci_ids.h><br>
+#include "southbridge/via/vt8237r/vt8237r.h"<br>
+#include "southbridge/via/k8t890/k8t890.h"<br>
+<br>
+extern const unsigned char AmlCode[];<br>
+<br>
+unsigned long acpi_fill_mcfg(unsigned long current)<br>
+{<br>
+ device_t dev;<br>
+ struct resource *res;<br>
+<br>
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);<br>
+ if (!dev)<br>
+ return current;<br>
+<br>
+ res = find_resource(dev, K8T890_MMCONFIG_MBAR);<br>
+ if (res) {<br>
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)<br>
+ current, res->base, 0x0, 0x0, 0xff);<br>
+ }<br>
+ return current;<br>
+}<br>
+<br>
+unsigned long acpi_fill_madt(unsigned long current)<br>
+{<br>
+ unsigned int gsi_base = 0x18;<br>
+<br>
+ /* Create all subtables for processors. */<br>
+ current = acpi_create_madt_lapics(current);<br>
+<br>
+ /* Write SB IOAPIC. */<br>
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,<br>
+ VT8237R_APIC_ID, IO_APIC_ADDR, 0);<br>
+<br>
+ /* Write NB IOAPIC. */<br>
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,<br>
+ K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);<br>
+<br>
+ /* IRQ9 ACPI active low. */<br>
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);<br>
+<br>
+ /* IRQ0 -> APIC IRQ2. */<br>
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>
+ current, 0, 0, 2, 0x0);<br>
+<br>
+ /* Create all subtables for processors. */<br>
+ current = acpi_create_madt_lapic_nmis(current,<br>
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);<br>
+<br>
+ return current;<br>
+}<br>
+<br>
+unsigned long write_acpi_tables(unsigned long start)<br>
+{<br>
+ unsigned long current;<br>
+ acpi_rsdp_t *rsdp;<br>
+ acpi_srat_t *srat;<br>
+ acpi_rsdt_t *rsdt;<br>
+ acpi_madt_t *madt;<br>
+ acpi_mcfg_t *mcfg;<br>
+ acpi_fadt_t *fadt;<br>
+ acpi_facs_t *facs;<br>
+ acpi_header_t *dsdt;<br>
+<br>
+ /* Align ACPI tables to 16 byte. */<br>
+ start = (start + 0x0f) & -0x10;<br>
+ current = start;<br>
+<br>
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);<br>
+<br>
+ /* We need at least an RSDP and an RSDT table. */<br>
+ rsdp = (acpi_rsdp_t *) current;<br>
+ current += sizeof(acpi_rsdp_t);<br>
+ rsdt = (acpi_rsdt_t *) current;<br>
+ current += sizeof(acpi_rsdt_t);<br>
+<br>
+ /* Clear all table memory. */<br>
+ memset((void *) start, 0, current - start);<br>
+<br>
+ acpi_write_rsdp(rsdp, rsdt, NULL);<br>
+ acpi_write_rsdt(rsdt);<br>
+<br>
+ /* We explicitly add these tables later on: */<br>
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");<br>
+ facs = (acpi_facs_t *) current;<br>
+ current += sizeof(acpi_facs_t);<br>
+ acpi_create_facs(facs);<br>
+<br>
+ dsdt = (acpi_header_t *)current;<br>
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));<br>
+ current += dsdt->length;<br>
+ memcpy(dsdt, &AmlCode, dsdt->length);<br>
+ dsdt->checksum = 0; /* Don't trust iasl to get this right. */<br>
+ dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);<br>
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,<br>
+ dsdt->length);<br>
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");<br>
+<br>
+ fadt = (acpi_fadt_t *) current;<br>
+ current += sizeof(acpi_fadt_t);<br>
+<br>
+ acpi_create_fadt(fadt, facs, dsdt);<br>
+ acpi_add_table(rsdp, fadt);<br>
+<br>
+ /* If we want to use HPET timers Linux wants it in MADT. */<br>
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");<br>
+ madt = (acpi_madt_t *) current;<br>
+ acpi_create_madt(madt);<br>
+ current += madt->header.length;<br>
+ acpi_add_table(rsdp, madt);<br>
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");<br>
+ mcfg = (acpi_mcfg_t *) current;<br>
+ acpi_create_mcfg(mcfg);<br>
+ current += mcfg->header.length;<br>
+ acpi_add_table(rsdp, mcfg);<br>
+<br>
+ printk(BIOS_DEBUG, "ACPI: * SRAT\n");<br>
+ srat = (acpi_srat_t *) current;<br>
+ acpi_create_srat(srat);<br>
+ current += srat->header.length;<br>
+ acpi_add_table(rsdp, srat);<br>
+<br>
+ printk(BIOS_INFO, "ACPI: done.\n");<br>
+ return current;<br>
+}<br>
diff -Naru src/mainboard/asus/m2v.none/chip.h src/mainboard/asus/m2v/chip.h<br>
--- src/mainboard/asus/m2v.none/chip.h 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/chip.h 2010-10-20 19:17:51.000000000 +0200<br>
@@ -0,0 +1,22 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Copyright (C) 2007 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; version 2 of the License.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+extern struct chip_operations mainboard_ops;<br>
+<br>
+struct mainboard_config {};<br>
diff -Naru src/mainboard/asus/m2v.none/cmos.layout src/mainboard/asus/m2v/cmos.layout<br>
--- src/mainboard/asus/m2v.none/cmos.layout 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/cmos.layout 2010-10-20 19:17:51.000000000 +0200<br>
@@ -0,0 +1,98 @@<br>
+entries<br>
+<br>
+#start-bit length config config-ID name<br>
+#0 8 r 0 seconds<br>
+#8 8 r 0 alarm_seconds<br>
+#16 8 r 0 minutes<br>
+#24 8 r 0 alarm_minutes<br>
+#32 8 r 0 hours<br>
+#40 8 r 0 alarm_hours<br>
+#48 8 r 0 day_of_week<br>
+#56 8 r 0 day_of_month<br>
+#64 8 r 0 month<br>
+#72 8 r 0 year<br>
+#80 4 r 0 rate_select<br>
+#84 3 r 0 REF_Clock<br>
+#87 1 r 0 UIP<br>
+#88 1 r 0 auto_switch_DST<br>
+#89 1 r 0 24_hour_mode<br>
+#90 1 r 0 binary_values_enable<br>
+#91 1 r 0 square-wave_out_enable<br>
+#92 1 r 0 update_finished_enable<br>
+#93 1 r 0 alarm_interrupt_enable<br>
+#94 1 r 0 periodic_interrupt_enable<br>
+#95 1 r 0 disable_clock_updates<br>
+#96 288 r 0 temporary_filler<br>
+0 384 r 0 reserved_memory<br>
+384 1 e 4 boot_option<br>
+385 1 e 4 last_boot<br>
+386 1 e 1 ECC_memory<br>
+388 4 r 0 reboot_bits<br>
+392 3 e 5 baud_rate<br>
+395 1 e 1 hw_scrubber<br>
+396 1 e 1 interleave_chip_selects<br>
+397 2 e 8 max_mem_clock<br>
+399 1 e 2 multi_core<br>
+400 1 e 1 power_on_after_fail<br>
+412 4 e 6 debug_level<br>
+416 4 e 7 boot_first<br>
+420 4 e 7 boot_second<br>
+424 4 e 7 boot_third<br>
+428 4 h 0 boot_index<br>
+432 8 h 0 boot_countdown<br>
+440 4 e 9 slow_cpu<br>
+444 1 e 1 nmi<br>
+445 1 e 1 iommu<br>
+728 256 h 0 user_data<br>
+984 16 h 0 check_sum<br>
+# Reserve the extended AMD configuration registers<br>
+1000 24 r 0 amd_reserved<br>
+<br>
+<br>
+<br>
+enumerations<br>
+<br>
+#ID value text<br>
+1 0 Disable<br>
+1 1 Enable<br>
+2 0 Enable<br>
+2 1 Disable<br>
+4 0 Fallback<br>
+4 1 Normal<br>
+5 0 115200<br>
+5 1 57600<br>
+5 2 38400<br>
+5 3 19200<br>
+5 4 9600<br>
+5 5 4800<br>
+5 6 2400<br>
+5 7 1200<br>
+6 6 Notice<br>
+6 7 Info<br>
+6 8 Debug<br>
+6 9 Spew<br>
+7 0 Network<br>
+7 1 HDD<br>
+7 2 Floppy<br>
+7 8 Fallback_Network<br>
+7 9 Fallback_HDD<br>
+7 10 Fallback_Floppy<br>
+#7 3 ROM<br>
+8 0 DDR400<br>
+8 1 DDR333<br>
+8 2 DDR266<br>
+8 3 DDR200<br>
+9 0 off<br>
+9 1 87.5%<br>
+9 2 75.0%<br>
+9 3 62.5%<br>
+9 4 50.0%<br>
+9 5 37.5%<br>
+9 6 25.0%<br>
+9 7 12.5%<br>
+<br>
+checksums<br>
+<br>
+checksum 392 983 984<br>
+<br>
+<br>
diff -Naru src/mainboard/asus/m2v.none/devicetree.cb src/mainboard/asus/m2v/devicetree.cb<br>
--- src/mainboard/asus/m2v.none/devicetree.cb 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/devicetree.cb 2010-10-21 01:50:56.000000000 +0200<br>
@@ -0,0 +1,75 @@<br>
+chip northbridge/amd/amdk8/root_complex # Root complex<br>
+ device lapic_cluster 0 on # APIC cluster<br>
+ chip cpu/amd/socket_AM2 # CPU<br>
+ device lapic 0 on end # APIC<br>
+ end<br>
+ end<br>
+ device pci_domain 0 on # PCI domain<br>
+ chip northbridge/amd/amdk8 # mc0<br>
+ device pci 18.0 on # Northbridge<br>
+ # Devices on link 0, link 0 == LDT 0<br>
+ chip southbridge/via/vt8237r # Southbridge<br>
+ register "ide0_enable" = "1" # Enable IDE channel 0<br>
+ register "ide1_enable" = "1" # Enable IDE channel 1<br>
+ register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0<br>
+ register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1<br>
+ register "fn_ctrl_lo" = "0xc0" # Enable SB functions<br>
+ register "fn_ctrl_hi" = "0x0d" # Enable SB functions<br>
+ device pci 0.0 on end # HT<br>
+ device pci f.1 on end # IDE<br>
+ device pci 11.0 on # LPC<br>
+ chip drivers/generic/generic # DIMM 0-0-0<br>
+ device i2c 50 on end<br>
+ end<br>
+ chip drivers/generic/generic # DIMM 0-0-1<br>
+ device i2c 51 on end<br>
+ end<br>
+ chip drivers/generic/generic # DIMM 0-1-0<br>
+ device i2c 52 on end<br>
+ end<br>
+ chip drivers/generic/generic # DIMM 0-1-1<br>
+ device i2c 53 on end<br>
+ end<br>
+ chip superio/ite/it8712f # Super I/O<br>
+ device pnp 2e.0 on # Floppy<br>
+ io 0x60 = 0x3f0<br>
+ irq 0x70 = 6<br>
+ drq 0x74 = 2<br>
+ end<br>
+ device pnp 2e.1 on # Parallel port<br>
+ io 0x60 = 0x378<br>
+ irq 0x70 = 7<br>
+ drq 0x74 = 3<br>
+ end<br>
+ device pnp 2e.2 on # Com1<br>
+ io 0x60 = 0x3f8<br>
+ irq 0x70 = 4<br>
+ end<br>
+ device pnp 2e.3 off # Com2 (N/A on this board)<br>
+ io 0x60 = 0x2f8<br>
+ irq 0x70 = 3<br>
+ end<br>
+ device pnp 2e.4 on # Environment controller<br>
+ io 0x60 = 0x290<br>
+ io 0x62 = 0x230<br>
+ irq 0x70 = 0x00<br>
+ end<br>
+ device pnp 2e.5 off end # PS/2 keyboard<br>
+ device pnp 2e.6 off end # PS/2 mouse<br>
+ device pnp 2e.7 off end # GPIO config<br>
+ device pnp 2e.8 off end # Midi port<br>
+ device pnp 2e.9 off end # Game port<br>
+ device pnp 2e.a off end # IR<br>
+ end<br>
+ end<br>
+ device pci 12.0 off end # VIA LAN (off, other chip used)<br>
+ end<br>
+ chip southbridge/via/k8t890 # "Southbridge" K8T890<br>
+ end<br>
+ end<br>
+ device pci 18.1 on end<br>
+ device pci 18.2 on end<br>
+ device pci 18.3 on end<br>
+ end<br>
+ end<br>
+end<br>
diff -Naru src/mainboard/asus/m2v.none/dsdt.asl src/mainboard/asus/m2v/dsdt.asl<br>
--- src/mainboard/asus/m2v.none/dsdt.asl 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/dsdt.asl 2010-10-20 19:17:51.000000000 +0200<br>
@@ -0,0 +1,211 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Copyright (C) 2004 Nick Barker <<a href="mailto:Nick.Barker9@btinternet.com">Nick.Barker9@btinternet.com</a>><br>
+ * Copyright (C) 2007 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; version 2 of the License.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+/*<br>
+ * ISA portions taken from QEMU acpi-dsdt.dsl.<br>
+ */<br>
+<br>
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)<br>
+{<br>
+ /* Define the main processor.*/<br>
+ Scope (\_PR)<br>
+ {<br>
+ Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}<br>
+ Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}<br>
+ }<br>
+<br>
+ /* For now only define 2 power states:<br>
+ * - S0 which is fully on<br>
+ * - S5 which is soft off<br>
+ * Any others would involve declaring the wake up methods.<br>
+ */<br>
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })<br>
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })<br>
+<br>
+ /* Root of the bus hierarchy */<br>
+ Scope (\_SB)<br>
+ {<br>
+ /* Top PCI device */<br>
+ Device (PCI0)<br>
+ {<br>
+ Name (_HID, EisaId ("PNP0A03"))<br>
+ Name (_ADR, 0x00)<br>
+ Name (_UID, 0x00)<br>
+ Name (_BBN, 0x00)<br>
+<br>
+ /* PCI Routing Table */<br>
+ /* aaa */<br>
+ Name (_PRT, Package () {<br>
+ Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */<br>
+ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },<br>
+ Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },<br>
+ Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },<br>
+ Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */<br>
+ Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },<br>
+ Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },<br>
+ Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },<br>
+ Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */<br>
+ Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },<br>
+ Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },<br>
+ Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },<br>
+ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */<br>
+ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */<br>
+ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */<br>
+ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },<br>
+ Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },<br>
+ Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },<br>
+ Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */<br>
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */<br>
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },<br>
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },<br>
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },<br>
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */<br>
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */<br>
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */<br>
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */<br>
+ })<br>
+<br>
+ Device (PEGG)<br>
+ {<br>
+ Name (_ADR, 0x00020000)<br>
+ Name (_UID, 0x00)<br>
+ Name (_BBN, 0x02)<br>
+ Name (_PRT, Package () {<br>
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */<br>
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },<br>
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },<br>
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },<br>
+ })<br>
+ }<br>
+<br>
+ Device (PEX0)<br>
+ {<br>
+ Name (_ADR, 0x00030000)<br>
+ Name (_UID, 0x00)<br>
+ Name (_BBN, 0x03)<br>
+ Name (_PRT, Package () {<br>
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */<br>
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },<br>
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },<br>
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },<br>
+ })<br>
+ }<br>
+<br>
+ Device (PEX1)<br>
+ {<br>
+ Name (_ADR, 0x00030001)<br>
+ Name (_UID, 0x00)<br>
+ Name (_BBN, 0x04)<br>
+ Name (_PRT, Package () {<br>
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */<br>
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },<br>
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },<br>
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },<br>
+ })<br>
+ }<br>
+<br>
+ Device (PEX2)<br>
+ {<br>
+ Name (_ADR, 0x00030002)<br>
+ Name (_UID, 0x00)<br>
+ Name (_BBN, 0x05)<br>
+ Name (_PRT, Package () {<br>
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */<br>
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },<br>
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },<br>
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },<br>
+ })<br>
+ }<br>
+<br>
+ Device (PEX3)<br>
+ {<br>
+ Name (_ADR, 0x00030003)<br>
+ Name (_UID, 0x00)<br>
+ Name (_BBN, 0x06)<br>
+ Name (_PRT, Package () {<br>
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */<br>
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },<br>
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },<br>
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },<br>
+ })<br>
+ }<br>
+<br>
+ Device (ISA) {<br>
+ Name (_ADR, 0x00110000)<br>
+<br>
+ /* PS/2 keyboard (seems to be important for WinXP install) */<br>
+ Device (KBD)<br>
+ {<br>
+ Name (_HID, EisaId ("PNP0303"))<br>
+ Method (_STA, 0, NotSerialized)<br>
+ {<br>
+ Return (0x0f)<br>
+ }<br>
+ Method (_CRS, 0, NotSerialized)<br>
+ {<br>
+ Name (TMP, ResourceTemplate () {<br>
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)<br>
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)<br>
+ IRQNoFlags () {1}<br>
+ })<br>
+ Return (TMP)<br>
+ }<br>
+ }<br>
+<br>
+ /* PS/2 mouse */<br>
+ Device (MOU)<br>
+ {<br>
+ Name (_HID, EisaId ("PNP0F13"))<br>
+ Method (_STA, 0, NotSerialized)<br>
+ {<br>
+ Return (0x0f)<br>
+ }<br>
+ Method (_CRS, 0, NotSerialized)<br>
+ {<br>
+ Name (TMP, ResourceTemplate () {<br>
+ IRQNoFlags () {12}<br>
+ })<br>
+ Return (TMP)<br>
+ }<br>
+ }<br>
+<br>
+ /* PS/2 floppy controller */<br>
+ Device (FDC0)<br>
+ {<br>
+ Name (_HID, EisaId ("PNP0700"))<br>
+ Method (_STA, 0, NotSerialized)<br>
+ {<br>
+ Return (0x0f)<br>
+ }<br>
+ Method (_CRS, 0, NotSerialized)<br>
+ {<br>
+ Name (BUF0, ResourceTemplate () {<br>
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)<br>
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)<br>
+ IRQNoFlags () {6}<br>
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}<br>
+ })<br>
+ Return (BUF0)<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+}<br>
diff -Naru src/mainboard/asus/m2v.none/Kconfig src/mainboard/asus/m2v/Kconfig<br>
--- src/mainboard/asus/m2v.none/Kconfig 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/Kconfig 2010-10-20 22:52:31.000000000 +0200<br>
@@ -0,0 +1,79 @@<br>
+if BOARD_ASUS_M2V<br>
+<br>
+config BOARD_SPECIFIC_OPTIONS # dummy<br>
+ def_bool y<br>
+ select ARCH_X86<br>
+ select CPU_AMD_SOCKET_AM2<br>
+ select DIMM_DDR2<br>
+ select K8_HT_FREQ_1G_SUPPORT<br>
+ select NORTHBRIDGE_AMD_AMDK8<br>
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX<br>
+ select SOUTHBRIDGE_VIA_VT8237R<br>
+ select SOUTHBRIDGE_VIA_K8T890<br>
+ select SUPERIO_ITE_IT8712F<br>
+ select CACHE_AS_RAM<br>
+ select HAVE_OPTION_TABLE<br>
+ select HAVE_ACPI_TABLES<br>
+ select HAVE_MP_TABLE<br>
+ select BOARD_ROMSIZE_KB_512<br>
+ select RAMINIT_SYSINFO<br>
+ select TINY_BOOTBLOCK<br>
+# select HAVE_MAINBOARD_RESOURCES<br>
+<br>
+config MAINBOARD_DIR<br>
+ string<br>
+ default asus/m2v<br>
+<br>
+config DCACHE_RAM_BASE<br>
+ hex<br>
+ default 0xcc000<br>
+<br>
+config DCACHE_RAM_SIZE<br>
+ hex<br>
+ default 0x4000<br>
+<br>
+config DCACHE_RAM_GLOBAL_VAR_SIZE<br>
+ hex<br>
+ default 0x1000<br>
+<br>
+config APIC_ID_OFFSET<br>
+ hex<br>
+ default 0x10<br>
+<br>
+config SB_HT_CHAIN_ON_BUS0<br>
+ int<br>
+ default 1<br>
+<br>
+config MAINBOARD_PART_NUMBER<br>
+ string<br>
+ default "M2V"<br>
+<br>
+config HW_MEM_HOLE_SIZEK<br>
+ hex<br>
+ default 0<br>
+<br>
+config MAX_CPUS<br>
+ int<br>
+ default 2<br>
+<br>
+config MAX_PHYSICAL_CPUS<br>
+ int<br>
+ default 1<br>
+<br>
+config HEAP_SIZE<br>
+ hex<br>
+ default 0x40000<br>
+<br>
+config HT_CHAIN_END_UNITID_BASE<br>
+ hex<br>
+ default 0x20<br>
+<br>
+config HT_CHAIN_UNITID_BASE<br>
+ hex<br>
+ default 0x0<br>
+<br>
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>
+ hex<br>
+ default 0x1043<br>
+<br>
+endif # BOARD_ASUS_M2V<br>
diff -Naru src/mainboard/asus/m2v.none/mainboard.c src/mainboard/asus/m2v/mainboard.c<br>
--- src/mainboard/asus/m2v.none/mainboard.c 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/mainboard.c 2010-10-20 19:57:44.000000000 +0200<br>
@@ -0,0 +1,28 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Copyright (C) 2007 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; version 2 of the License.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+#include <console/console.h><br>
+#include <device/device.h><br>
+#include <device/pci.h><br>
+#include <device/pci_ids.h><br>
+#include "chip.h"<br>
+<br>
+struct chip_operations mainboard_ops = {<br>
+ CHIP_NAME("ASUS M2V Mainboard")<br>
+};<br>
diff -Naru src/mainboard/asus/m2v.none/mptable.c src/mainboard/asus/m2v/mptable.c<br>
--- src/mainboard/asus/m2v.none/mptable.c 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/mptable.c 2010-10-20 19:57:57.000000000 +0200<br>
@@ -0,0 +1,146 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Copyright (C) 2007 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; version 2 of the License.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+#include <string.h><br>
+#include <stdint.h><br>
+#include <arch/smp/mpspec.h><br>
+#include <arch/ioapic.h><br>
+#include "southbridge/via/vt8237r/vt8237r.h"<br>
+#include "southbridge/via/k8t890/k8t890.h"<br>
+<br>
+static void *smp_write_config_table(void *v)<br>
+{<br>
+ static const char sig[4] = "PCMP";<br>
+ static const char oem[8] = "COREBOOT";<br>
+ static const char productid[12] = "M2V ";<br>
+ struct mp_config_table *mc;<br>
+ int bus_isa = 42;<br>
+<br>
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);<br>
+ memset(mc, 0, sizeof(*mc));<br>
+<br>
+ memcpy(mc->mpc_signature, sig, sizeof(sig));<br>
+ mc->mpc_length = sizeof(*mc); /* Initially just the header. */<br>
+ mc->mpc_spec = 0x04;<br>
+ mc->mpc_checksum = 0; /* Not yet computed. */<br>
+ memcpy(mc->mpc_oem, oem, sizeof(oem));<br>
+ memcpy(mc->mpc_productid, productid, sizeof(productid));<br>
+ mc->mpc_oemptr = 0;<br>
+ mc->mpc_oemsize = 0;<br>
+ mc->mpc_entry_count = 0; /* No entries yet. */<br>
+ mc->mpc_lapic = LAPIC_ADDR;<br>
+ mc->mpe_length = 0;<br>
+ mc->mpe_checksum = 0;<br>
+ mc->reserved = 0;<br>
+<br>
+ smp_write_processors(mc);<br>
+<br>
+<br>
+ /* Bus: Bus ID Type */<br>
+ smp_write_bus(mc, 0, "PCI ");<br>
+ smp_write_bus(mc, 1, "PCI ");<br>
+ smp_write_bus(mc, 2, "PCI ");<br>
+ smp_write_bus(mc, 3, "PCI ");<br>
+ smp_write_bus(mc, 4, "PCI ");<br>
+ smp_write_bus(mc, 5, "PCI ");<br>
+ smp_write_bus(mc, 6, "PCI ");<br>
+ smp_write_bus(mc, bus_isa, "ISA ");<br>
+<br>
+ /* I/O APICs: APIC ID Version State Address */<br>
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);<br>
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);<br>
+<br>
+ mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);<br>
+<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);<br>
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);<br>
+<br>
+ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br>
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);<br>
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);<br>
+ /* There is no extension information... */<br>
+<br>
+ /* Compute the checksums. */<br>
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),<br>
+ mc->mpe_length);<br>
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);<br>
+<br>
+ return smp_next_mpe_entry(mc);<br>
+}<br>
+<br>
+unsigned long write_smp_table(unsigned long addr)<br>
+{<br>
+ void *v;<br>
+ v = smp_write_floating_table(addr);<br>
+ return (unsigned long)smp_write_config_table(v);<br>
+}<br>
diff -Naru src/mainboard/asus/m2v.none/romstage_a8v-e_se.c src/mainboard/asus/m2v/romstage_a8v-e_se.c<br>
--- src/mainboard/asus/m2v.none/romstage_a8v-e_se.c 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/romstage_a8v-e_se.c 2010-10-20 20:43:06.000000000 +0200<br>
@@ -0,0 +1,244 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Copyright (C) 2006 AMD<br>
+ * (Written by Yinghai Lu <<a href="mailto:yinghailu@amd.com">yinghailu@amd.com</a>> for AMD)<br>
+ * Copyright (C) 2006 MSI<br>
+ * (Written by Bingxun Shi <<a href="mailto:bingxunshi@gmail.com">bingxunshi@gmail.com</a>> for MSI)<br>
+ * Copyright (C) 2007 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+unsigned int get_sbdn(unsigned bus);<br>
+<br>
+/* Used by raminit. */<br>
+#define QRANK_DIMM_SUPPORT 1<br>
+<br>
+/* Used by init_cpus and fidvid */<br>
+#define SET_FIDVID 1<br>
+<br>
+/* If we want to wait for core1 done before DQS training, set it to 0. */<br>
+#define SET_FIDVID_CORE0_ONLY 1<br>
+<br>
+#include <stdint.h><br>
+#include <string.h><br>
+#include <device/pci_def.h><br>
+#include <arch/io.h><br>
+#include <device/pnp_def.h><br>
+#include <arch/romcc_io.h><br>
+#include <cpu/x86/lapic.h><br>
+#include <pc80/mc146818rtc.h><br>
+#include <console/console.h><br>
+#include <cpu/amd/model_fxx_rev.h><br>
+#include "northbridge/amd/amdk8/raminit.h"<br>
+#include "cpu/amd/model_fxx/apic_timer.c"<br>
+#include "lib/delay.c"<br>
+#include "cpu/x86/lapic/boot_cpu.c"<br>
+#include "northbridge/amd/amdk8/reset_test.c"<br>
+#include "northbridge/amd/amdk8/early_ht.c"<br>
+#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"<br>
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"<br>
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */<br>
+#include "cpu/x86/mtrr/earlymtrr.c"<br>
+#include "cpu/x86/bist.h"<br>
+#include "northbridge/amd/amdk8/setup_resource_map.c"<br>
+<br>
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)<br>
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)<br>
+#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)<br>
+#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)<br>
+<br>
+static void memreset(int controllers, const struct mem_controller *ctrl)<br>
+{<br>
+}<br>
+<br>
+static inline int spd_read_byte(unsigned device, unsigned address)<br>
+{<br>
+ return smbus_read_byte(device, address);<br>
+}<br>
+<br>
+static void activate_spd_rom(const struct mem_controller *ctrl)<br>
+{<br>
+}<br>
+<br>
+#include <reset.h><br>
+void soft_reset(void)<br>
+{<br>
+ uint8_t tmp;<br>
+<br>
+ set_bios_reset();<br>
+ print_debug("soft reset \n");<br>
+<br>
+ /* PCI reset */<br>
+ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);<br>
+ tmp |= 0x01;<br>
+ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);<br>
+<br>
+ while (1) {<br>
+ /* daisy daisy ... */<br>
+ hlt();<br>
+ }<br>
+}<br>
+<br>
+// defines S3_NVRAM_EARLY:<br>
+#include "southbridge/via/k8t890/k8t890_early_car.c"<br>
+<br>
+#include "northbridge/amd/amdk8/amdk8.h"<br>
+#include "northbridge/amd/amdk8/incoherent_ht.c"<br>
+#include "northbridge/amd/amdk8/coherent_ht.c"<br>
+#include "northbridge/amd/amdk8/raminit.c"<br>
+#include "lib/generic_sdram.c"<br>
+<br>
+#include "cpu/amd/dualcore/dualcore.c"<br>
+<br>
+#include "cpu/amd/car/post_cache_as_ram.c"<br>
+#include "cpu/amd/model_fxx/init_cpus.c"<br>
+#include "cpu/amd/model_fxx/fidvid.c"<br>
+#include "northbridge/amd/amdk8/resourcemap.c"<br>
+<br>
+unsigned int get_sbdn(unsigned bus)<br>
+{<br>
+ device_t dev;<br>
+<br>
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,<br>
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);<br>
+ return (dev >> 15) & 0x1f;<br>
+}<br>
+<br>
+static void sio_init(void)<br>
+{<br>
+ u8 reg;<br>
+<br>
+ pnp_enter_ext_func_mode(SERIAL_DEV);<br>
+ /* We have 24MHz input. */<br>
+ reg = pnp_read_config(SERIAL_DEV, 0x24);<br>
+ pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));<br>
+ /* We have GPIO for KB/MS pin. */<br>
+ reg = pnp_read_config(SERIAL_DEV, 0x2a);<br>
+ pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));<br>
+ /* We have all RESTOUT and even some reserved bits, too. */<br>
+ reg = pnp_read_config(SERIAL_DEV, 0x2c);<br>
+ pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));<br>
+ pnp_exit_ext_func_mode(SERIAL_DEV);<br>
+<br>
+ pnp_enter_ext_func_mode(ACPI_DEV);<br>
+ pnp_set_logical_device(ACPI_DEV);<br>
+ /*<br>
+ * Set the delay rising time from PWROK_LP to PWROK_ST to<br>
+ * 300 - 600ms, and 0 to vice versa.<br>
+ */<br>
+ reg = pnp_read_config(ACPI_DEV, 0xe6);<br>
+ pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));<br>
+ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */<br>
+ reg = pnp_read_config(ACPI_DEV, 0xe4);<br>
+ pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));<br>
+ pnp_exit_ext_func_mode(ACPI_DEV);<br>
+<br>
+ pnp_enter_ext_func_mode(GPIO_DEV);<br>
+ pnp_set_logical_device(GPIO_DEV);<br>
+ /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */<br>
+ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */<br>
+ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */<br>
+ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */<br>
+ pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */<br>
+ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */<br>
+ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */<br>
+ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */<br>
+ pnp_exit_ext_func_mode(GPIO_DEV);<br>
+}<br>
+<br>
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)<br>
+{<br>
+ static const uint16_t spd_addr[] = {<br>
+ // Node 0<br>
+ (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,<br>
+ (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,<br>
+ // Node 1<br>
+ (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,<br>
+ (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,<br>
+ };<br>
+ unsigned bsp_apicid = 0;<br>
+ int needs_reset = 0;<br>
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE<br>
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);<br>
+<br>
+ sio_init();<br>
+ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>
+ uart_init();<br>
+ console_init();<br>
+ enable_rom_decode();<br>
+<br>
+ print_info("now booting... fallback\n");<br>
+<br>
+ /* Is this a CPU only reset? Or is this a secondary CPU? */<br>
+ if (!cpu_init_detectedx && boot_cpu()) {<br>
+ /* Nothing special needs to be done to find bus 0. */<br>
+ /* Allow the HT devices to be found. */<br>
+ enumerate_ht_chain();<br>
+ }<br>
+<br>
+ sio_init();<br>
+ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>
+ uart_init();<br>
+ console_init();<br>
+ enable_rom_decode();<br>
+<br>
+ print_info("now booting... real_main\n");<br>
+<br>
+ if (bist == 0)<br>
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<br>
+<br>
+ /* Halt if there was a built in self test failure. */<br>
+ report_bist_failure(bist);<br>
+<br>
+ setup_default_resource_map();<br>
+ setup_coherent_ht_domain();<br>
+ wait_all_core0_started();<br>
+<br>
+ print_info("now booting... Core0 started\n");<br>
+<br>
+#if CONFIG_LOGICAL_CPUS==1<br>
+ /* It is said that we should start core1 after all core0 launched. */<br>
+ start_other_cores();<br>
+ wait_all_other_cores_started(bsp_apicid);<br>
+#endif<br>
+ init_timer();<br>
+ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */<br>
+<br>
+ needs_reset = optimize_link_coherent_ht();<br>
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);<br>
+ needs_reset |= k8t890_early_setup_ht();<br>
+<br>
+ if (needs_reset) {<br>
+ print_debug("ht reset -\n");<br>
+ soft_reset();<br>
+ }<br>
+<br>
+ /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */<br>
+ enable_fid_change();<br>
+ init_fidvid_bsp(bsp_apicid);<br>
+<br>
+ /* Stop the APs so we can start them later in init. */<br>
+ allow_all_aps_stop(bsp_apicid);<br>
+<br>
+ /* It's the time to set ctrl now. */<br>
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);<br>
+<br>
+ enable_smbus();<br>
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);<br>
+ post_cache_as_ram();<br>
+}<br>
+<br>
diff -Naru src/mainboard/asus/m2v.none/romstage.c src/mainboard/asus/m2v/romstage.c<br>
--- src/mainboard/asus/m2v.none/romstage.c 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/romstage.c 2010-10-20 22:58:40.000000000 +0200<br>
@@ -0,0 +1,210 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Copyright (C) 2006 AMD<br>
+ * (Written by Yinghai Lu <<a href="mailto:yinghailu@amd.com">yinghailu@amd.com</a>> for AMD)<br>
+ * Copyright (C) 2006 MSI<br>
+ * (Written by Bingxun Shi <<a href="mailto:bingxunshi@gmail.com">bingxunshi@gmail.com</a>> for MSI)<br>
+ * Copyright (C) 2008 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+unsigned int get_sbdn(unsigned bus);<br>
+<br>
+/* Used by raminit. */<br>
+#define QRANK_DIMM_SUPPORT 1<br>
+<br>
+/* Used by init_cpus and fidvid */<br>
+#define SET_FIDVID 1<br>
+<br>
+/* If we want to wait for core1 done before DQS training, set it to 0. */<br>
+#define SET_FIDVID_CORE0_ONLY 1<br>
+<br>
+#if CONFIG_K8_REV_F_SUPPORT == 1<br>
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0<br>
+#endif<br>
+<br>
+#include <stdint.h><br>
+#include <string.h><br>
+#include <device/pci_def.h><br>
+#include <arch/io.h><br>
+#include <device/pnp_def.h><br>
+#include <arch/romcc_io.h><br>
+#include <cpu/amd/mtrr.h><br>
+#include <cpu/x86/lapic.h><br>
+#include <pc80/mc146818rtc.h><br>
+#include <console/console.h><br>
+#include <cpu/amd/model_fxx_rev.h><br>
+#include "northbridge/amd/amdk8/raminit.h"<br>
+#include "cpu/amd/model_fxx/apic_timer.c"<br>
+#include "lib/delay.c"<br>
+#include "northbridge/amd/amdk8/reset_test.c"<br>
+#include "northbridge/amd/amdk8/debug.c"<br>
+#include "superio/ite/it8712f/it8712f_early_serial.c"<br>
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"<br>
+#include "cpu/x86/mtrr/earlymtrr.c"<br>
+#include "cpu/x86/bist.h"<br>
+#include "northbridge/amd/amdk8/setup_resource_map.c"<br>
+<br>
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)<br>
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)<br>
+<br>
+static void memreset(int controllers, const struct mem_controller *ctrl)<br>
+{<br>
+}<br>
+<br>
+static inline int spd_read_byte(unsigned device, unsigned address)<br>
+{<br>
+ return smbus_read_byte(device, address);<br>
+}<br>
+<br>
+static void activate_spd_rom(const struct mem_controller *ctrl)<br>
+{<br>
+}<br>
+<br>
+// defines S3_NVRAM_EARLY:<br>
+#include "southbridge/via/k8t890/k8t890_early_car.c"<br>
+<br>
+#include "northbridge/amd/amdk8/amdk8.h"<br>
+#include "northbridge/amd/amdk8/incoherent_ht.c"<br>
+#include "northbridge/amd/amdk8/coherent_ht.c"<br>
+#include "northbridge/amd/amdk8/raminit_f.c"<br>
+#include "lib/generic_sdram.c"<br>
+<br>
+#include "cpu/amd/dualcore/dualcore.c"<br>
+<br>
+#include "cpu/amd/car/post_cache_as_ram.c"<br>
+#include "cpu/amd/model_fxx/init_cpus.c"<br>
+<br>
+#define SB_VFSMAF 0<br>
+<br>
+/* this function might fail on some K8 CPUs with errata #181 */<br>
+static void ldtstop_sb(void)<br>
+{<br>
+ print_debug("toggle LDTSTP#\n");<br>
+ u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);<br>
+ reg = reg ^ (1 << 0);<br>
+ outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);<br>
+ reg = inb(VT8237R_ACPI_IO_BASE + 0x15);<br>
+ print_debug("done\n");<br>
+}<br>
+<br>
+#include "cpu/amd/model_fxx/fidvid.c"<br>
+#include "northbridge/amd/amdk8/resourcemap.c"<br>
+<br>
+void soft_reset(void)<br>
+{<br>
+ uint8_t tmp;<br>
+<br>
+ set_bios_reset();<br>
+ print_debug("soft reset \n");<br>
+<br>
+ /* PCI reset */<br>
+ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);<br>
+ tmp |= 0x01;<br>
+ /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */<br>
+ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);<br>
+<br>
+ while (1) {<br>
+ /* daisy daisy ... */<br>
+ hlt();<br>
+ }<br>
+}<br>
+<br>
+unsigned int get_sbdn(unsigned bus)<br>
+{<br>
+ device_t dev;<br>
+<br>
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,<br>
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);<br>
+ return (dev >> 15) & 0x1f;<br>
+}<br>
+<br>
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)<br>
+{<br>
+ static const uint16_t spd_addr[] = {<br>
+ // Node 0<br>
+ (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,<br>
+ (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,<br>
+ // Node 1<br>
+ (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,<br>
+ (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,<br>
+ };<br>
+ unsigned bsp_apicid = 0;<br>
+ int needs_reset = 0;<br>
+ struct sys_info *sysinfo =<br>
+ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);<br>
+<br>
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>
+ it8712f_kill_watchdog();<br>
+ it8712f_enable_3vsbsw();<br>
+ uart_init();<br>
+ console_init();<br>
+ enable_rom_decode();<br>
+<br>
+ printk(BIOS_INFO, "now booting... \n");<br>
+<br>
+ if (bist == 0)<br>
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<br>
+<br>
+ /* Halt if there was a built in self test failure. */<br>
+ report_bist_failure(bist);<br>
+ setup_default_resource_map();<br>
+ setup_coherent_ht_domain();<br>
+ wait_all_core0_started();<br>
+<br>
+ printk(BIOS_INFO, "now booting... All core 0 started\n");<br>
+<br>
+#if CONFIG_LOGICAL_CPUS==1<br>
+ /* It is said that we should start core1 after all core0 launched. */<br>
+ start_other_cores();<br>
+ wait_all_other_cores_started(bsp_apicid);<br>
+#endif<br>
+ init_timer();<br>
+ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */<br>
+<br>
+ needs_reset = optimize_link_coherent_ht();<br>
+ print_debug_hex8(needs_reset);<br>
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);<br>
+ print_debug_hex8(needs_reset);<br>
+ needs_reset |= k8t890_early_setup_ht();<br>
+ print_debug_hex8(needs_reset);<br>
+<br>
+ if (needs_reset) {<br>
+ printk(BIOS_DEBUG, "ht reset -\n");<br>
+ soft_reset();<br>
+ printk(BIOS_DEBUG, "FAILED!\n");<br>
+ }<br>
+<br>
+ /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */<br>
+ /* allow LDT STOP asserts */<br>
+ vt8237_sb_enable_fid_vid();<br>
+<br>
+ enable_fid_change();<br>
+ print_debug("after enable_fid_change\n");<br>
+<br>
+ init_fidvid_bsp(bsp_apicid);<br>
+<br>
+ /* Stop the APs so we can start them later in init. */<br>
+ allow_all_aps_stop(bsp_apicid);<br>
+<br>
+ /* It's the time to set ctrl now. */<br>
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);<br>
+ enable_smbus();<br>
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);<br>
+ post_cache_as_ram();<br>
+}<br>
+<br>
diff -Naru src/mainboard/asus/m2v.none/romstage_m2v-mx_se.c src/mainboard/asus/m2v/romstage_m2v-mx_se.c<br>
--- src/mainboard/asus/m2v.none/romstage_m2v-mx_se.c 1970-01-01 01:00:00.000000000 +0100<br>
+++ src/mainboard/asus/m2v/romstage_m2v-mx_se.c 2010-10-20 20:43:15.000000000 +0200<br>
@@ -0,0 +1,213 @@<br>
+/*<br>
+ * This file is part of the coreboot project.<br>
+ *<br>
+ * Copyright (C) 2006 AMD<br>
+ * (Written by Yinghai Lu <<a href="mailto:yinghailu@amd.com">yinghailu@amd.com</a>> for AMD)<br>
+ * Copyright (C) 2006 MSI<br>
+ * (Written by Bingxun Shi <<a href="mailto:bingxunshi@gmail.com">bingxunshi@gmail.com</a>> for MSI)<br>
+ * Copyright (C) 2008 Rudolf Marek <<a href="mailto:r.marek@assembler.cz">r.marek@assembler.cz</a>><br>
+ *<br>
+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License as published by<br>
+ * the Free Software Foundation; either version 2 of the License, or<br>
+ * (at your option) any later version.<br>
+ *<br>
+ * This program is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
+ * GNU General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU General Public License<br>
+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
+ */<br>
+<br>
+unsigned int get_sbdn(unsigned bus);<br>
+<br>
+/* Used by raminit. */<br>
+#define QRANK_DIMM_SUPPORT 1<br>
+<br>
+/* Used by init_cpus and fidvid */<br>
+#define SET_FIDVID 1<br>
+<br>
+/* If we want to wait for core1 done before DQS training, set it to 0. */<br>
+#define SET_FIDVID_CORE0_ONLY 1<br>
+<br>
+#if CONFIG_K8_REV_F_SUPPORT == 1<br>
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0<br>
+#endif<br>
+<br>
+#include <stdint.h><br>
+#include <string.h><br>
+#include <device/pci_def.h><br>
+#include <arch/io.h><br>
+#include <device/pnp_def.h><br>
+#include <arch/romcc_io.h><br>
+#include <cpu/amd/mtrr.h><br>
+#include <cpu/x86/lapic.h><br>
+#include <pc80/mc146818rtc.h><br>
+#include <console/console.h><br>
+#include <cpu/amd/model_fxx_rev.h><br>
+#include "northbridge/amd/amdk8/raminit.h"<br>
+#include "cpu/amd/model_fxx/apic_timer.c"<br>
+#include "lib/delay.c"<br>
+#include "northbridge/amd/amdk8/reset_test.c"<br>
+#include "northbridge/amd/amdk8/debug.c"<br>
+#include "superio/ite/it8712f/it8712f_early_serial.c"<br>
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"<br>
+#include "cpu/x86/mtrr/earlymtrr.c"<br>
+#include "cpu/x86/bist.h"<br>
+#include "northbridge/amd/amdk8/setup_resource_map.c"<br>
+<br>
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)<br>
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)<br>
+<br>
+static void memreset(int controllers, const struct mem_controller *ctrl)<br>
+{<br>
+}<br>
+<br>
+static inline int spd_read_byte(unsigned device, unsigned address)<br>
+{<br>
+ return smbus_read_byte(device, address);<br>
+}<br>
+<br>
+static void activate_spd_rom(const struct mem_controller *ctrl)<br>
+{<br>
+}<br>
+<br>
+// defines S3_NVRAM_EARLY:<br>
+#include "southbridge/via/k8t890/k8t890_early_car.c"<br>
+<br>
+#include "northbridge/amd/amdk8/amdk8.h"<br>
+#include "northbridge/amd/amdk8/incoherent_ht.c"<br>
+#include "northbridge/amd/amdk8/coherent_ht.c"<br>
+#include "northbridge/amd/amdk8/raminit_f.c"<br>
+#include "lib/generic_sdram.c"<br>
+<br>
+#include "cpu/amd/dualcore/dualcore.c"<br>
+<br>
+#include "cpu/amd/car/post_cache_as_ram.c"<br>
+#include "cpu/amd/model_fxx/init_cpus.c"<br>
+<br>
+#define SB_VFSMAF 0<br>
+<br>
+/* this function might fail on some K8 CPUs with errata #181 */<br>
+static void ldtstop_sb(void)<br>
+{<br>
+ print_debug("toggle LDTSTP#\n");<br>
+ u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);<br>
+ reg = reg ^ (1 << 0);<br>
+ outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);<br>
+ reg = inb(VT8237R_ACPI_IO_BASE + 0x15);<br>
+ print_debug("done\n");<br>
+}<br>
+<br>
+#include "cpu/amd/model_fxx/fidvid.c"<br>
+#include "northbridge/amd/amdk8/resourcemap.c"<br>
+<br>
+void soft_reset(void)<br>
+{<br>
+ uint8_t tmp;<br>
+<br>
+ set_bios_reset();<br>
+ print_debug("soft reset \n");<br>
+<br>
+ /* PCI reset */<br>
+ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);<br>
+ tmp |= 0x01;<br>
+ /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */<br>
+ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);<br>
+<br>
+ while (1) {<br>
+ /* daisy daisy ... */<br>
+ hlt();<br>
+ }<br>
+}<br>
+<br>
+unsigned int get_sbdn(unsigned bus)<br>
+{<br>
+ device_t dev;<br>
+<br>
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,<br>
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);<br>
+ return (dev >> 15) & 0x1f;<br>
+}<br>
+<br>
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)<br>
+{<br>
+ static const uint16_t spd_addr[] = {<br>
+ // Node 0<br>
+ (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,<br>
+ (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,<br>
+ // Node 1<br>
+ (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,<br>
+ (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,<br>
+ };<br>
+ unsigned bsp_apicid = 0;<br>
+ int needs_reset = 0;<br>
+ struct sys_info *sysinfo =<br>
+ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);<br>
+<br>
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>
+ it8712f_kill_watchdog();<br>
+ it8712f_enable_3vsbsw();<br>
+ uart_init();<br>
+ console_init();<br>
+ enable_rom_decode();<br>
+<br>
+ printk(BIOS_INFO, "now booting... \n");<br>
+<br>
+ if (bist == 0)<br>
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<br>
+<br>
+ /* Halt if there was a built in self test failure. */<br>
+ report_bist_failure(bist);<br>
+ setup_default_resource_map();<br>
+ setup_coherent_ht_domain();<br>
+ wait_all_core0_started();<br>
+<br>
+ printk(BIOS_INFO, "now booting... All core 0 started\n");<br>
+<br>
+#if CONFIG_LOGICAL_CPUS==1<br>
+ /* It is said that we should start core1 after all core0 launched. */<br>
+ start_other_cores();<br>
+ wait_all_other_cores_started(bsp_apicid);<br>
+#endif<br>
+ init_timer();<br>
+ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */<br>
+<br>
+ needs_reset = optimize_link_coherent_ht();<br>
+ print_debug_hex8(needs_reset);<br>
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);<br>
+ print_debug_hex8(needs_reset);<br>
+ needs_reset |= k8t890_early_setup_ht();<br>
+ print_debug_hex8(needs_reset);<br>
+<br>
+ vt8237_early_network_init(NULL);<br>
+ vt8237_early_spi_init();<br>
+<br>
+ if (needs_reset) {<br>
+ printk(BIOS_DEBUG, "ht reset -\n");<br>
+ soft_reset();<br>
+ printk(BIOS_DEBUG, "FAILED!\n");<br>
+ }<br>
+<br>
+ /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */<br>
+ /* allow LDT STOP asserts */<br>
+ vt8237_sb_enable_fid_vid();<br>
+<br>
+ enable_fid_change();<br>
+ print_debug("after enable_fid_change\n");<br>
+<br>
+ init_fidvid_bsp(bsp_apicid);<br>
+<br>
+ /* Stop the APs so we can start them later in init. */<br>
+ allow_all_aps_stop(bsp_apicid);<br>
+<br>
+ /* It's the time to set ctrl now. */<br>
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);<br>
+ enable_smbus();<br>
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);<br>
+ post_cache_as_ram();<br>
+}<br>
+<br>
<br>
<br>
<br>
--<br>
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<font color="#888888"><br>
--<br>
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</font></blockquote></div><br><br clear="all"><br>-- <br>Wang Qing Pei <br>Phone: 86+18930528086<br>
</div>