<div class="gmail_quote">2010/11/4 Nils <span dir="ltr"><<a href="mailto:njacobs8@hetnet.nl">njacobs8@hetnet.nl</a>></span><br><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
Remove banner wrapper function and unify print(k).<br></blockquote><div><br><blockquote style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;" class="gmail_quote">Index: src/northbridge/amd/gx2/raminit.c<br>
===================================================================<br>--- src/northbridge/amd/gx2/raminit.c (revision 6017)<br>+++ src/northbridge/amd/gx2/raminit.c (working copy)<br>@@ -26,20 +26,15 @@<br> 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,<br>
};<br> <br>-static void banner(const char *s)<br>-{<br>- printk(BIOS_DEBUG, " * %s\n", s);<br>-}<br>-<br> static void hcf(void)<br> {<br>- print_emerg("DIE\n");<br>+ printk(BIOS_EMERG, "DIE\n");<br>
/* this guarantees we flush the UART fifos (if any) and also<br> * ensures that things, in general, keep going so no debug output<br> * is lost<br> */<br> while (1)<br>- print_emerg_char(0);<br>
+ printk(BIOS_EMERG, (0));<br> }<br> <br> static void auto_size_dimm(unsigned int dimm)<br>@@ -51,35 +46,35 @@<br> <br> dimm_setting = 0;<br> <br>- banner("Check present");<br>+ printk(BIOS_DEBUG, "Check present\n");<br>
/* Check that we have a dimm */<br> if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {<br> return;<br> }<br> <br>- banner("MODBANKS");<br>+ printk(BIOS_DEBUG, "MODBANKS\n");<br>
/* Field: Module Banks per DIMM */<br> /* EEPROM byte usage: (5) Number of DIMM Banks */<br> spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);<br> if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {<br>
- print_emerg("Number of module banks not compatible\n");<br>+ printk(BIOS_EMERG, "Number of module banks not compatible\n");<br> post_code(ERROR_BANK_SET);<br> hcf();<br>
}<br> dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;<br>- banner("FIELDBANKS");<br> <br>+ printk(BIOS_DEBUG, "FIELDBANKS\n");<br> /* Field: Banks per SDRAM device */<br>
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */<br> spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);<br> if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {<br>- print_emerg("Number of device banks not compatible\n");<br>
+ printk(BIOS_EMERG, "Number of device banks not compatible\n");<br> post_code(ERROR_BANK_SET);<br> hcf();<br> }<br> dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;<br>
- banner("SPDNUMROWS");<br> <br>+ printk(BIOS_DEBUG, "SPDNUMROWS\n");<br> /* Field: DIMM size<br> * EEPROM byte usage:<br> * (3) Number of Row Addresses<br>@@ -90,29 +85,29 @@<br>
*/<br> if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)<br> || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {<br>- print_emerg("Assymetirc DIMM not compatible\n");<br>+ printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");<br>
</blockquote><div><br>"Asymmetric"<br> </div><blockquote style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;" class="gmail_quote"> post_code(ERROR_UNSUPPORTED_DIMM);<br>
hcf();<br> }<br>- banner("SPDBANKDENSITY");<br> <br>+ printk(BIOS_DEBUG, "SPDBANKDENSITY\n");<br> dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);<br>- banner("DIMMSIZE");<br>
+ printk(BIOS_DEBUG, "DIMMSIZE\n");<br> dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */<br> dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */<br>
<br> /* Module Density * Module Banks */<br> dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */<br>- banner("BEFORT CTZ");<br>+ printk(BIOS_DEBUG, "BEFORT CTZ\n");<br>
dimm_size = __builtin_ctz(dimm_size);<br>- banner("TEST DIMM SIZE>7");<br>+ printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n");<br> if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */<br>
- print_emerg("Only support up to 512MB per DIMM\n");<br>+ printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");<br> post_code(ERROR_DENSITY_DIMM);<br> hcf();<br> }<br>
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;<br>- banner("PAGESIZE");<br>+ printk(BIOS_DEBUG, "PAGESIZE\n");<br> <br> /*<br> * Field: PAGE size<br>@@ -142,22 +137,22 @@<br> */<br>
<br> spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];<br>- banner("MAXCOLADDR");<br>+ printk(BIOS_DEBUG, "MAXCOLADDR\n");<br> if (spd_byte > MAX_COL_ADDR) {<br>- print_emerg("DIMM page size not compatible\n");<br>
+ printk(BIOS_EMERG, "DIMM page size not compatible\n");<br> post_code(ERROR_SET_PAGE);<br> hcf();<br> }<br>- banner(">11address test");<br>+ printk(BIOS_DEBUG, ">11address test\n");<br>
spd_byte -= 7;<br> if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */<br> spd_byte = 7; /* which means >16k so set to disabled */<br> }<br> dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */<br>
<br>- banner("RDMSR CF07");<br>+ printk(BIOS_DEBUG, "RDMSR CF07\n");<br> msr = rdmsr(MC_CF07_DATA);<br>- banner("WRMSR CF07");<br>+ printk(BIOS_DEBUG, "WRMSR CF07\n");<br>
if (dimm == DIMM0) {<br> msr.hi &= 0xFFFF0000;<br> msr.hi |= dimm_setting;<br>@@ -166,7 +161,7 @@<br> msr.hi |= dimm_setting << 16;<br> }<br> wrmsr(MC_CF07_DATA, msr);<br>- banner("ALL DONE");<br>
+ printk(BIOS_DEBUG, "ALL DONE\n");<br> }<br> <br> static void checkDDRMax(void)<br>@@ -194,7 +189,7 @@<br> <br> /* current speed > max speed? */<br> if (GeodeLinkSpeed() > speed) {<br>- print_emerg("DIMM overclocked. Check GeodeLink Speed\n");<br>
+ printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");<br> post_code(POST_PLL_MEM_FAIL);<br> hcf();<br> }<br>@@ -311,7 +306,7 @@<br> } else if ((casmap0 &= casmap1)) {<br>
spd_byte = CASDDR[__builtin_ctz(casmap0)];<br> } else {<br>- print_emerg("DIMM CAS Latencies not compatible\n");<br>+ printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");<br>
post_code(ERROR_DIFF_DIMMS);<br> hcf();<br> }<br>@@ -466,53 +461,53 @@<br> {<br> uint8_t spd_byte;<br> <br>- banner("sdram_set_spd_register");<br>+ printk(BIOS_DEBUG, "sdram_set_spd_register\n");<br>
post_code(POST_MEM_SETUP); /* post_70h */<br> <br> spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);<br>- banner("Check DIMM 0");<br>+ printk(BIOS_DEBUG, "Check DIMM 0\n");<br> /* Check DIMM is not Register and not Buffered DIMMs. */<br>
if ((spd_byte != 0xFF) && (spd_byte & 3)) {<br>- print_emerg("DIMM0 NOT COMPATIBLE\n");<br>+ printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");<br> post_code(ERROR_UNSUPPORTED_DIMM);<br>
hcf();<br> }<br>- banner("Check DIMM 1");<br>+ printk(BIOS_DEBUG, "Check DIMM 1\n");<br> spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);<br> if ((spd_byte != 0xFF) && (spd_byte & 3)) {<br>
- print_emerg("DIMM1 NOT COMPATIBLE\n");<br>+ printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");<br> post_code(ERROR_UNSUPPORTED_DIMM);<br> hcf();<br> }<br> <br> post_code(POST_MEM_SETUP2); /* post_72h */<br>
- banner("Check DDR MAX");<br>+ printk(BIOS_DEBUG, "Check DDR MAX\n");<br> <br> /* Check that the memory is not overclocked. */<br> checkDDRMax();<br> <br> /* Size the DIMMS */<br> post_code(POST_MEM_SETUP3); /* post_73h */<br>
- banner("AUTOSIZE DIMM 0");<br>+ printk(BIOS_DEBUG, "AUTOSIZE DIMM 0\n");<br> auto_size_dimm(DIMM0);<br> post_code(POST_MEM_SETUP4); /* post_74h */<br>- banner("AUTOSIZE DIMM 1");<br>
+ printk(BIOS_DEBUG, "AUTOSIZE DIMM 1\n");<br> auto_size_dimm(DIMM1);<br> <br> /* Set CAS latency */<br>- banner("set cas latency");<br>+ printk(BIOS_DEBUG, "set cas latency\n");<br>
post_code(POST_MEM_SETUP5); /* post_75h */<br> setCAS();<br> <br> /* Set all the other latencies here (tRAS, tRP....) */<br>- banner("set all latency");<br>+ printk(BIOS_DEBUG, "set all latency\n");<br>
set_latencies();<br> <br> /* Set Extended Mode Registers */<br>- banner("set emrs");<br>+ printk(BIOS_DEBUG, "set emrs\n");<br> set_extended_mode_registers();<br> <br>- banner("set ref rate");<br>
+ printk(BIOS_DEBUG, "set ref rate\n");<br> /* Set Memory Refresh Rate */<br> set_refresh_rate();<br> }<br>@@ -534,13 +529,13 @@<br> msr = rdmsr(MC_CF1017_DATA);<br> msr.lo = 0x0101;<br> wrmsr(MC_CF1017_DATA, msr);<br>
- //print_debug("sdram_enable step 2\n");<br>+ printk(BIOS_DEBUG, "sdram_enable step 2\n");<br> <br> /* 3. release CKE mask to enable CKE */<br> msr = rdmsr(MC_CFCLK_DBUG);<br> msr.lo &= ~(0x03 << 8);<br>
wrmsr(MC_CFCLK_DBUG, msr);<br>- //print_debug("sdram_enable step 3\n");<br>+ printk(BIOS_DEBUG, "sdram_enable step 3\n");<br> <br> /* 4. set and clear REF_TST 16 times, more shouldn't hurt<br>
* why this is before EMRS and MRS ? */<br>@@ -551,7 +546,7 @@<br> msr.lo &= ~(0x01 << 3);<br> wrmsr(MC_CF07_DATA, msr);<br> }<br>- //print_debug("sdram_enable step 4\n");<br>
+ printk(BIOS_DEBUG, "sdram_enable step 4\n");<br> <br> /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */<br> msr = rdmsr(MC_CF07_DATA);<br>@@ -559,7 +554,7 @@<br> wrmsr(MC_CF07_DATA, msr);<br>
msr.lo &= ~((0x01 << 28) | 0x01);<br> wrmsr(MC_CF07_DATA, msr);<br>- //print_debug("sdram_enable step 6\n");<br>+ printk(BIOS_DEBUG, "sdram_enable step 6\n");<br> <br> /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,<br>
* it is documented in LX datasheet */<br>@@ -569,7 +564,7 @@<br> wrmsr(MC_CF07_DATA, msr);<br> msr.lo &= ~((0x01 << 27) | 0x01);<br> wrmsr(MC_CF07_DATA, msr);<br>- //print_debug("sdram_enable step 7\n");<br>
+ printk(BIOS_DEBUG, "sdram_enable step 7\n");<br> <br> /* 8. load Mode Register by set and clear PROG_DRAM */<br> msr = rdmsr(MC_CF07_DATA);<br>@@ -577,7 +572,7 @@<br> wrmsr(MC_CF07_DATA, msr);<br>
msr.lo &= ~0x01;<br> wrmsr(MC_CF07_DATA, msr);<br>- //print_debug("sdram_enable step 8\n");<br>+ printk(BIOS_DEBUG, "sdram_enable step 8\n");<br> <br> /* wait 200 SDCLKs */<br> for (i = 0; i < 200; i++)<br>
</blockquote> </div><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<br>
Signed-off-by: Nils Jacobs <<a href="mailto:njacobs8@hetnet.nl">njacobs8@hetnet.nl</a>><br>
<br>
The banner part was requested by Uwe.<br>
This is Abuild and boot tested.<br>
<br>
Thanks, Nils.<br>
<br>
<br>--<br>
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