Index: src/southbridge/amd/cs5535/cs5535.h
===================================================================
--- src/southbridge/amd/cs5535/cs5535.h	(revision 6218)
+++ src/southbridge/amd/cs5535/cs5535.h	(working copy)
@@ -70,6 +70,7 @@
 #define ATA_SB_GLD_MSR_CONF	(MSR_SB_ATA + 0x01)
 #define ATA_SB_GLD_MSR_ERR	(MSR_SB_ATA + 0x03)
 #define ATA_SB_GLD_MSR_PM	(MSR_SB_ATA + 0x04)
+#define ATA_SB_IDE_CFG		(MSR_SB_ATA + 0x10)
 
 /* AC97 */
 #define AC97_SB_GLD_MSR_CONF	(MSR_SB_AC97 + 0x01)
Index: src/southbridge/amd/cs5536/cs5536.h
===================================================================
--- src/southbridge/amd/cs5536/cs5536.h	(revision 6218)
+++ src/southbridge/amd/cs5536/cs5536.h	(working copy)
@@ -93,6 +93,7 @@
 #define ATA_SB_GLD_MSR_CONF		(MSR_SB_ATA + 0x01)
 #define ATA_SB_GLD_MSR_ERR		(MSR_SB_ATA + 0x03)
 #define ATA_SB_GLD_MSR_PM		(MSR_SB_ATA + 0x04)
+#define ATA_SB_IDE_CFG			(MSR_SB_ATA + 0x10)
 
 /* */
 /*	AC97*/
Index: src/northbridge/amd/gx2/northbridge.c
===================================================================
--- src/northbridge/amd/gx2/northbridge.c	(revision 6218)
+++ src/northbridge/amd/gx2/northbridge.c	(working copy)
@@ -18,6 +18,157 @@
 
 #define NORTHBRIDGE_FILE "northbridge.c"
 
+void print_conf(void);
+
+/* Print the platform configuration - do before PCI init or it will not
+ * work right.
+ */
+void print_conf(void)
+{
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+	int i;
+	unsigned long iol;
+	msr_t msr;
+
+	int cpu_msr_defs[] = { CPU_IM_CONFIG, CPU_DM_CONFIG0,
+		CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
+		CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
+		GLCP_DELAY_CONTROLS, GL_END
+	};
+
+	int gliu0_msr_defs[] = { GLIU0_P2D_BM_0, GLIU0_P2D_BM_1,
+		GLIU0_P2D_BM_2, GLIU0_P2D_BM_3, GLIU0_P2D_BM_4,
+		GLIU0_P2D_BM_5, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1,
+		GLIU0_P2D_R_0, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1,
+		GLIU0_P2D_RO_2, GLIU0_P2D_SC_0, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
+		GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
+		GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+		GLIU0_GLD_MSR_COH, GL_END
+	};
+
+	int gliu1_msr_defs[] = { GLIU1_P2D_BM_0, GLIU1_P2D_BM_1,
+		GLIU1_P2D_BM_2, GLIU1_P2D_BM_3, GLIU1_P2D_BM_4,
+		GLIU1_P2D_BM_5, GLIU1_P2D_BM_6, GLIU1_P2D_BM_7,
+		GLIU1_P2D_BM_8, GLIU1_P2D_R_0, GLIU1_P2D_R_1,
+		GLIU1_P2D_R_2, GLIU1_P2D_R_3, GLIU1_P2D_SC_0,
+		GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
+		GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_IOD_SC_4,
+		GLIU1_IOD_SC_5, GLIU1_GLD_MSR_COH, GL_END
+	};
+
+	int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
+		CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+	};
+
+	int lbar_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, GL_END
+	};
+
+	int irq_msr[] = { MDD_IRQM_YLOW, MDD_IRQM_YHIGH, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
+		MDD_IRQM_PRIM, GL_END
+	};
+
+	int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
+		GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
+		GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
+	};
+
+	int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
+		MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
+		MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
+	};
+
+	printk(BIOS_DEBUG, "---------- CPU ------------\n");
+
+	for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(cpu_msr_defs[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+			     cpu_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
+
+	for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(gliu0_msr_defs[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+			     gliu0_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
+
+	for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(gliu1_msr_defs[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+			     gliu1_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk(BIOS_DEBUG, "---------- RCONF ------------\n");
+
+	for (i = 0; rconf_msr[i] != GL_END; i++) {
+		msr = rdmsr(rconf_msr[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+			     msr.hi, msr.lo);
+	}
+
+	printk(BIOS_DEBUG, "---------- VARIA ------------\n");
+	msr = rdmsr(ATA_SB_IDE_CFG);
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", ATA_SB_IDE_CFG, msr.hi,
+		     msr.lo);
+
+	msr = rdmsr(MDD_LEG_IO);
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_LEG_IO, msr.hi,
+		     msr.lo);
+
+	msr = rdmsr(MDD_PIN_OPT);
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_PIN_OPT, msr.hi,
+		     msr.lo);
+
+	printk(BIOS_DEBUG, "---------- PCI ------------\n");
+
+	for (i = 0; pci_msr[i] != GL_END; i++) {
+		msr = rdmsr(pci_msr[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+			     msr.hi, msr.lo);
+	}
+
+	printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
+
+	for (i = 0; dma_msr[i] != GL_END; i++) {
+		msr = rdmsr(dma_msr[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+			     msr.hi, msr.lo);
+	}
+
+	printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
+
+	for (i = 0; irq_msr[i] != GL_END; i++) {
+		msr = rdmsr(irq_msr[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", irq_msr[i],
+			     msr.hi, msr.lo);
+	}
+
+	printk(BIOS_DEBUG, "---------- DIVIL LBAR -----------\n");
+
+	for (i = 0; lbar_msr[i] != GL_END; i++) {
+		msr = rdmsr(lbar_msr[i]);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", lbar_msr[i],
+			     msr.hi, msr.lo);
+	}
+
+	iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+		     GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
+	iol = inl(GPIOL_EVENTS_ENABLE);
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+		     GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
+	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+		     GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
+	iol = inl(GPIO_MAPPER_X);
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+		     iol);
+#endif				/* CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR */
+}
+
 /* todo: add a resource record. We don't do this here because this may be called when
  * very little of the platform is actually working.
  */
@@ -297,6 +448,7 @@
 		cpubug();
 		chipsetinit();
 		setup_gx2();
+		print_conf();
 		do_vsmbios();
 		graphics_init();
 		dev->ops = &pci_domain_ops;
