Index: src/southbridge/via/Kconfig
===================================================================
--- src/southbridge/via/Kconfig	(revision 6252)
+++ src/southbridge/via/Kconfig	(working copy)
@@ -1,3 +1,4 @@
+source src/southbridge/via/k8t800/Kconfig
 source src/southbridge/via/k8t890/Kconfig
 source src/southbridge/via/vt8231/Kconfig
 source src/southbridge/via/vt8235/Kconfig
Index: src/southbridge/via/Makefile.inc
===================================================================
--- src/southbridge/via/Makefile.inc	(revision 6252)
+++ src/southbridge/via/Makefile.inc	(working copy)
@@ -1,3 +1,4 @@
+subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t800
 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890
 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890
 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231
Index: src/southbridge/via/k8t800/romstrap.inc
===================================================================
--- src/southbridge/via/k8t800/romstrap.inc	(revision 6252)
+++ src/southbridge/via/k8t800/romstrap.inc	(working copy)
@@ -20,7 +20,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This file constructs the ROM strap table for K8T890 and K8M890 */
+/* This file constructs the ROM strap table for K8T800 and K8M800 */
 
 .section ".romstrap", "a", @progbits
 
Index: src/southbridge/via/k8t800/Kconfig
===================================================================
--- src/southbridge/via/k8t800/Kconfig	(revision 6252)
+++ src/southbridge/via/k8t800/Kconfig	(working copy)
@@ -1,44 +1,44 @@
-config SOUTHBRIDGE_VIA_K8M890
+config SOUTHBRIDGE_VIA_K8M800
 	bool
 
-config SOUTHBRIDGE_VIA_K8T890
+config SOUTHBRIDGE_VIA_K8T800
 	bool
 
-config SOUTHBRIDGE_VIA_K8M890_VGA_EN
-	bool "Enable onboard K8M890 graphics"
+config SOUTHBRIDGE_VIA_K8M800_VGA_EN
+	bool "Enable onboard K8M800 graphics"
 	default y
-	depends on SOUTHBRIDGE_VIA_K8M890
+	depends on SOUTHBRIDGE_VIA_K8M800
 	select VGA
 	select GFXUMA
 
 choice
 	prompt "Framebuffer size"
-	default K8M890_VIDEO_MB_32MB
-	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
+	default K8M800_VIDEO_MB_32MB
+	depends on SOUTHBRIDGE_VIA_K8M800_VGA_EN
 
-config K8M890_VIDEO_MB_32MB
+config K8M800_VIDEO_MB_32MB
 	bool "32MB"
-config K8M890_VIDEO_MB_64MB
+config K8M800_VIDEO_MB_64MB
 	bool "64MB"
-config K8M890_VIDEO_MB_128MB
+config K8M800_VIDEO_MB_128MB
 	bool "128MB"
-config K8M890_VIDEO_MB_256MB
+config K8M800_VIDEO_MB_256MB
 	bool "256MB"
-config K8M890_VIDEO_MB_CMOS
+config K8M800_VIDEO_MB_CMOS
 	bool "Use CMOS option"
 
 endchoice
 
 config VIDEO_MB
 	int
-	default 32  if K8M890_VIDEO_MB_32MB
-	default 64  if K8M890_VIDEO_MB_64MB
-	default 128  if K8M890_VIDEO_MB_128MB
-	default 256 if K8M890_VIDEO_MB_256MB
-	default -1  if K8M890_VIDEO_MB_CMOS
-	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
+	default 32  if K8M800_VIDEO_MB_32MB
+	default 64  if K8M800_VIDEO_MB_64MB
+	default 128  if K8M800_VIDEO_MB_128MB
+	default 256 if K8M800_VIDEO_MB_256MB
+	default -1  if K8M800_VIDEO_MB_CMOS
+	depends on SOUTHBRIDGE_VIA_K8M800_VGA_EN
 
 config ID_SECTION_OFFSET
 	hex
-	default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890
+	default 0x80 if SOUTHBRIDGE_VIA_K8M800 || SOUTHBRIDGE_VIA_K8T800
 
Index: src/southbridge/via/k8t800/host_ctrl.c
===================================================================
--- src/southbridge/via/k8t800/host_ctrl.c	(revision 6252)
+++ src/southbridge/via/k8t800/host_ctrl.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,13 +25,14 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <arch/io.h>
-#include "k8t890.h"
+#include "k8t800.h"
 
 /* this may be later merged */
 
 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8t890(struct device *dev)
+static void host_ctrl_enable_k8t800(struct device *dev)
 {
+	bugnuke(" NUKE: host_ctrl_enable_k8t800()\n");
 	dump_south(dev);
 
 	/*
@@ -40,10 +42,10 @@
 	pci_write_config8(dev, 0xa0, 0x13);
 
 	/*
-	 * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+	 * NVRAM I/O base at K8T800_NVRAM_IO_BASE
 	 * Some bits are set and reserved.
 	 */
-	pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+	pci_write_config8(dev, 0xa2, (K8T800_NVRAM_IO_BASE >> 8));
 
 	/* enable NB NVRAM and enable non-posted PCI writes. */
 	pci_write_config8(dev, 0xa1, 0x8f);
@@ -55,7 +57,7 @@
 
 	/* this will be possibly removed, when I figure out
 	 * if the ROM SIP is good, second reason is that the
-	 * unknown bits are AGP related, which are dummy on K8T890
+	 * unknown bits are AGP related, which are dummy on K8T800
 	 */
 
 	writeback(dev, 0xa0, 0x13);	/* Bit4 is reserved! */
@@ -89,8 +91,9 @@
 }
 
 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8m890(struct device *dev) {
+static void host_ctrl_enable_k8m800(struct device *dev) {
 
+	bugnuke(" NUKE: host_ctrl_enable_k8m800()\n");
 	/*
 	 * Set PCI to HT outstanding requests to 03.
 	 * Bit 4 32 AGP ADS Read Outstanding Request Number
@@ -98,10 +101,10 @@
 	pci_write_config8(dev, 0xa0, 0x13);
 
 	/*
-	 * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+	 * NVRAM I/O base at K8T800_NVRAM_IO_BASE
 	 */
 
-	pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+	pci_write_config8(dev, 0xa2, (K8T800_NVRAM_IO_BASE >> 8));
 
 	/* Enable NVRAM and enable non-posted PCI writes. */
 	pci_write_config8(dev, 0xa1, 0x8f);
@@ -115,18 +118,18 @@
 }
 #if 0
 struct cbmem_entry *get_cbmem_toc(void) {
-		return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+		return (struct cbmem_entry *) inl(K8T800_NVRAM_IO_BASE+K8T800_NVRAM_CBMEM_TOC);
 }
 #endif
 void set_cbmem_toc(struct cbmem_entry *toc) {
-		outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+		outl((u32) toc, K8T800_NVRAM_IO_BASE+K8T800_NVRAM_CBMEM_TOC);
 }
 
 static const struct device_operations host_ctrl_ops_t = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.enable			= host_ctrl_enable_k8t890,
+	.enable			= host_ctrl_enable_k8t800,
 	.ops_pci		= 0,
 };
 
@@ -134,18 +137,18 @@
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.enable			= host_ctrl_enable_k8m890,
+	.enable			= host_ctrl_enable_k8m800,
 	.ops_pci		= 0,
 };
 
 static const struct pci_driver northbridge_driver_t __pci_driver = {
 	.ops	= &host_ctrl_ops_t,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_2,
+	.device	= PCI_DEVICE_ID_VIA_K8T800_2,
 };
 
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &host_ctrl_ops_m,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8M890CE_2,
+	.device	= PCI_DEVICE_ID_VIA_K8M800_2,
 };
Index: src/southbridge/via/k8t800/early_car.c
===================================================================
--- src/southbridge/via/k8t800/early_car.c	(revision 6252)
+++ src/southbridge/via/k8t800/early_car.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,33 +26,33 @@
 #include <stdlib.h>
 #include <cbmem.h>
 #include <arch/io.h>
-#include "k8t890.h"
+#include "k8t800.h"
 
 /* The 256 bytes of NVRAM for S3 storage, 256B aligned */
-#define K8T890_NVRAM_IO_BASE	0xf00
-#define K8T890_MULTIPLE_FN_EN	0x4f
+#define K8T800_NVRAM_IO_BASE	0xf00
+#define K8T800_MULTIPLE_FN_EN	0x4f
 
 /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
 static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
 
-/* This functions sets KT890 link frequency and width to same values as
+/* This functions sets KT800 link frequency and width to same values as
  * it has been setup on K8 side, by AMD NB init.
  */
 
-u8 k8t890_early_setup_ht(void)
+u8 k8t800_early_setup_ht(void)
 {
 	u8 awidth, afreq, cldtfreq, reg;
 	u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
 	u16 vldtcaps;
 
 	/* hack, enable NVRAM in chipset */
-	pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
+	pci_write_config8(PCI_DEV(0, 0x0, 0), K8T800_MULTIPLE_FN_EN, 0x01);
 
 	/*
-	 * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+	 * NVRAM I/O base at K8T800_NVRAM_IO_BASE
 	 */
 
-	pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+	pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T800_NVRAM_IO_BASE >> 8));
 	reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
 	reg |= 0x1;
 	pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
@@ -66,7 +67,7 @@
 		ldtnr = 2;
 	}
 
-	print_debug("K8T890 found at LDT ");
+	print_debug("K8T800 found at LDT ");
 	print_debug_hex8(ldtnr);
 
 	/* get the maximum widths for both sides */
@@ -117,15 +118,15 @@
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 	switch (size) {
 	case 1:
-		outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
+		outb((dword & 0xff), K8T800_NVRAM_IO_BASE+nvram_pos);
 		nvram_pos +=1;
 		break;
 	case 2:
-		outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos);
+		outw((dword & 0xffff), K8T800_NVRAM_IO_BASE+nvram_pos);
 		nvram_pos +=2;
 		break;
 	default:
-		outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos);
+		outl(dword, K8T800_NVRAM_IO_BASE+nvram_pos);
 		nvram_pos +=4;
 		break;
 	}
@@ -137,16 +138,16 @@
 	switch (size) {
 	case 1:
 		*old_dword &= ~0xff;
-		*old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos);
+		*old_dword |= inb(K8T800_NVRAM_IO_BASE+nvram_pos);
 		nvram_pos +=1;
 		break;
 	case 2:
 		*old_dword &= ~0xffff;
-		*old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos);
+		*old_dword |= inw(K8T800_NVRAM_IO_BASE+nvram_pos);
 		nvram_pos +=2;
 		break;
 	default:
-		*old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos);
+		*old_dword = inl(K8T800_NVRAM_IO_BASE+nvram_pos);
 		nvram_pos +=4;
 		break;
 	}
@@ -154,6 +155,8 @@
 	return nvram_pos;
 }
 
+/* this should be a function
 struct cbmem_entry *get_cbmem_toc(void) {
-	return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
-}
+*/
+
+#define get_cbmem_toc() ((struct cbmem_entry *) inl(K8T800_NVRAM_IO_BASE+K8T800_NVRAM_CBMEM_TOC))
Index: src/southbridge/via/k8t800/k8t800.h
===================================================================
--- src/southbridge/via/k8t800/k8t800.h	(revision 6252)
+++ src/southbridge/via/k8t800/k8t800.h	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,30 +18,33 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef SOUTHBRIDGE_VIA_K8T890_K8T890_H
-#define SOUTHBRIDGE_VIA_K8T890_K8T890_H
+#ifndef SOUTHBRIDGE_VIA_K8T800_K8T800_H
+#define SOUTHBRIDGE_VIA_K8T800_K8T800_H
 
-/* Static resources for K8T890. */
-#define K8T890_APIC_ID		0x3
+/* Static resources for K8T800. */
+#define K8T800_APIC_ID		0x3
 
+// Used strictly for personal debugging; should never make it into svn
+#define bugnuke(x) print_debug(x)
+
 /*
  * Please check the datasheet and traf_ctrl_enable before change!
  * It can't be changed to an arbitrary address.
  */
-#define K8T890_APIC_BASE	0xfecc0000
+#define K8T800_APIC_BASE	0xfecc0000
 
 /* The 256 bytes of NVRAM for S3 storage, 256B aligned */
-#define K8T890_NVRAM_IO_BASE	0xf00
-#define K8T890_NVRAM_CBMEM_TOC	0xfc
+#define K8T800_NVRAM_IO_BASE	0xf00
+#define K8T800_NVRAM_CBMEM_TOC	0xfc
 
-#define K8T890_MMCONFIG_MBAR	0x61
-#define K8T890_MULTIPLE_FN_EN	0x4f
+#define K8T800_MMCONFIG_MBAR	0x61
+#define K8T800_MULTIPLE_FN_EN	0x4f
 
 /* the FB size in MB (min is 8MB max is 512MB) */
-#define K8M890_FBSIZEMB		64
+#define K8M800_FBSIZEMB		64
 
 #ifdef __PRE_RAM__
-u8 k8t890_early_setup_ht(void);
+u8 k8t800_early_setup_ht(void);
 #else
 #include <device/device.h>
 #if 0
@@ -51,7 +55,7 @@
 
 #include <southbridge/via/vt8237r/vt8237r.h>
 
-int k8m890_host_fb_size_get(void);
-//void k8m890_host_fb_direct_set(uint32_t fb_address);
+int k8m800_host_fb_size_get(void);
+//void k8m800_host_fb_direct_set(uint32_t fb_address);
 
 #endif
Index: src/southbridge/via/k8t800/ctrl.c
===================================================================
--- src/southbridge/via/k8t800/ctrl.c	(revision 6252)
+++ src/southbridge/via/k8t800/ctrl.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,8 +23,9 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include "k8t800.h"
 
-/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
+/* We support here K8M800/K8T800 and VT8237R PCI1/Vlink which setup is not in separate
  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  */
 
@@ -34,16 +36,13 @@
 	device_t devfun3;
 
 	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+					   PCI_DEVICE_ID_VIA_K8T800_3, 0);
 
 	if (!devfun3)
 		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
+					   PCI_DEVICE_ID_VIA_K8M800_3, 0);
 
-	if (!devfun3)
-		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-					   PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
-
+	bugnuke(" NUKE: vt8237r_cfg()\n");
 	pci_write_config8(dev, 0x70, 0xc2);
 
 	/* PCI Control */
@@ -94,7 +93,7 @@
 /**
  * Setup the V-Link for VT8237R, 8X mode.
  *
- * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
+ * For K8T800CF VIA recommends what is in VIA column, AW is award 8X:
  *
  *						 REG   DEF   AW  VIA-8X VIA-4X
  *						 -----------------------------
@@ -176,17 +175,11 @@
 static const struct pci_driver northbridge_driver_t __pci_driver = {
 	.ops	= &ctrl_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_7,
+	.device	= PCI_DEVICE_ID_VIA_K8T800_7,
 };
 
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
-	.ops	= &ctrl_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CF_7,
-};
-
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &ctrl_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8M890CE_7,
+	.device	= PCI_DEVICE_ID_VIA_K8M800_7,
 };
Index: src/southbridge/via/k8t800/romstrap.lds
===================================================================
--- src/southbridge/via/k8t800/romstrap.lds	(revision 6252)
+++ src/southbridge/via/k8t800/romstrap.lds	(working copy)
@@ -19,7 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek@assembler.cz>. */
+/* Modified for K8T800 ROM strap by Rudolf Marek <r.marek@assembler.cz>. */
 
 SECTIONS {
 	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
Index: src/southbridge/via/k8t800/k8t890.h
===================================================================
--- src/southbridge/via/k8t800/k8t890.h	(revision 6252)
+++ src/southbridge/via/k8t800/k8t890.h	(working copy)
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#ifndef SOUTHBRIDGE_VIA_K8T890_K8T890_H
-#define SOUTHBRIDGE_VIA_K8T890_K8T890_H
-
-/* Static resources for K8T890. */
-#define K8T890_APIC_ID		0x3
-
-/*
- * Please check the datasheet and traf_ctrl_enable before change!
- * It can't be changed to an arbitrary address.
- */
-#define K8T890_APIC_BASE	0xfecc0000
-
-/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
-#define K8T890_NVRAM_IO_BASE	0xf00
-#define K8T890_NVRAM_CBMEM_TOC	0xfc
-
-#define K8T890_MMCONFIG_MBAR	0x61
-#define K8T890_MULTIPLE_FN_EN	0x4f
-
-/* the FB size in MB (min is 8MB max is 512MB) */
-#define K8M890_FBSIZEMB		64
-
-#ifdef __PRE_RAM__
-u8 k8t890_early_setup_ht(void);
-#else
-#include <device/device.h>
-#if 0
-extern void writeback(struct device *dev, u16 where, u8 what);
-extern void dump_south(device_t dev);
-#endif
-#endif
-
-#include <southbridge/via/vt8237r/vt8237r.h>
-
-int k8m890_host_fb_size_get(void);
-//void k8m890_host_fb_direct_set(uint32_t fb_address);
-
-#endif
Index: src/southbridge/via/k8t800/host.c
===================================================================
--- src/southbridge/via/k8t800/host.c	(revision 6252)
+++ src/southbridge/via/k8t800/host.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,12 +23,12 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include "k8t890.h"
+#include "k8t800.h"
 
 static void host_enable(struct device *dev)
 {
 	/* Multiple function control */
-	pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
+	pci_write_config8(dev, K8T800_MULTIPLE_FN_EN, 0x01);
 
 }
 
@@ -36,6 +37,7 @@
 {
 	u8 reg;
 
+	bugnuke(" NUKE: host_init()\n");
 	/* AGP Capability Header Control */
 	reg = pci_read_config8(dev, 0x4d);
 	reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
@@ -73,17 +75,11 @@
 static const struct pci_driver northbridge_driver_t __pci_driver = {
 	.ops	= &host_ops_t,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_0,
+	.device	= PCI_DEVICE_ID_VIA_K8T800_0,
 };
 
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
-	.ops	= &host_ops_t,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CF_0,
-};
-
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &host_ops_m,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8M890CE_0,
+	.device	= PCI_DEVICE_ID_VIA_K8M800_0,
 };
Index: src/southbridge/via/k8t800/chrome.c
===================================================================
--- src/southbridge/via/k8t800/chrome.c	(revision 6252)
+++ src/southbridge/via/k8t800/chrome.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,7 +24,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <string.h> /* for memset */
-#include "k8t890.h"
+#include "k8t800.h"
 
 #if CONFIG_VGA
 #include <pc80/vga_io.h>
@@ -123,7 +124,7 @@
 {
 	uint32_t fb_size, fb_address;
 
-	fb_size = k8m890_host_fb_size_get();
+	fb_size = k8m800_host_fb_size_get();
 	if (!fb_size) {
 		printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
 			       " ramcontroller!\n");
@@ -140,7 +141,7 @@
 	printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
 		    fb_size, fb_address);
 
-	//k8m890_host_fb_direct_set(fb_address);
+	//k8m800_host_fb_direct_set(fb_address);
 
 #if CONFIG_VGA
 	/* Now set up the VGA console */
Index: src/southbridge/via/k8t800/traf_ctrl.c
===================================================================
--- src/southbridge/via/k8t800/traf_ctrl.c	(revision 6252)
+++ src/southbridge/via/k8t800/traf_ctrl.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,7 +22,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include "k8t890.h"
+#include "k8t800.h"
 
 extern unsigned long log2(unsigned long x);
 
@@ -30,13 +31,14 @@
 	struct resource *resource;
 	u8 reg;
 
-	resource = find_resource(dev, K8T890_MMCONFIG_MBAR);
+	bugnuke(" NUKE: mmconfig_set_resources()\n");
+	resource = find_resource(dev, K8T800_MMCONFIG_MBAR);
 	if (resource) {
 		report_resource_stored(dev, resource, "<mmconfig>");
 
 		/* Remember this resource has been stored. */
 		resource->flags |= IORESOURCE_STORED;
-		pci_write_config8(dev, K8T890_MMCONFIG_MBAR,
+		pci_write_config8(dev, K8T800_MMCONFIG_MBAR,
 				  (resource->base >> 28));
 		reg = pci_read_config8(dev, 0x60);
 		reg |= 0x3;
@@ -48,12 +50,13 @@
 
 static void apic_mmconfig_read_resources(device_t dev)
 {
+	bugnuke(" NUKE: apic_mmconfig_read_resources()\n");
 	struct resource *res;
 	pci_dev_read_resources(dev);
 
 	res = new_resource(dev, 0x40);
 	/* NB APIC fixed to this address. */
-	res->base = K8T890_APIC_BASE;
+	res->base = K8T800_APIC_BASE;
 	res->size = 256;
 	res->limit = res->base + res->size - 1;
 	res->align = 8;
@@ -62,7 +65,7 @@
 		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
 	/* Add an MMCONFIG resource. */
-	res = new_resource(dev, K8T890_MMCONFIG_MBAR);
+	res = new_resource(dev, K8T800_MMCONFIG_MBAR);
 	res->size = 256 * 1024 * 1024;
 	res->align = log2(res->size);
 	res->gran = log2(res->size);
@@ -75,6 +78,7 @@
 	volatile u32 *apic;
 	u32 data;
 
+	bugnuke(" NUKE: traf_ctrl_enable_generic()\n");
 	/* no device2 redirect, enable just one device behind
 	 * bridge device 2 and device 3).
 	 */
@@ -87,13 +91,13 @@
 
 	/* Offset80 ->95 bit 4 in 1 in Award. */
 
-	/* Enable APIC, to K8T890_APIC_BASE. */
+	/* Enable APIC, to K8T800_APIC_BASE. */
 	pci_write_config8(dev, 0x41, 0x00);
 	pci_write_config8(dev, 0x40, 0x8c);
 	/* BT_INTR enable, APIC Nonshare Mode Enable. */
 	pci_write_config8(dev, 0x42, 0x5);
 
-	apic = (u32 *)K8T890_APIC_BASE;
+	apic = (u32 *)K8T800_APIC_BASE;
 
 	/* Set APIC to FSB transported messages. */
 	apic[0] = 3;
@@ -103,18 +107,20 @@
 	/* Set APIC ID. */
 	apic[0] = 0;
 	data = apic[4];
-	apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
+	apic[4] = (data & 0xF0FFFF) | (K8T800_APIC_ID << 24);
 }
 
-static void traf_ctrl_enable_k8m890(struct device *dev)
+static void traf_ctrl_enable_k8m800(struct device *dev)
 {
+	bugnuke(" NUKE: traf_ctrl_enable_k8m800()\n");
 	traf_ctrl_enable_generic(dev);
 }
 
-static void traf_ctrl_enable_k8t890(struct device *dev)
+static void traf_ctrl_enable_k8t800(struct device *dev)
 {
 	u8 reg;
 
+	bugnuke(" NUKE: traf_ctrl_enable_k8t800()\n");
 	traf_ctrl_enable_generic(dev);
 
 	/* Enable D3F1-D3F3 */
@@ -126,7 +132,7 @@
 	.read_resources		= apic_mmconfig_read_resources,
 	.set_resources		= mmconfig_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.enable			= traf_ctrl_enable_k8m890,
+	.enable			= traf_ctrl_enable_k8m800,
 	.ops_pci		= 0,
 };
 
@@ -134,24 +140,18 @@
 	.read_resources		= apic_mmconfig_read_resources,
 	.set_resources		= mmconfig_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.enable			= traf_ctrl_enable_k8t890,
+	.enable			= traf_ctrl_enable_k8t800,
 	.ops_pci		= 0,
 };
 
 static const struct pci_driver northbridge_driver_t __pci_driver = {
 	.ops	= &traf_ctrl_ops_t,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_5,
+	.device	= PCI_DEVICE_ID_VIA_K8T800_5,
 };
 
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
-	.ops	= &traf_ctrl_ops_t,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CF_5,
-};
-
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &traf_ctrl_ops_m,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8M890CE_5,
+	.device	= PCI_DEVICE_ID_VIA_K8M800_5,
 };
Index: src/southbridge/via/k8t800/pcie.c
===================================================================
--- src/southbridge/via/k8t800/pcie.c	(revision 6252)
+++ src/southbridge/via/k8t800/pcie.c	(working copy)
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pciexp.h>
-#include <device/pci_ids.h>
-#include <delay.h>
-#include "k8t890.h"
-
-/*
- * Note:
- * The pcie bridges are similar to the VX800 ones documented at
- * http://linux.via.com.tw/
- */
-
-static void pcie_common_init(struct device *dev)
-{
-	u8 reg;
-	int i, up;
-
-	/* Disable downstream read cycle retry,
-	 * otherwise the bus scan will hang if no device is plugged in. */
-	reg = pci_read_config8(dev, 0xa3);
-	pci_write_config8(dev, 0xa3, reg & ~0x01);
-
-	/* Use PHY negotiation for lane config */
-	reg = pci_read_config8(dev, 0xc1);
-	pci_write_config8(dev, 0xc1, reg & ~0x1f);
-
-	/* Award has 0xb, VIA recommends 0xd, default 0x8.
-	 * bit4: receive polarity change control
-	 * bits3:2: squelch window select 64~175mv
-	 * bit1: Number of non-idle bits detected before exiting idle state
-	 *       0: 10 bits, 1: 2 bits
-	 * bit0: Number of idle bits detected before entering idle state
-	 *       0: 10 bits, 1: 2 bits
-	 */
-	pci_write_config8(dev, 0xe1, 0xb);
-
-	/* Set replay timer limit. */
-	pci_write_config8(dev, 0xb1, 0xf0);
-
-	/* Enable link. */
-	reg = pci_read_config8(dev, 0x50);
-	pci_write_config8(dev, 0x50, reg & ~0x10);
-
-	/* Wait up to 100ms for link to come up */
-	up = 0;
-	for (i=0; i<1000; i++) {
-		if (pci_read_config16(dev, 0x52) & (1<<13)) {
-			up = 1;
-			break;
-		}
-		udelay(100);
-	}
-
-	printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev));
-	if (up)
-		printk(BIOS_SPEW, "up after %d us\n", i*100);
-	else
-		printk(BIOS_SPEW, "timeout\n");
-
-	dump_south(dev);
-}
-
-static void peg_init(struct device *dev)
-{
-	u8 reg;
-
-	printk(BIOS_DEBUG, "Configuring PCIe PEG\n");
-	dump_south(dev);
-
-	/* Disable link. */
-	reg = pci_read_config8(dev, 0x50);
-	pci_write_config8(dev, 0x50, reg | 0x10);
-
-	/*
-	 * pci_write_config8(dev, 0xe2, 0x0);
-	 * pci_write_config8(dev, 0xe3, 0x92);
-	 */
-
-	/* Bit0 = 1 SDP (Start DLLP) always at Lane0. */
-	reg = pci_read_config8(dev, 0xb8);
-	pci_write_config8(dev, 0xb8, reg | 0x1);
-
-	/*
-	 * Downstream wait and Upstream Checking Malformed TLP through
-	 * "Byte Enable Rule" And "Over 4K Boundary Rule".
-	 */
-	reg = pci_read_config8(dev, 0xa4);
-	pci_write_config8(dev, 0xa4, reg | 0x30);
-
-	pcie_common_init(dev);
-}
-
-static void pcie_init(struct device *dev)
-{
-	u8 reg;
-
-	printk(BIOS_DEBUG, "Configuring PCIe PEXs\n");
-	dump_south(dev);
-
-	/* Disable link. */
-	reg = pci_read_config8(dev, 0x50);
-	pci_write_config8(dev, 0x50, reg | 0x10);
-
-	pcie_common_init(dev);
-}
-
-static const struct device_operations peg_ops = {
-	.read_resources		= pci_bus_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_bus_enable_resources,
-	.enable			= peg_init,
-	.scan_bus		= pciexp_scan_bridge,
-	.reset_bus		= pci_bus_reset,
-	.ops_pci		= 0,
-};
-
-static const struct device_operations pcie_ops = {
-	.read_resources		= pci_bus_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_bus_enable_resources,
-	.enable			= pcie_init,
-	.scan_bus		= pciexp_scan_bridge,
-	.reset_bus		= pci_bus_reset,
-	.ops_pci		= 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
-	.ops	= &peg_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_PEG,
-};
-
-static const struct pci_driver pcie_drvd3f0 __pci_driver = {
-	.ops	= &pcie_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_PEX0,
-};
-
-static const struct pci_driver pcie_drvd3f1 __pci_driver = {
-	.ops	= &pcie_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_PEX1,
-};
-
-static const struct pci_driver pcie_drvd3f2 __pci_driver = {
-	.ops	= &pcie_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_PEX2,
-};
-
-static const struct pci_driver pcie_drvd3f3 __pci_driver = {
-	.ops	= &pcie_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_PEX3,
-};
Index: src/southbridge/via/k8t800/dram.c
===================================================================
--- src/southbridge/via/k8t800/dram.c	(revision 6252)
+++ src/southbridge/via/k8t800/dram.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,7 +26,7 @@
 #include <cpu/amd/mtrr.h>
 #include <pc80/mc146818rtc.h>
 #include <bitops.h>
-#include "k8t890.h"
+#include "k8t800.h"
 
 static void dram_enable(struct device *dev)
 {
@@ -36,6 +37,7 @@
 	 * Enable Lowest Interrupt arbitration for APIC, enable NB APIC
 	 * decoding, MSI support, no SMRAM, compatible SMM.
 	 */
+	bugnuke(" NUKE: dram_enable()\n");
 	pci_write_config8(dev, 0x86, 0x39);
 
 	/*
@@ -71,13 +73,14 @@
 extern uint64_t uma_memory_base, uma_memory_size;
 #endif
 
-static void dram_enable_k8m890(struct device *dev)
+static void dram_enable_k8m800(struct device *dev)
 {
 #if CONFIG_GFXUMA
 	msr_t msr;
 	int ret;
 	unsigned int fbbits;
 
+	bugnuke("dram_enable_k8m800()\n");
 	/* use CMOS */
 	if (CONFIG_VIDEO_MB == -1) {
 		ret = get_option(&fbbits, "videoram_size");
@@ -98,7 +101,7 @@
 
 	msr = rdmsr(TOP_MEM);
 	uma_memory_base = msr.lo - uma_memory_size;
-	printk(BIOS_INFO, "K8M890: UMA base is %llx size is %u (MB)\n", uma_memory_base,
+	printk(BIOS_INFO, "K8M800: UMA base is %llx size is %u (MB)\n", uma_memory_base,
 				(u32) (uma_memory_size / 1024 / 1024));
 	/* enable VGA, so the bridges gets VGA_EN and resources are set */
 	pci_write_config8(dev, 0xa1, 0x80);
@@ -107,12 +110,13 @@
 }
 
 int
-k8m890_host_fb_size_get(void)
+k8m800_host_fb_size_get(void)
 {
 	struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
-					     PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
+					     PCI_DEVICE_ID_VIA_K8M800_3, 0);
 	unsigned char tmp;
 
+	bugnuke("k8m800_host_fb_size_get()\n");
 	tmp = pci_read_config8(dev, 0xA1);
 	tmp >>= 4;
 	if (tmp & 0x08)
@@ -134,7 +138,7 @@
 	u8 tmp;
 
 	fbbits = ((log2(uma_memory_size >> 20) - 2) << 4);
-	printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20));
+	printk(BIOS_INFO, "K8M800: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20));
 
 	/* Step 1: enable UMA but no FB */
 	pci_write_config8(dev, 0xa1, 0x80);
@@ -159,7 +163,7 @@
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.enable			= dram_enable_k8m890,
+	.enable			= dram_enable_k8m800,
 	.init			= dram_init_fb,
 	.ops_pci		= 0,
 };
@@ -167,17 +171,11 @@
 static const struct pci_driver northbridge_driver_t __pci_driver = {
 	.ops	= &dram_ops_t,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_3,
+	.device	= PCI_DEVICE_ID_VIA_K8T800_3,
 };
 
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
-	.ops	= &dram_ops_t,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CF_3,
-};
-
 static const struct pci_driver northbridge_driver_m __pci_driver = {
 	.ops	= &dram_ops_m,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8M890CE_3,
+	.device	= PCI_DEVICE_ID_VIA_K8M800_3,
 };
Index: src/southbridge/via/k8t800/error.c
===================================================================
--- src/southbridge/via/k8t800/error.c	(revision 6252)
+++ src/southbridge/via/k8t800/error.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,7 +32,7 @@
 	 */
 	pci_write_config8(dev, 0x58, 0x81);
 
-	/* TODO: enable AGP errors reporting on K8M890 */
+	/* TODO: enable AGP errors reporting on K8M800 */
 }
 
 static const struct device_operations error_ops = {
@@ -45,17 +46,5 @@
 static const struct pci_driver northbridge_driver_t __pci_driver = {
 	.ops	= &error_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_1,
+	.device	= PCI_DEVICE_ID_VIA_K8T800_1,
 };
-
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
-	.ops	= &error_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CF_1,
-};
-
-static const struct pci_driver northbridge_driver_m __pci_driver = {
-	.ops	= &error_ops,
-	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8M890CE_1,
-};
Index: src/southbridge/via/k8t800/bridge.c
===================================================================
--- src/southbridge/via/k8t800/bridge.c	(revision 6252)
+++ src/southbridge/via/k8t800/bridge.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,7 +22,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include "k8t890.h"
+#include "k8t800.h"
 
 static void bridge_enable(struct device *dev)
 {
@@ -32,14 +33,14 @@
 	writeback(dev, 0x40, 0x91);
 	writeback(dev, 0x41, 0x40);
 	writeback(dev, 0x43, 0x44);
-	writeback(dev, 0x44, 0x31); 	/* K8M890 should have 0x35 datasheet
+	writeback(dev, 0x44, 0x31); 	/* K8M800 should have 0x35 datasheet
 					 * says it is reserved
 					 */
 	writeback(dev, 0x45, 0x3a);
 	writeback(dev, 0x46, 0x88);	/* PCI ID lo */
 	writeback(dev, 0x47, 0xb1);	/* PCI ID hi */
 
-	/* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
+	/* Bridge control, K8M800 bit 3 should be set to enable VGA on AGP
 	 * (Forward VGA compatible memory and I/O cycles )
 	 */
 
@@ -66,5 +67,5 @@
 static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops	= &bridge_ops,
 	.vendor	= PCI_VENDOR_ID_VIA,
-	.device	= PCI_DEVICE_ID_VIA_K8T890CE_BR,
+	.device	= PCI_DEVICE_ID_VIA_K8T800_BR,
 };
Index: src/devices/pnp_device.c
===================================================================
--- src/devices/pnp_device.c	(revision 6252)
+++ src/devices/pnp_device.c	(working copy)
@@ -183,6 +183,12 @@
 	step = 1 << gran;
 
 	/* Find the first bit that moves. */
+	/* If by any chance, moving will be zero when entering the loop
+	 * we will never exit it. This check ensures that execution
+	 * continues if this conditon arises.
+	 * FIXME: Is this the best solution?
+	 */
+	if(moving != 0)
 	while ((moving & step) == 0) {
 		gran--;
 		step >>= 1;
Index: src/include/device/pci_ids.h
===================================================================
--- src/include/device/pci_ids.h	(revision 6252)
+++ src/include/device/pci_ids.h	(working copy)
@@ -1220,6 +1220,24 @@
 #define PCI_DEVICE_ID_VIA_8505_1	0x8605
 #define PCI_DEVICE_ID_VIA_8633_1	0xB091
 #define PCI_DEVICE_ID_VIA_8367_1	0xB099
+#define PCI_DEVICE_ID_VIA_K8T800_0	0x0282
+#define PCI_DEVICE_ID_VIA_K8T800_1	0x1282
+#define PCI_DEVICE_ID_VIA_K8T800_2	0x2282
+#define PCI_DEVICE_ID_VIA_K8T800_3	0x3282
+#define PCI_DEVICE_ID_VIA_K8T800_4	0x4282
+#define PCI_DEVICE_ID_VIA_K8T800_5	0x5282
+#define PCI_DEVICE_ID_VIA_K8T800_6	0x6282
+#define PCI_DEVICE_ID_VIA_K8T800_7	0x7282
+#define PCI_DEVICE_ID_VIA_K8M800_0	0x0204
+#define PCI_DEVICE_ID_VIA_K8M800_1	0x1204
+#define PCI_DEVICE_ID_VIA_K8M800_2	0x2204
+#define PCI_DEVICE_ID_VIA_K8M800_3	0x3204
+#define PCI_DEVICE_ID_VIA_K8M800_4	0x4204
+#define PCI_DEVICE_ID_VIA_K8M800_5	0x5204
+#define PCI_DEVICE_ID_VIA_K8M800_6	0x6204
+#define PCI_DEVICE_ID_VIA_K8M800_7	0x7204
+#define PCI_DEVICE_ID_VIA_K8T800_AGP	0x3188
+#define PCI_DEVICE_ID_VIA_K8T800_BR	0xb188
 #define PCI_DEVICE_ID_VIA_K8T890CE_0	0x0238
 #define PCI_DEVICE_ID_VIA_K8T890CE_1	0x1238
 #define PCI_DEVICE_ID_VIA_K8T890CE_2	0x2238
Index: src/mainboard/asus/Kconfig
===================================================================
--- src/mainboard/asus/Kconfig	(revision 6252)
+++ src/mainboard/asus/Kconfig	(working copy)
@@ -27,6 +27,8 @@
 	bool "A8V-E SE"
 config BOARD_ASUS_A8V_E_DELUXE
 	bool "A8V-E Deluxe"
+config BOARD_ASUS_K8V_X_SE
+	bool "K8V-X SE"
 config BOARD_ASUS_M2N_E
 	bool "M2N-E"
 config BOARD_ASUS_M2V
@@ -59,6 +61,7 @@
 source "src/mainboard/asus/a8n_e/Kconfig"
 source "src/mainboard/asus/a8v-e_se/Kconfig"
 source "src/mainboard/asus/a8v-e_deluxe/Kconfig"
+source "src/mainboard/asus/k8v-x_se/Kconfig"
 source "src/mainboard/asus/m2n-e/Kconfig"
 source "src/mainboard/asus/m2v/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
Index: src/mainboard/asus/k8v-x_se/Kconfig
===================================================================
--- src/mainboard/asus/k8v-x_se/Kconfig	(revision 6252)
+++ src/mainboard/asus/k8v-x_se/Kconfig	(working copy)
@@ -1,26 +1,25 @@
-if BOARD_ASUS_A8V_E_SE
+if BOARD_ASUS_K8V_X_SE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_SOCKET_939
-	select K8_HT_FREQ_1G_SUPPORT
+	select CPU_AMD_SOCKET_754
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_VIA_VT8237R
-	select SOUTHBRIDGE_VIA_K8T890
+	select SOUTHBRIDGE_VIA_K8T800
 	select SUPERIO_WINBOND_W83627EHG
+	select CACHE_AS_RAM
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
 	select QRANK_DIMM_SUPPORT
-	select SET_FIDVID
 
 config MAINBOARD_DIR
 	string
-	default asus/a8v-e_se
+	default asus/k8v-x_se
 
 config DCACHE_RAM_BASE
 	hex
@@ -44,7 +43,7 @@
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "A8V-E SE"
+	default "K8V-X SE"
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -74,4 +73,4 @@
 	hex
 	default 0x1043
 
-endif # BOARD_ASUS_A8V_E_SE
+endif # BOARD_ASUS_K8V_X_SE
Index: src/mainboard/asus/k8v-x_se/mptable_from_other_board.c
===================================================================
--- src/mainboard/asus/k8v-x_se/mptable_from_other_board.c	(revision 0)
+++ src/mainboard/asus/k8v-x_se/mptable_from_other_board.c	(revision 0)
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t800/k8t800.h"
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/* I/O APICs:	APIC ID	Version	State		Address */
+	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, K8T800_APIC_ID, 0x20, K8T800_APIC_BASE);
+
+	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 0, K8T800_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 1, K8T800_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 2, K8T800_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 3, K8T800_APIC_ID, 0x3);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 0, K8T800_APIC_ID, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 1, K8T800_APIC_ID, 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 2, K8T800_APIC_ID, 0xf);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 3, K8T800_APIC_ID, 0x13);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x3);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x7);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 2, K8T800_APIC_ID, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 3, K8T800_APIC_ID, 0xb);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 0, K8T800_APIC_ID, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 1, K8T800_APIC_ID, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 2, K8T800_APIC_ID, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 3, K8T800_APIC_ID, 0xf);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x11);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x12);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x13);
+
+	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
+	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums. */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
+						mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+                mc, smp_next_mpe_entry(mc));
+
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/asus/k8v-x_se/devicetree.cb
===================================================================
--- src/mainboard/asus/k8v-x_se/devicetree.cb	(revision 6252)
+++ src/mainboard/asus/k8v-x_se/devicetree.cb	(working copy)
@@ -1,6 +1,6 @@
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# CPU
+    chip cpu/amd/socket_754			# CPU
       device lapic 0 on end			# APIC
     end
   end
@@ -12,7 +12,7 @@
           register "ide0_enable" = "1"		# Enable IDE channel 0
           register "ide1_enable" = "1"		# Enable IDE channel 1
           register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
-          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "ide1_80pin_cable" = "0"	# 80pin cable on IDE channel 1
           register "fn_ctrl_lo" = "0"		# Enable SB functions
           register "fn_ctrl_hi" = "0xad"	# Enable SB functions
           device pci 0.0 on end			# HT
@@ -24,12 +24,6 @@
             chip drivers/generic/generic	# DIMM 0-0-1
               device i2c 51 on end
             end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
             chip superio/winbond/w83627ehg	# Super I/O
               device pnp 2e.0 on		# Floppy
                 io 0x60 = 0x3f0
@@ -39,7 +33,7 @@
               device pnp 2e.1 on		# Parallel port
                 io 0x60 = 0x378
                 irq 0x70 = 7
-                drq 0x74 = 3
+                drq 0x74 = 4
               end
               device pnp 2e.2 on		# Com1
                 io 0x60 = 0x3f8
@@ -49,19 +43,21 @@
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 2e.5 off		# PS/2 keyboard & mouse (off)
+              device pnp 2e.5 on		# PS/2 keyboard & mouse (on or off?)
+                io 0x60 = 0x60
+                irq 0x70 = 1
               end
               device pnp 2e.106 off		# Serial flash interface (SFI)
                 io 0x60 = 0x100
               end
               device pnp 2e.007 off		# GPIO 1
               end
-              device pnp 2e.107 on		# Game port
+              device pnp 2e.107 off		# Game port
                 io 0x60 = 0x201
               end
-              device pnp 2e.207 on		# MIDI
+              device pnp 2e.207 off		# MIDI
                 io 0x62 = 0x330
-                irq 0x70 = 0xa
+                irq 0x70 = 9
               end
               device pnp 2e.307 off		# GPIO 6
               end
@@ -83,9 +79,9 @@
               end
             end
           end
-          device pci 12.0 off end		# VIA LAN (off, other chip used)
+          device pci 12.0 on end		# VIA LAN
         end
-        chip southbridge/via/k8t890		# "Southbridge" K8T890
+        chip southbridge/via/k8t800		# "Southbridge" K8T800
         end
       end
       device pci 18.1 on end
Index: src/mainboard/asus/k8v-x_se/romstage.c
===================================================================
--- src/mainboard/asus/k8v-x_se/romstage.c	(revision 6252)
+++ src/mainboard/asus/k8v-x_se/romstage.c	(working copy)
@@ -6,6 +6,7 @@
  * Copyright (C) 2006 MSI
  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -42,7 +43,7 @@
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/early_serial.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -79,7 +80,7 @@
 	}
 }
 
-#include "southbridge/via/k8t890/early_car.c"
+#include "southbridge/via/k8t800/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -88,7 +89,7 @@
 #include "cpu/amd/dualcore/dualcore.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
+//#include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 
 unsigned int get_sbdn(unsigned bus)
@@ -146,11 +147,7 @@
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		DIMM0, DIMM2, 0, 0,
-		DIMM1, DIMM3, 0, 0,
-		// Node 1
-		DIMM4, DIMM6, 0, 0,
-		DIMM5, DIMM7, 0, 0,
+		DIMM0, DIMM1, 0, 0,
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
@@ -202,7 +199,7 @@
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-	needs_reset |= k8t890_early_setup_ht();
+	needs_reset |= k8t800_early_setup_ht();
 
 	if (needs_reset) {
 		print_debug("ht reset -\n");
@@ -210,15 +207,18 @@
 	}
 
 	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
-	enable_fid_change();
+	/*enable_fid_change();
+	print_debug("post fis_change\n");
 	init_fidvid_bsp(bsp_apicid);
+	print_debug("post fis_bsp\n");
+	*/
 
 	/* Stop the APs so we can start them later in init. */
 	allow_all_aps_stop(bsp_apicid);
 
 	/* It's the time to set ctrl now. */
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
+	
 	enable_smbus();
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
Index: src/mainboard/asus/k8v-x_se/mptable.c.generated
===================================================================
--- src/mainboard/asus/k8v-x_se/mptable.c.generated	(revision 0)
+++ src/mainboard/asus/k8v-x_se/mptable.c.generated	(revision 0)
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/* generated by MPTable, version 2.0.15*/
+/* as modified by RGM for coreboot */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t800/k8t800.h"
+
+static void *smp_write_config_table(void *v)
+{
+        struct mp_config_table *mc;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+        mptable_init(mc, LAPIC_ADDR);
+
+        smp_write_processors(mc);
+
+
+        /*Bus:          Bus ID  Type*/
+        smp_write_bus(mc, 0, "PCI   ");
+        smp_write_bus(mc, 1, "PCI   ");
+        smp_write_bus(mc, 2, "ISA   ");
+        /*I/O APICs:    APIC ID Version State           Address*/
+        smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, K8T800_APIC_ID, 0x20, K8T800_APIC_BASE);
+        /* TODO: If you have multiple IOAPICs, add them here. */
+        /*I/O Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#
+         */      
+        smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x1, 0x0);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x1, 0x1, 0x1);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x1, 0x2);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x3, 0x1, 0x3);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x4, 0x1, 0x4);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x5, 0x1, 0x5);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x6, 0x1, 0x6);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x7, 0x1, 0x7);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x2, 0x8, 0x1, 0x8);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x9, 0x1, 0x9);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xa, 0x1, 0xa);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xb, 0x1, 0xb);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xc, 0x1, 0xc);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xd, 0x1, 0xd);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xe, 0x1, 0xe);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xf, 0x1, 0xf);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x1, 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x1, 0x16);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x1, 0x14);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3c, 0x1, 0x14);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x1, 0x15);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x1, 0x15);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x1, 0x15);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x2c, 0x1, 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x30, 0x1, 0x11);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x1, 0x17);
+/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
+        smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+        smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+        /* Compute the checksums. */
+        mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+        mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+        printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+                mc, smp_next_mpe_entry(mc));
+        return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+        void *v;
+        v = smp_write_floating_table(addr);
+        return (unsigned long)smp_write_config_table(v);
+}
+ 
Index: src/mainboard/asus/k8v-x_se/mptable.c
===================================================================
--- src/mainboard/asus/k8v-x_se/mptable.c	(revision 6252)
+++ src/mainboard/asus/k8v-x_se/mptable.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,7 +23,7 @@
 #include <arch/smp/mpspec.h>
 #include <arch/ioapic.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
+#include "southbridge/via/k8t800/k8t800.h"
 
 static void *smp_write_config_table(void *v)
 {
@@ -39,25 +40,30 @@
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
-	smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+	smp_write_ioapic(mc, K8T800_APIC_ID, 0x20, K8T800_APIC_BASE);
 
 	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xa << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xa << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xa << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xa << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ17
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ17
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ19
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ17
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ16
 
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 0, VT8237R_APIC_ID, 0x13); //IRQ18
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 1, VT8237R_APIC_ID, 0x10); //IRQ19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 2, VT8237R_APIC_ID, 0x11); //IRQ16
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 3, VT8237R_APIC_ID, 0x12); //IRQ17
+
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
@@ -65,40 +71,40 @@
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 0, K8T800_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 1, K8T800_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 2, K8T800_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 3, K8T800_APIC_ID, 0x3);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 0, K8T800_APIC_ID, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 1, K8T800_APIC_ID, 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 2, K8T800_APIC_ID, 0xf);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 3, K8T800_APIC_ID, 0x13);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x3);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x7);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 2, K8T800_APIC_ID, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 3, K8T800_APIC_ID, 0xb);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 0, K8T800_APIC_ID, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 1, K8T800_APIC_ID, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 2, K8T800_APIC_ID, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 3, K8T800_APIC_ID, 0xf);
 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x11);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x12);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x13);
 
 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
 	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
Index: src/mainboard/asus/k8v-x_se/mpdiff
===================================================================
--- src/mainboard/asus/k8v-x_se/mpdiff	(revision 0)
+++ src/mainboard/asus/k8v-x_se/mpdiff	(revision 0)
@@ -0,0 +1,162 @@
+19,24c19
+< /* generated by MPTable, version 2.0.15*/
+< /* as modified by RGM for coreboot */
+< #include <console/console.h>
+< #include <arch/smp/mpspec.h>
+< #include <arch/ioapic.h>
+< #include <device/pci.h>
+---
+> 
+26a22,25
+> #include <arch/smp/mpspec.h>
+> #include <arch/ioapic.h>
+> #include "southbridge/via/vt8237r/vt8237r.h"
+> #include "southbridge/via/k8t800/k8t800.h"
+30c29,30
+<         struct mp_config_table *mc;
+---
+> 	struct mp_config_table *mc;
+> 	int bus_isa;
+32c32
+<         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+---
+> 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+34c34
+<         mptable_init(mc, "TODO        ", LAPIC_ADDR);
+---
+> 	mptable_init(mc, LAPIC_ADDR);
+36c36
+<         smp_write_processors(mc);
+---
+> 	smp_write_processors(mc);
+37a38,111
+> 	mptable_write_buses(mc, NULL, &bus_isa);
+> 
+> 	/* I/O APICs:	APIC ID	Version	State		Address */
+> 	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+> 	smp_write_ioapic(mc, K8T800_APIC_ID, 0x20, K8T800_APIC_BASE);
+> 
+> 	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 0, K8T800_APIC_ID, 0x3);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 1, K8T800_APIC_ID, 0x3);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 2, K8T800_APIC_ID, 0x3);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 3, K8T800_APIC_ID, 0x3);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 0, K8T800_APIC_ID, 0x7);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 1, K8T800_APIC_ID, 0xb);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 2, K8T800_APIC_ID, 0xf);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 3, K8T800_APIC_ID, 0x13);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x0);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x1);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x2);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x3);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x4);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x5);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x6);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x7);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x8);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x9);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 2, K8T800_APIC_ID, 0xa);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 3, K8T800_APIC_ID, 0xb);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 0, K8T800_APIC_ID, 0xc);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 1, K8T800_APIC_ID, 0xd);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 2, K8T800_APIC_ID, 0xe);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 3, K8T800_APIC_ID, 0xf);
+> 
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 0, K8T800_APIC_ID, 0x10);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 1, K8T800_APIC_ID, 0x11);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T800_APIC_ID, 0x12);
+> 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T800_APIC_ID, 0x13);
+> 
+> 	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
+> 	smp_write_lintsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+> 	smp_write_lintsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+> 	/* There is no extension information... */
+> 
+> 	/* Compute the checksums. */
+> 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
+> 						mc->mpe_length);
+> 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+39,81c113
+< /*Bus:          Bus ID  Type*/
+<         smp_write_bus(mc, 0, "PCI   ");
+<         smp_write_bus(mc, 1, "PCI   ");
+<         smp_write_bus(mc, 2, "ISA   ");
+< /*I/O APICs:    APIC ID Version State           Address*/
+<         smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+<         /* TODO: If you have multiple IOAPICs, add them here. */
+< /*I/O Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#
+< */      smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x1, 0x0);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x1, 0x1, 0x1);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x1, 0x2);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x3, 0x1, 0x3);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x4, 0x1, 0x4);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x5, 0x1, 0x5);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x6, 0x1, 0x6);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x7, 0x1, 0x7);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x2, 0x8, 0x1, 0x8);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x9, 0x1, 0x9);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xa, 0x1, 0xa);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xb, 0x1, 0xb);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xc, 0x1, 0xc);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xd, 0x1, 0xd);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xe, 0x1, 0xe);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xf, 0x1, 0xf);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x1, 0x10);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x1, 0x16);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x1, 0x14);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3c, 0x1, 0x14);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x1, 0x15);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x1, 0x15);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x1, 0x15);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x2c, 0x1, 0x10);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x30, 0x1, 0x11);
+<         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x1, 0x17);
+< /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
+<         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+<         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+<         /* Compute the checksums. */
+<         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+<         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+<         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+<                 mc, smp_next_mpe_entry(mc));
+<         return smp_next_mpe_entry(mc);
+---
+> 	return smp_next_mpe_entry(mc);
+86,88c118,120
+<         void *v;
+<         v = smp_write_floating_table(addr);
+<         return (unsigned long)smp_write_config_table(v);
+---
+> 	void *v;
+> 	v = smp_write_floating_table(addr);
+> 	return (unsigned long)smp_write_config_table(v);
+90d121
+<  
Index: src/mainboard/asus/k8v-x_se/acpi_tables.c
===================================================================
--- src/mainboard/asus/k8v-x_se/acpi_tables.c	(revision 6252)
+++ src/mainboard/asus/k8v-x_se/acpi_tables.c	(working copy)
@@ -7,6 +7,7 @@
  * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
  * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -30,20 +31,21 @@
 #include <device/device.h>
 #include <device/pci_ids.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
+#include "southbridge/via/k8t800/k8t800.h"
 
 extern const unsigned char AmlCode[];
 
+
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	device_t dev;
 	struct resource *res;
 
-	dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T800_5, 0);
 	if (!dev)
 		return current;
 
-	res = find_resource(dev, K8T890_MMCONFIG_MBAR);
+	res = find_resource(dev, K8T800_MMCONFIG_MBAR);
 	if (res) {
 		current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
 				current, res->base, 0x0, 0x0, 0xff);
@@ -64,7 +66,7 @@
 
 	/* Write NB IOAPIC. */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
+				K8T800_APIC_ID, K8T800_APIC_BASE, gsi_base);
 
 	/* IRQ9 ACPI active low. */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
Index: src/mainboard/asus/k8v-x_se/dsdt.asl
===================================================================
--- src/mainboard/asus/k8v-x_se/dsdt.asl	(revision 6252)
+++ src/mainboard/asus/k8v-x_se/dsdt.asl	(working copy)
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,7 +29,6 @@
 	Scope (\_PR)
 	{
 		Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
-		Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
 	}
 
 	/* For now only define 2 power states:
@@ -53,18 +53,22 @@
 			/* PCI Routing Table */
 			/* aaa */
 			Name (_PRT, Package () {
-				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
-				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
-				Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
-				Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
-				Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
-				Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
-				Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
-				Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
-				Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
-				Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
-				Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
-				Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
+				Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xA */
+				Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x11 },
+				Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x12 },
+				Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x13 },
+				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xB */
+				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x12 },
+				Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x13 },
+				Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x10 },
+				Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xC */
+				Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x13 },
+				Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x10 },
+				Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x11 },
+				Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xD */
+				Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x10 },
+				Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x11 },
+				Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x12 },
 				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
 				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
 				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
@@ -72,81 +76,14 @@
 				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
 				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
 				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
-				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
 				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
 				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
 				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
-				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
 				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
 				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
 				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }  /* IRQ43 */
 			})
 
-			Device (PEGG)
-			{
-				Name (_ADR, 0x00020000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x02)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
-				})
-			}
-
-			Device (PEX0)
-			{
-				Name (_ADR, 0x00030000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x03)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
-				})
-			}
-
-			Device (PEX1)
-			{
-				Name (_ADR, 0x00030001)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x04)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
-				})
-			}
-
-			Device (PEX2)
-			{
-				Name (_ADR, 0x00030002)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x05)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
-				})
-			}
-
-			Device (PEX3)
-			{
-				Name (_ADR, 0x00030003)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x06)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
-				})
-			}
-
 			Device (ISA) {
 				Name (_ADR, 0x00110000)
 
Index: src/mainboard/asus/k8v-x_se/mainboard.c
===================================================================
--- src/mainboard/asus/k8v-x_se/mainboard.c	(revision 6252)
+++ src/mainboard/asus/k8v-x_se/mainboard.c	(working copy)
@@ -24,5 +24,5 @@
 #include "chip.h"
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("ASUS A8V-E SE Mainboard")
+	CHIP_NAME("ASUS K8V_X SE Mainboard")
 };
