<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40">
<head>
<meta http-equiv=Content-Type content="text/html; charset=us-ascii">
<meta name=Generator content="Microsoft Word 11 (filtered medium)">
<!--[if !mso]>
<style>
v\:* {behavior:url(#default#VML);}
o\:* {behavior:url(#default#VML);}
w\:* {behavior:url(#default#VML);}
.shape {behavior:url(#default#VML);}
</style>
<![endif]-->
<style>
<!--
/* Font Definitions */
@font-face
{font-family:SimSun;
panose-1:2 1 6 0 3 1 1 1 1 1;}
@font-face
{font-family:Tahoma;
panose-1:2 11 6 4 3 5 4 4 2 4;}
@font-face
{font-family:"\@SimSun";
panose-1:2 1 6 0 3 1 1 1 1 1;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:SimSun;}
a:link, span.MsoHyperlink
{color:blue;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{color:purple;
text-decoration:underline;}
p
{mso-margin-top-alt:auto;
margin-right:0in;
mso-margin-bottom-alt:auto;
margin-left:0in;
font-size:12.0pt;
font-family:SimSun;}
pre
{margin:0in;
margin-bottom:.0001pt;
font-size:12.0pt;
font-family:SimSun;}
span.EmailStyle19
{mso-style-type:personal-reply;
font-family:Arial;
color:blue;
font-weight:normal;
font-style:normal;
text-decoration:none none;}
@page Section1
{size:8.5in 11.0in;
margin:1.0in 1.25in 1.0in 1.25in;}
div.Section1
{page:Section1;}
-->
</style>
<!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]-->
</head>
<body lang=EN-US link=blue vlink=purple>
<div class=Section1>
<div>
<div class=MsoNormal align=center style='text-align:center'><font size=3
face=SimSun><span style='font-size:12.0pt'>
<hr size=2 width="100%" align=center tabindex=-1>
</span></font></div>
<p class=MsoNormal><b><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma;font-weight:bold'>From:</span></font></b><font size=2
face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma'>
coreboot-bounces+scott=notabs.org@coreboot.org
[mailto:coreboot-bounces+scott=notabs.org@coreboot.org] <b><span
style='font-weight:bold'>On Behalf Of </span></b>Zheng Bao<br>
<b><span style='font-weight:bold'>Sent:</span></b> Friday, January 14, 2011
07:51 AM<br>
<b><span style='font-weight:bold'>To:</span></b> coreboot@coreboot.org<br>
<b><span style='font-weight:bold'>Subject:</span></b> Re: [coreboot] [patch]
AMD MCT DDR3 for register DIMMs</span></font><o:p></o:p></p>
</div>
<p class=MsoNormal><font size=3 face=SimSun><span style='font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=MsoNormal style='margin-bottom:12.0pt'><font size=2 color=blue
face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma;color:blue'>]</span></font><font
size=2 face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma'>ping.<br>
<font color=blue><span style='color:blue'>]</span></font>Any comment before it
is drowned?<br>
<br>
<font color=blue><span style='color:blue'>]</span></font>Zheng<font color=blue><span
style='color:blue'><o:p></o:p></span></font></span></font></p>
<p class=MsoNormal style='margin-bottom:12.0pt'><font size=2 color=blue
face=Arial><span style='font-size:10.0pt;font-family:Arial;color:blue'>Hello
Bao Zheng,<o:p></o:p></span></font></p>
<p class=MsoNormal style='margin-bottom:12.0pt'><font size=2 color=blue
face=Arial><span style='font-size:10.0pt;font-family:Arial;color:blue'>I do not
have a setup for testing with registered DIMMs. But I will ack the patch
based on that fact that you have the latest agesa code and a way to test.<o:p></o:p></span></font></p>
<p class=MsoNormal style='margin-bottom:12.0pt'><font size=2 color=blue
face=Arial><span style='font-size:10.0pt;font-family:Arial;color:blue'>Acked-by:
Scott Duplichan <scott@notabs.org><o:p></o:p></span></font></p>
<p class=MsoNormal style='margin-bottom:12.0pt'><font size=2 color=blue
face=Arial><span style='font-size:10.0pt;font-family:Arial;color:blue'>Thanks,<br>
Scott</span></font><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma'><br>
<br>
<br>
Date: Mon, 10 Jan 2011 13:29:49 +0800<br>
From: Zheng.Bao@amd.com<br>
To: coreboot@coreboot.org<br>
Subject: [coreboot] [patch] AMD MCT DDR3 for register DIMMs<o:p></o:p></span></font></p>
<pre><font size=3 face=SimSun><span style='font-size:12.0pt'>The code is tested on my board with register DIMMs. More tests need to<br>
be<br>
done. Please send the testing report.<br>
<br>
Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set<br>
to a higher limit, otherwise the frequnce will be set as 400MHz.<br>
<br>
Signed-off-by: Zheng Bao <zheng.bao@amd.com><br>
<br>
Index: src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c<br>
===================================================================<br>
--- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c (revision 6244)<br>
+++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c (working copy)<br>
@@ -86,7 +86,7 @@<br>
procConifg(pMCTData,pDCTData, dimm, pass);<br>
/* 5. Begin write levelization training:<br>
* Program F2x[1, 0]9C_x08[WrtLevelTrEn]=1. */<br>
- if (pDCTData->LogicalCPUID & AMD_DR_Cx)<br>
+ if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))<br>
set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,<br>
pDCTData->NodeId, FUN_DCT,<br>
DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn,<br>
WrtLvTrEn, 1);<br>
else<br>
@@ -656,9 +656,9 @@<br>
programODT(pMCTData, pDCTData, dimm);<br>
<br>
/* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */<br>
- if (pDCTData->LogicalCPUID & AMD_DR_Cx)<br>
+ if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))<br>
set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,<br>
pDCTData->NodeId, FUN_DCT,<br>
- DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,<br>
WrLvOdtEn,(u32) 1);<br>
+ DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,<br>
WrLvOdtEn, (u32)1);<br>
else<br>
{<br>
/* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg<br>
offset 0 for Rev.B*/<br>
@@ -722,7 +722,36 @@<br>
<br>
pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;<br>
ByteLane++;<br>
}<br>
+ } else if (pDCTData->Status[DCT_STATUS_REGISTERED]) {<br>
/* For Pass 2 */<br>
+ /* From BKDG, Write Leveling Seed Value. */<br>
+ /* TODO: The unbuffered DIMMs are unstable on the code<br>
below. So temporarily it is<br>
+ * only for registered DIMMs. */<br>
+ u32 RegisterDelay, SeedTotal;<br>
+ u8 MemClkFreq;<br>
+ u16 freq_tab[] = {400, 533, 667, 800};<br>
+ while(ByteLane < MAX_BYTE_LANES)<br>
+ {<br>
+ MemClkFreq = get_Bits(pDCTData,<br>
pDCTData->CurrDct, pDCTData->NodeId,<br>
+ FUN_DCT, DRAM_CONFIG_HIGH,<br>
0, 2);<br>
+ if (pDCTData->Status[DCT_STATUS_REGISTERED])<br>
+ RegisterDelay = 0x20; /* TODO: ((RCW2 &<br>
BIT0) == 0) ? 0x20 : 0x30; */<br>
+ else<br>
+ RegisterDelay = 0;<br>
+ SeedTotal =<br>
(pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1F) |<br>
+<br>
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5;<br>
+ /* SeedTotalPreScaling = (the total delay value<br>
in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization<br>
+ training) - RegisterDelay. */<br>
+ /* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz;<br>
6: 800Mhz */<br>
+ SeedTotal = (u16) (RegisterDelay + ((((u32)<br>
SeedTotal - RegisterDelay) *<br>
+<br>
freq_tab[MemClkFreq-3]) / 400));<br>
+ Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2;<br>
+ Seed_Fine = SeedTotal & 0x1F;<br>
+<br>
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;<br>
+<br>
pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;<br>
+ ByteLane ++;<br>
+ }<br>
}<br>
+<br>
setWLByteDelay(pDCTData, ByteLane, dimm, 0);<br>
}<br>
<br>
Index: src/northbridge/amd/amdmct/mct_ddr3/mctwl.c<br>
===================================================================<br>
--- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c (revision 6246)<br>
+++ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c (working copy)<br>
@@ -342,7 +342,21 @@<br>
mct_Wait(250);<br>
<br>
if (pDCTstat->Status & (1 << SB_Registered)) {<br>
- /* TODO: Assuming the dct==0. The agesa here is<br>
confusing. */<br>
+ u8 DCT0Present, DCT1Present;<br>
+<br>
+ DCT0Present = pDCTstat->DIMMValidDCT[0];<br>
+ if (pDCTstat->GangedMode)<br>
+ DCT1Present = 0;<br>
+ else<br>
+ DCT1Present = pDCTstat->DIMMValidDCT[1];<br>
+<br>
+ if (!DCT1Present)<br>
+ pDCTstat->CSPresent =<br>
pDCTstat->CSPresent_DCT[0];<br>
+ else if (pDCTstat->GangedMode) {<br>
+ pDCTstat->CSPresent = 0;<br>
+ } else<br>
+ pDCTstat->CSPresent =<br>
pDCTstat->CSPresent_DCT[1];<br>
+<br>
FreqChgCtrlWrd(pMCTstat, pDCTstat);<br>
}<br>
}<o:p></o:p></span></font></pre>
<p class=MsoNormal><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma'><br>
-- coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot <o:p></o:p></span></font></p>
</div>
</body>
</html>