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ping.<BR>
Any comment before it is drowned?<BR>
<BR>
Zheng<BR>
<BR> <BR>
Date: Mon, 10 Jan 2011 13:29:49 +0800<BR>From: Zheng.Bao@amd.com<BR>To: coreboot@coreboot.org<BR>Subject: [coreboot] [patch] AMD MCT DDR3 for register DIMMs<BR><BR><PRE>The code is tested on my board with register DIMMs. More tests need to<BR>be<BR>done. Please send the testing report.<BR> <BR>Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set<BR>to a higher limit, otherwise the frequnce will be set as 400MHz.<BR> <BR>Signed-off-by: Zheng Bao <zheng.bao@amd.com><BR> <BR>Index: src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c<BR>===================================================================<BR>--- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c (revision 6244)<BR>+++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c (working copy)<BR>@@ -86,7 +86,7 @@<BR> procConifg(pMCTData,pDCTData, dimm, pass);<BR> /* 5. Begin write levelization training:<BR> * Program F2x[1, 0]9C_x08[WrtLevelTrEn]=1. */<BR>- if (pDCTData->LogicalCPUID & AMD_DR_Cx)<BR>+ if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))<BR> set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,<BR>pDCTData->NodeId, FUN_DCT,<BR> DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn,<BR>WrtLvTrEn, 1);<BR> else<BR>@@ -656,9 +656,9 @@<BR> programODT(pMCTData, pDCTData, dimm);<BR> <BR> /* Program F2x[1,0]9C_x08[WrLvOdtEn]=1 */<BR>- if (pDCTData->LogicalCPUID & AMD_DR_Cx)<BR>+ if (pDCTData->LogicalCPUID & (AMD_DR_Cx | AMD_DR_Dx))<BR> set_DCT_ADDR_Bits(pDCTData, pDCTData->DctTrain,<BR>pDCTData->NodeId, FUN_DCT,<BR>- DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,<BR>WrLvOdtEn,(u32) 1);<BR>+ DRAM_ADD_DCT_PHY_CONTROL_REG, WrLvOdtEn,<BR>WrLvOdtEn, (u32)1);<BR> else<BR> {<BR> /* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg<BR>offset 0 for Rev.B*/<BR>@@ -722,7 +722,36 @@<BR> <BR>pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;<BR> ByteLane++;<BR> }<BR>+ } else if (pDCTData->Status[DCT_STATUS_REGISTERED]) {<BR>/* For Pass 2 */<BR>+ /* From BKDG, Write Leveling Seed Value. */<BR>+ /* TODO: The unbuffered DIMMs are unstable on the code<BR>below. So temporarily it is<BR>+ * only for registered DIMMs. */<BR>+ u32 RegisterDelay, SeedTotal;<BR>+ u8 MemClkFreq;<BR>+ u16 freq_tab[] = {400, 533, 667, 800};<BR>+ while(ByteLane < MAX_BYTE_LANES)<BR>+ {<BR>+ MemClkFreq = get_Bits(pDCTData,<BR>pDCTData->CurrDct, pDCTData->NodeId,<BR>+ FUN_DCT, DRAM_CONFIG_HIGH,<BR>0, 2);<BR>+ if (pDCTData->Status[DCT_STATUS_REGISTERED])<BR>+ RegisterDelay = 0x20; /* TODO: ((RCW2 &<BR>BIT0) == 0) ? 0x20 : 0x30; */<BR>+ else<BR>+ RegisterDelay = 0;<BR>+ SeedTotal =<BR>(pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1F) |<BR>+<BR>pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5;<BR>+ /* SeedTotalPreScaling = (the total delay value<BR>in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization<BR>+ training) - RegisterDelay. */<BR>+ /* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz;<BR>6: 800Mhz */<BR>+ SeedTotal = (u16) (RegisterDelay + ((((u32)<BR>SeedTotal - RegisterDelay) *<BR>+<BR>freq_tab[MemClkFreq-3]) / 400));<BR>+ Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2;<BR>+ Seed_Fine = SeedTotal & 0x1F;<BR>+<BR>pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;<BR>+<BR>pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;<BR>+ ByteLane ++;<BR>+ }<BR> }<BR>+<BR> setWLByteDelay(pDCTData, ByteLane, dimm, 0);<BR> }<BR> <BR>Index: src/northbridge/amd/amdmct/mct_ddr3/mctwl.c<BR>===================================================================<BR>--- src/northbridge/amd/amdmct/mct_ddr3/mctwl.c (revision 6246)<BR>+++ src/northbridge/amd/amdmct/mct_ddr3/mctwl.c (working copy)<BR>@@ -342,7 +342,21 @@<BR> mct_Wait(250);<BR> <BR> if (pDCTstat->Status & (1 << SB_Registered)) {<BR>- /* TODO: Assuming the dct==0. The agesa here is<BR>confusing. */<BR>+ u8 DCT0Present, DCT1Present;<BR>+<BR>+ DCT0Present = pDCTstat->DIMMValidDCT[0];<BR>+ if (pDCTstat->GangedMode)<BR>+ DCT1Present = 0;<BR>+ else<BR>+ DCT1Present = pDCTstat->DIMMValidDCT[1];<BR>+<BR>+ if (!DCT1Present)<BR>+ pDCTstat->CSPresent =<BR>pDCTstat->CSPresent_DCT[0];<BR>+ else if (pDCTstat->GangedMode) {<BR>+ pDCTstat->CSPresent = 0;<BR>+ } else<BR>+ pDCTstat->CSPresent =<BR>pDCTstat->CSPresent_DCT[1];<BR>+<BR> FreqChgCtrlWrd(pMCTstat, pDCTstat);<BR> }<BR> }<BR></PRE><BR>-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot </body>
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