Yes, I copied the following:<br>- board used as template was mainboard/iei/pcisa-lx-800-r10/<br>- superio used as template was superio/fintek/f71805f/<br>- irq_tables.c used as template was mainboard/digitallogic/msm800sev/<br>
I did not sign it because is not a real patch yet; just showing what source I'm using for this board. Any hints with the PIRQ map?<br><br>Regards,<br>Cristian<br><br><div class="gmail_quote">On Wed, Jan 19, 2011 at 9:15 AM, Stefan Reinauer <span dir="ltr"><<a href="mailto:stefan.reinauer@coreboot.org">stefan.reinauer@coreboot.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">* Cristian Craciunescu <<a href="mailto:ccristian@gmail.com">ccristian@gmail.com</a>> [110118 09:37]:<br>
><br>
> Patch bellow:<br>
><br>
<br>
<br>
did you create the board, superio etc by copying another component?<br>
If so, which one? Then we can svn copy and it's easier to see the<br>
differences.<br>
<br>
Also, you need to sign off the patch:<br>
<a href="http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure" target="_blank">http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure</a><br>
<div><div></div><div class="h5"><br>
> Index: src/superio/fintek/Kconfig<br>
> ===================================================================<br>
> --- src/superio/fintek/Kconfig (revision 6237)<br>
> +++ src/superio/fintek/Kconfig (working copy)<br>
> @@ -27,3 +27,5 @@<br>
> bool<br>
> config SUPERIO_FINTEK_F71889<br>
> bool<br>
> +config SUPERIO_FINTEK_F81216<br>
> + bool<br>
> Index: src/superio/fintek/Makefile.inc<br>
> ===================================================================<br>
> --- src/superio/fintek/Makefile.inc (revision 6237)<br>
> +++ src/superio/fintek/Makefile.inc (working copy)<br>
> @@ -22,3 +22,4 @@<br>
> subdirs-y += f71863fg<br>
> subdirs-y += f71872<br>
> subdirs-y += f71889<br>
> +subdirs-y += f81216<br>
> Index: src/superio/fintek/f81216/Makefile.inc<br>
> ===================================================================<br>
> --- src/superio/fintek/f81216/Makefile.inc (revision 0)<br>
> +++ src/superio/fintek/f81216/Makefile.inc (revision 0)<br>
> @@ -0,0 +1,22 @@<br>
> +##<br>
> +## This file is part of the coreboot project.<br>
> +##<br>
> +## Copyright (C) 2008 Corey Osgood <<a href="mailto:corey.osgood@gmail.com">corey.osgood@gmail.com</a>><br>
> +##<br>
> +## This program is free software; you can redistribute it and/or modify<br>
> +## it under the terms of the GNU General Public License as published by<br>
> +## the Free Software Foundation; either version 2 of the License, or<br>
> +## (at your option) any later version.<br>
> +##<br>
> +## This program is distributed in the hope that it will be useful,<br>
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> +## GNU General Public License for more details.<br>
> +##<br>
> +## You should have received a copy of the GNU General Public License<br>
> +## along with this program; if not, write to the Free Software<br>
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> +##<br>
> +<br>
> +ramstage-$(CONFIG_SUPERIO_FINTEK_F81216) += superio.c<br>
> +<br>
> Index: src/superio/fintek/f81216/superio.c<br>
> ===================================================================<br>
> --- src/superio/fintek/f81216/superio.c (revision 0)<br>
> +++ src/superio/fintek/f81216/superio.c (revision 0)<br>
> @@ -0,0 +1,116 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2008 Corey Osgood <<a href="mailto:corey.osgood@gmail.com">corey.osgood@gmail.com</a>><br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License as published by<br>
> + * the Free Software Foundation; either version 2 of the License, or<br>
> + * (at your option) any later version.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +#include <arch/io.h><br>
> +#include <device/device.h><br>
> +#include <device/pnp.h><br>
> +#include <console/console.h><br>
> +#include <stdlib.h><br>
> +#include <uart8250.h><br>
> +#include "chip.h"<br>
> +#include "f81216.h"<br>
> +<br>
> +static void pnp_enter_conf_state(device_t dev)<br>
> +{<br>
> + outb(0x77, dev->path.pnp.port);<br>
> + outb(0x77, dev->path.pnp.port);<br>
> +}<br>
> +<br>
> +static void pnp_exit_conf_state(device_t dev)<br>
> +{<br>
> + outb(0xaa, dev->path.pnp.port);<br>
> +}<br>
> +<br>
> +static void f81216_init(device_t dev)<br>
> +{<br>
> + struct superio_fintek_f81216_config *conf = dev->chip_info;<br>
> + struct resource *res0;<br>
> +<br>
> + if (!dev->enabled)<br>
> + return;<br>
> +<br>
> + switch(dev->path.pnp.device) {<br>
> + /* TODO: Might potentially need code for HWM or FDC etc. */<br>
> + case F81216_SP1:<br>
> + res0 = find_resource(dev, PNP_IDX_IO0);<br>
> + init_uart8250(res0->base, &conf->com1);<br>
> + break;<br>
> + case F81216_SP2:<br>
> + res0 = find_resource(dev, PNP_IDX_IO0);<br>
> + init_uart8250(res0->base, &conf->com2);<br>
> + break;<br>
> + case F81216_SP3:<br>
> + res0 = find_resource(dev, PNP_IDX_IO0);<br>
> + init_uart8250(res0->base, &conf->com3);<br>
> + break;<br>
> + case F81216_SP4:<br>
> + res0 = find_resource(dev, PNP_IDX_IO0);<br>
> + init_uart8250(res0->base, &conf->com4);<br>
> + break;<br>
> + }<br>
> +}<br>
> +<br>
> +static void f81216_pnp_set_resources(device_t dev)<br>
> +{<br>
> + pnp_enter_conf_state(dev);<br>
> + pnp_set_resources(dev);<br>
> + pnp_exit_conf_state(dev);<br>
> +}<br>
> +<br>
> +static void f81216_pnp_enable_resources(device_t dev)<br>
> +{<br>
> + pnp_enter_conf_state(dev);<br>
> + pnp_enable_resources(dev);<br>
> + pnp_exit_conf_state(dev);<br>
> +}<br>
> +<br>
> +static void f81216_pnp_enable(device_t dev)<br>
> +{<br>
> + pnp_enter_conf_state(dev);<br>
> + pnp_set_logical_device(dev);<br>
> + (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);<br>
> + pnp_exit_conf_state(dev);<br>
> +}<br>
> +<br>
> +static struct device_operations ops = {<br>
> + .read_resources = pnp_read_resources,<br>
> + .set_resources = f81216_pnp_set_resources,<br>
> + .enable_resources = f81216_pnp_enable_resources,<br>
> + .enable = f81216_pnp_enable,<br>
> + .init = f81216_init,<br>
> +};<br>
> +<br>
> +static struct pnp_info pnp_dev_info[] = {<br>
> + /* TODO: Some of the 0x07f8 etc. values may not be correct. */<br>
> + { &ops, F81216_SP1, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },<br>
> + { &ops, F81216_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },<br>
> + { &ops, F81216_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },<br>
> + { &ops, F81216_SP4, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },<br>
> +};<br>
> +<br>
> +static void enable_dev(device_t dev)<br>
> +{<br>
> + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);<br>
> +}<br>
> +<br>
> +struct chip_operations superio_fintek_f81216_ops = {<br>
> + CHIP_NAME("Fintek F81216 Super I/O")<br>
> + .enable_dev = enable_dev<br>
> +};<br>
> Index: src/superio/fintek/f81216/chip.h<br>
> ===================================================================<br>
> --- src/superio/fintek/f81216/chip.h (revision 0)<br>
> +++ src/superio/fintek/f81216/chip.h (revision 0)<br>
> @@ -0,0 +1,35 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2007 Corey Osgood <<a href="mailto:corey@slightlyhackish.com">corey@slightlyhackish.com</a>><br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License as published by<br>
> + * the Free Software Foundation; either version 2 of the License, or<br>
> + * (at your option) any later version.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +#ifndef SUPERIO_FINTEK_F81216_CHIP_H<br>
> +#define SUPERIO_FINTEK_F81216_CHIP_H<br>
> +<br>
> +#include <device/device.h><br>
> +#include <uart8250.h><br>
> +<br>
> +/* This chip doesn't have keyboard and mouse support. */<br>
> +<br>
> +extern struct chip_operations superio_fintek_f81216_ops;<br>
> +<br>
> +struct superio_fintek_f81216_config {<br>
> + struct uart8250 com1, com2, com3, com4;<br>
> +};<br>
> +<br>
> +#endif<br>
> Index: src/superio/fintek/f81216/early_serial.c<br>
> ===================================================================<br>
> --- src/superio/fintek/f81216/early_serial.c (revision 0)<br>
> +++ src/superio/fintek/f81216/early_serial.c (revision 0)<br>
> @@ -0,0 +1,59 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2007 Corey Osgood <<a href="mailto:corey@slightlyhackish.com">corey@slightlyhackish.com</a>><br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License as published by<br>
> + * the Free Software Foundation; either version 2 of the License, or<br>
> + * (at your option) any later version.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */<br>
> +<br>
> +#include <arch/romcc_io.h><br>
> +#include "f81216.h"<br>
> +<br>
> +static void pnp_enter_conf_state(device_t dev)<br>
> +{<br>
> + u16 port = dev >> 8;<br>
> + outb(0x77, port);<br>
> + outb(0x77, port);<br>
> +}<br>
> +<br>
> +/*<br>
> + * Acording to documentation of Fintek device<br>
> + * we must set the clock option first(we set 48Mhz)<br>
> + */<br>
> +static void pnp_set_clock(device_t dev)<br>
> +{<br>
> + u16 port = dev >> 8;<br>
> + outb(0x25, port);<br>
> + outb(0x01, port + 1);<br>
> +}<br>
> +<br>
> +static void pnp_exit_conf_state(device_t dev)<br>
> +{<br>
> + u16 port = dev >> 8;<br>
> + outb(0xaa, port);<br>
> +}<br>
> +<br>
> +static void f81216_enable_serial(device_t dev, u16 iobase)<br>
> +{<br>
> + pnp_enter_conf_state(dev);<br>
> + pnp_set_clock(dev);<br>
> + pnp_set_logical_device(dev);<br>
> + pnp_set_enable(dev, 0);<br>
> + pnp_set_iobase(dev, PNP_IDX_IO0, iobase);<br>
> + pnp_set_enable(dev, 1);<br>
> + pnp_exit_conf_state(dev);<br>
> +}<br>
> Index: src/superio/fintek/f81216/f81216.h<br>
> ===================================================================<br>
> --- src/superio/fintek/f81216/f81216.h (revision 0)<br>
> +++ src/superio/fintek/f81216/f81216.h (revision 0)<br>
> @@ -0,0 +1,38 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2007 Corey Osgood <<a href="mailto:corey@slightlyhackish.com">corey@slightlyhackish.com</a>><br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License as published by<br>
> + * the Free Software Foundation; either version 2 of the License, or<br>
> + * (at your option) any later version.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +#ifndef SUPERIO_FINTEK_F81216_H<br>
> +#define SUPERIO_FINTEK_F81216_H<br>
> +<br>
> +/*<br>
> + * Datasheet:<br>
> + * - Name: F71805F/FG Super H/W Monitor + LPC IO<br>
> + * - URL: <a href="http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17" target="_blank">http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17</a><br>
> + * - PDF: <a href="http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf" target="_blank">http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf</a><br>
> + * - Revision: V0.25P<br>
> + */<br>
> +<br>
> +/* Logical Device Numbers (LDN). */<br>
> +#define F81216_SP1 0x00 /* UART1 */<br>
> +#define F81216_SP2 0x01 /* UART2 */<br>
> +#define F81216_SP3 0x02 /* UART3 */<br>
> +#define F81216_SP4 0x03 /* UART4 */<br>
> +<br>
> +#endif<br>
> Index: src/mainboard/jetway/Kconfig<br>
> ===================================================================<br>
> --- src/mainboard/jetway/Kconfig (revision 6237)<br>
> +++ src/mainboard/jetway/Kconfig (working copy)<br>
> @@ -7,11 +7,14 @@<br>
> bool "J7F24"<br>
> config BOARD_JETWAY_PA78VM5<br>
> bool "PA78VM5 (Fam10)"<br>
> +config BOARD_JETWAY_J8<br>
> + bool "J8 Nano-ITX"<br>
><br>
> endchoice<br>
><br>
> source "src/mainboard/jetway/j7f24/Kconfig"<br>
> source "src/mainboard/jetway/pa78vm5/Kconfig"<br>
> +source "src/mainboard/jetway/j8/Kconfig"<br>
><br>
> config MAINBOARD_VENDOR<br>
> string<br>
> Index: src/mainboard/jetway/j8/Kconfig<br>
> ===================================================================<br>
> --- src/mainboard/jetway/j8/Kconfig (revision 0)<br>
> +++ src/mainboard/jetway/j8/Kconfig (revision 0)<br>
> @@ -0,0 +1,28 @@<br>
> +if BOARD_JETWAY_J8<br>
> +<br>
> +config BOARD_SPECIFIC_OPTIONS # dummy<br>
> + def_bool y<br>
> + select ARCH_X86<br>
> + select CPU_AMD_LX<br>
> + select NORTHBRIDGE_AMD_LX<br>
> + select SOUTHBRIDGE_AMD_CS5536<br>
> +# select SUPERIO_WINBOND_W83627HF<br>
> + select SUPERIO_FINTEK_F81216<br>
> + select HAVE_PIRQ_TABLE<br>
> + select PIRQ_ROUTE<br>
> + select BOARD_ROMSIZE_KB_256<br>
> + select POWER_BUTTON_FORCE_ENABLE<br>
> +<br>
> +config MAINBOARD_DIR<br>
> + string<br>
> + default jetway/j8<br>
> +<br>
> +config MAINBOARD_PART_NUMBER<br>
> + string<br>
> + default "PCISA-LX-800-R10"<br>
> +<br>
> +config IRQ_SLOT_COUNT<br>
> + int<br>
> + default 9<br>
> +<br>
> +endif # BOARD_JETWAY_J8<br>
> Index: src/mainboard/jetway/j8/devicetree.cb<br>
> ===================================================================<br>
> --- src/mainboard/jetway/j8/devicetree.cb (revision 0)<br>
> +++ src/mainboard/jetway/j8/devicetree.cb (revision 0)<br>
> @@ -0,0 +1,58 @@<br>
> +chip northbridge/amd/lx<br>
> + device pci_domain 0 on<br>
> + device pci 1.0 on end # Northbridge<br>
> + device pci 1.1 on end # Graphics<br>
> + chip southbridge/amd/cs5536<br>
> + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK<br>
> + # SIRQ Mode = Active(Quiet) mode. Save power....<br>
> + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse,<br>
> UARTs, etc IRQs. OK<br>
> + register "lpc_serirq_enable" = "0x000011fa"<br>
> + register "lpc_serirq_polarity" = "0x0000EF05"<br>
> + register "lpc_serirq_mode" = "1"<br>
> + register "enable_gpio_int_route" = "0x0D0C0700"<br>
> + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash<br>
> + register "com1_enable" = "0"<br>
> + register "com1_address" = "0x3F8"<br>
> + register "com1_irq" = "4"<br>
> + register "com2_enable" = "0"<br>
> + register "com2_address" = "0x2F8"<br>
> + register "com2_irq" = "3"<br>
> + register "enable_USBP4_device" = "1" # 0: host, 1:device<br>
> + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent<br>
> setting CS5536 Data Book (pages 380-381)<br>
> + register "unwanted_vpci[0]" = "0" # End of list has a zero<br>
> + device pci d.0 on end # Ethernet 1<br>
> + device pci f.0 on # ISA Bridge<br>
> + chip superio/fintek/f81216<br>
> + device pnp 4e.0 on # Com1<br>
> + io 0x60 = 0x3f8<br>
> + irq 0x70 = 3<br>
> + end<br>
> + device pnp 4e.1 on # Com2<br>
> + io 0x60 = 0x2f8<br>
> + irq 0x70 = 4<br>
> + end<br>
> + device pnp 4e.2 on # Com3<br>
> + io 0x60 = 0x3e8<br>
> + irq 0x70 = 5<br>
> + end<br>
> + device pnp 4e.3 on # Com4<br>
> + io 0x60 = 0x2e8<br>
> + irq 0x70 = 7<br>
> + end<br>
> + end<br>
> + end<br>
> +<br>
> + device pci f.2 on end # IDE Controller<br>
> + device pci f.3 on end # Audio<br>
> + device pci f.4 on end # OHCI<br>
> + device pci f.5 on end # EHCI<br>
> + end<br>
> + end<br>
> + # APIC cluster is late CPU init.<br>
> + device lapic_cluster 0 on<br>
> + chip cpu/amd/model_lx<br>
> + device lapic 0 on end<br>
> + end<br>
> + end<br>
> +end<br>
> +<br>
> Index: src/mainboard/jetway/j8/romstage.c<br>
> ===================================================================<br>
> --- src/mainboard/jetway/j8/romstage.c (revision 0)<br>
> +++ src/mainboard/jetway/j8/romstage.c (revision 0)<br>
> @@ -0,0 +1,98 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License as published by<br>
> + * the Free Software Foundation; either version 2 of the License, or<br>
> + * (at your option) any later version.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +#include <stdint.h><br>
> +#include <stdlib.h><br>
> +#include <device/pci_def.h><br>
> +#include <arch/io.h><br>
> +#include <device/pnp_def.h><br>
> +#include <arch/hlt.h><br>
> +#include <console/console.h><br>
> +#include "cpu/x86/bist.h"<br>
> +#include "cpu/x86/msr.h"<br>
> +#include <cpu/amd/lxdef.h><br>
> +#include <cpu/amd/geode_post_code.h><br>
> +#include "southbridge/amd/cs5536/cs5536.h"<br>
> +#include <spd.h><br>
> +#include "southbridge/amd/cs5536/early_smbus.c"<br>
> +#include "southbridge/amd/cs5536/early_setup.c"<br>
> +#include "superio/fintek/f81216/early_serial.c"<br>
> +#include "arch/x86/include/arch/llshell.h"<br>
> +<br>
> +#define SERIAL_DEV PNP_DEV(0x4e, F81216_SP1)<br>
> +<br>
> +static inline int spd_read_byte(unsigned int device, unsigned int address)<br>
> +{<br>
> + return smbus_read_byte(device, address);<br>
> +}<br>
> +<br>
> +#define ManualConf 1 /* Do automatic strapped PLL config */<br>
> +#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/<br>
> +////#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/<br>
> +//#define PLLMSRhi 0x0000049e<br>
> +//#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/<br>
> +//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0<br>
> +/* Hold Count - how long we will sit in reset */<br>
> +#define PLLMSRlo 0x00DE6000<br>
> +<br>
> +#include "northbridge/amd/lx/raminit.h"<br>
> +#include "northbridge/amd/lx/pll_reset.c"<br>
> +#include "northbridge/amd/lx/raminit.c"<br>
> +#include "lib/generic_sdram.c"<br>
> +#include "cpu/amd/model_lx/cpureginit.c"<br>
> +#include "cpu/amd/model_lx/syspreinit.c"<br>
> +#include "cpu/amd/model_lx/msrinit.c"<br>
> +<br>
> +void main(unsigned long bist)<br>
> +{<br>
> + post_code(0x01);<br>
> +<br>
> + static const struct mem_controller memctrl[] = {<br>
> + {.channel0 = {DIMM0, DIMM1}}<br>
> + };<br>
> +<br>
> + SystemPreInit();<br>
> + msr_init();<br>
> +<br>
> + cs5536_early_setup();<br>
> +<br>
> + /* Note: must do this AFTER the early_setup! It is counting on some<br>
> + * early MSR setup for CS5536.<br>
> + */<br>
> + // Cristi<br>
> + // Need to initialize the Fintek superio for serials<br>
> + //<br>
> + f81216_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>
> + uart_init();<br>
> + console_init();<br>
> +<br>
> + /* Halt if there was a built in self test failure */<br>
> + report_bist_failure(bist);<br>
> +<br>
> + pll_reset(ManualConf);<br>
> +<br>
> + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);<br>
> +<br>
> + sdram_initialize(1, memctrl);<br>
> + llshell();<br>
> +<br>
> + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */<br>
> + return;<br>
> +}<br>
> Index: src/mainboard/jetway/j8/irq_tables.c<br>
> ===================================================================<br>
> --- src/mainboard/jetway/j8/irq_tables.c (revision 0)<br>
> +++ src/mainboard/jetway/j8/irq_tables.c (revision 0)<br>
> @@ -0,0 +1,75 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2007 Advanced Micro Devices, Inc.<br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License version 2 as<br>
> + * published by the Free Software Foundation.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +#include <arch/pirq_routing.h><br>
> +#include <console/console.h><br>
> +#include <arch/io.h><br>
> +#include <arch/pirq_routing.h><br>
> +#include "southbridge/amd/cs5536/cs5536.h"<br>
> +<br>
> +/* Platform IRQs */<br>
> +#define PIRQA 11<br>
> +#define PIRQB 5<br>
> +#define PIRQC 10<br>
> +#define PIRQD 10<br>
> +<br>
> +/* Map */<br>
> +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */<br>
> +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */<br>
> +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */<br>
> +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */<br>
> +<br>
> +/* Link */<br>
> +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */<br>
> +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */<br>
> +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */<br>
> +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */<br>
> +<br>
> +const struct irq_routing_table intel_irq_routing_table = {<br>
> + PIRQ_SIGNATURE, /* u32 signature */<br>
> + PIRQ_VERSION, /* u16 version */<br>
> + 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total<br>
> CONFIG_IRQ_SLOT_COUNT devices on the bus */<br>
> + 0x00, /* Where the interrupt router lies (bus) */<br>
> + (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */<br>
> + 0xc00, /* IRQs devoted exclusively to PCI usage */<br>
> + 0x100b, /* Vendor */<br>
> + 0x2b, /* Device */<br>
> + 0, /* Miniport data */<br>
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>
> + 0xe, /* u8 checksum. This has to be set to some<br>
> + value that would give 0 after the sum of all<br>
> + bytes for this structure (including checksum) */<br>
> + {<br>
> + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap},<br>
> {link, bitmap}, slot, rfu */<br>
> + {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000},<br>
> {0x00, 0x00000}}, 0x0, 0x0},<br>
> + {0x00,(0x0f<<3)|0x0, {{0x00, 0x0000}, {0x02, 0x0400}, {0x00, 0x0000},<br>
> {0x04, 0x00400}}, 0x0, 0x0},<br>
> + {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000},<br>
> {0x00, 0x00000}}, 0x0, 0x0},<br>
> + {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000},<br>
> {0x00, 0x00000}}, 0x0, 0x0},<br>
> + {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000},<br>
> {0x00, 0x00000}}, 0x0, 0x0},<br>
> + {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400},<br>
> {0x04, 0x00800}}, 0x1, 0x0},<br>
> + {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800},<br>
> {0x01, 0x00400}}, 0x2, 0x0},<br>
> + {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400},<br>
> {0x02, 0x00800}}, 0x3, 0x0},<br>
> + {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800},<br>
> {0x03, 0x00400}}, 0x4, 0x0},<br>
> + }<br>
> +};<br>
> +<br>
> +unsigned long write_pirq_routing_table(unsigned long addr)<br>
> +{<br>
> + return copy_pirq_routing_table(addr);<br>
> +}<br>
> Index: src/mainboard/jetway/j8/chip.h<br>
> ===================================================================<br>
> --- src/mainboard/jetway/j8/chip.h (revision 0)<br>
> +++ src/mainboard/jetway/j8/chip.h (revision 0)<br>
> @@ -0,0 +1,23 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2007 Nikolay Petukhov <<a href="mailto:nikolay.petukhov@gmail.com">nikolay.petukhov@gmail.com</a>><br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License as published by<br>
> + * the Free Software Foundation; either version 2 of the License, or<br>
> + * (at your option) any later version.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +extern struct chip_operations mainboard_ops;<br>
> +<br>
> +struct mainboard_config {};<br>
> Index: src/mainboard/jetway/j8/mainboard.c<br>
> ===================================================================<br>
> --- src/mainboard/jetway/j8/mainboard.c (revision 0)<br>
> +++ src/mainboard/jetway/j8/mainboard.c (revision 0)<br>
> @@ -0,0 +1,25 @@<br>
> +/*<br>
> + * This file is part of the coreboot project.<br>
> + *<br>
> + * Copyright (C) 2007 Nikolay Petukhov <<a href="mailto:nikolay.petukhov@gmail.com">nikolay.petukhov@gmail.com</a>><br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify<br>
> + * it under the terms of the GNU General Public License as published by<br>
> + * the Free Software Foundation; either version 2 of the License, or<br>
> + * (at your option) any later version.<br>
> + *<br>
> + * This program is distributed in the hope that it will be useful,<br>
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>
> + * GNU General Public License for more details.<br>
> + *<br>
> + * You should have received a copy of the GNU General Public License<br>
> + * along with this program; if not, write to the Free Software<br>
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>
> + */<br>
> +<br>
> +#include <device/device.h><br>
> +<br>
> +struct chip_operations mainboard_ops = {<br>
> + CHIP_NAME("Jetway LX-800 Mainboard")<br>
> +};<br>
> Index: src/northbridge/amd/lx/northbridge.c<br>
> ===================================================================<br>
> --- src/northbridge/amd/lx/northbridge.c (revision 6237)<br>
> +++ src/northbridge/amd/lx/northbridge.c (working copy)<br>
> @@ -412,11 +412,11 @@<br>
> cpubug();<br>
> chipsetinit();<br>
><br>
> - // print_conf();<br>
> + print_conf();<br>
><br>
> do_vsmbios(); // do the magic stuff here, so prepare your<br>
> tambourine ;)<br>
><br>
> - // print_conf();<br>
> + print_conf();<br>
><br>
> graphics_init();<br>
> pci_set_method(dev);<br>
><br>
><br>
> On Tue, Jan 18, 2011 at 10:28 AM, Cristian Craciunescu <<a href="mailto:ccristian@gmail.com">ccristian@gmail.com</a>><br>
> wrote:<br>
><br>
><br>
> I'm sure the problem is coming from PIRQ map; needs some fine tuning. The<br>
> board has four serials and all of them are connected the 81216DG super IO<br>
> chip so I'm using the first serial port, the onchip uarts are disabled.<br>
> There is an additional hwmon chip(f71858) which I did not touched<br>
> yet. Attached the patch with j8 dir in mainboard and f81216DG superio<br>
> added.<br>
><br>
><br>
><br>
><br>
> Regards,<br>
> Cristian<br>
> On Tue, Jan 18, 2011 at 10:01 AM, Cristian Craciunescu<br>
> <<a href="mailto:ccristian@gmail.com">ccristian@gmail.com</a>>wrote:<br>
><br>
> > Cristian Craciunescu wrote:<br>
> > > I've compiled suport for j8f9 board from jetw. using as template other<br>
> LX<br>
> > > mainboard. The system is booting with coreboot/seabios however the<br>
> serial<br>
> > > does not seam to work in kernel. GRUB bootloader works ok over serial<br>
> but<br>
> > as<br>
> > > soon as the linux kernel finish booting it does not respond over serial<br>
> > but<br>
> > > it can send messages to serial. Although the IRQs are detected<br>
> correctly<br>
> > > when the serial has input I can not see any irq messages incrementing<br>
> in<br>
> > > /proc/interrupts. Any hint?<br>
> ><br>
> > Something is wrong with the interrupt setup in coreboot if they are<br>
> > not being delivered to the kernel.<br>
> ><br>
> > Are you using the internal UART in CS5536 or do you have a superio?<br>
> > Which board did you use as template?<br>
> > Can you post a patch with your code so far?<br>
> ><br>
> ><br>
> > //Peter<br>
> ><br>
><br>
><br>
<br>
</div></div>> --<br>
> coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
> <a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
<br>
</blockquote></div><br>