Index: src/southbridge/intel/i3100/early_smbus.c
===================================================================
--- src/southbridge/intel/i3100/early_smbus.c	(revision 6427)
+++ src/southbridge/intel/i3100/early_smbus.c	(working copy)
@@ -35,6 +35,11 @@
 
 	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+	// Taken from the i82801ex code
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
 }
 
 static int smbus_read_byte(u32 device, u32 address)
Index: src/cpu/intel/ep80579/Kconfig
===================================================================
--- src/cpu/intel/ep80579/Kconfig	(revision 6427)
+++ src/cpu/intel/ep80579/Kconfig	(working copy)
@@ -1,3 +1,6 @@
 config CPU_INTEL_EP80579
 	bool
 	select SSE
+	select SSE2
+	select MMX
+
Index: src/cpu/intel/ep80579/Makefile.inc
===================================================================
--- src/cpu/intel/ep80579/Makefile.inc	(revision 6427)
+++ src/cpu/intel/ep80579/Makefile.inc	(working copy)
@@ -7,3 +7,5 @@
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+
Index: src/mainboard/intel/truxton/Kconfig
===================================================================
--- src/mainboard/intel/truxton/Kconfig	(revision 6427)
+++ src/mainboard/intel/truxton/Kconfig	(working copy)
@@ -8,12 +8,13 @@
 	select SOUTHBRIDGE_INTEL_I3100
 	select SUPERIO_INTEL_I3100
 	select SUPERIO_SMSC_SMSCSUPERIO
-	select ROMCC
 	select HAVE_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_2048
+	select CACHE_AS_RAM
+	#select ROMCC
 
 config MAINBOARD_DIR
 	string
@@ -31,4 +32,13 @@
 	int
 	default 4
 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+
+
 endif # BOARD_INTEL_TRUXTON
Index: src/mainboard/intel/truxton/romstage.c
===================================================================
--- src/mainboard/intel/truxton/romstage.c	(revision 6427)
+++ src/mainboard/intel/truxton/romstage.c	(working copy)
@@ -32,10 +32,10 @@
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
 #include "superio/intel/i3100/i3100.h"
-#include "cpu/x86/lapic/boot_cpu.c"
+//#include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/intel/i3100/early_serial.c"
-#include "cpu/x86/bist.h"
+//#include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
@@ -48,14 +48,12 @@
 #include "northbridge/intel/i3100/raminit_ep80579.c"
 #include "lib/generic_sdram.c"
 #include "../../intel/jarrell/debug.c"
-#include "arch/x86/lib/stages.c"
+//#include "arch/x86/lib/stages.c"
 
 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	msr_t msr;
-	u16 perf;
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -64,12 +62,12 @@
 		}
 	};
 
-	if (bist == 0) {
-		/* Skip this if there was a built in self test failure */
-		early_mtrr_init();
-		if (memory_initialized())
-			skip_romstage();
-	}
+	//if (bist == 0) {
+	//	/* Skip this if there was a built in self test failure */
+	//	//early_mtrr_init();
+	//	if (memory_initialized())
+	//		;//skip_romstage();
+	//}
 
 	/* Set up the console */
 	i3100_enable_superio();
@@ -83,16 +81,21 @@
 	i3100_halt_tco_timer();
 
 	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
+	//report_bist_failure(bist);
 
 #ifdef TRUXTON_DEBUG
+	print_debug("ECHEC?\n");
 	print_pci_devices();
+	print_debug("ECHEC!\n");
 #endif
+	print_debug("enable_smbus();\n");
 	enable_smbus();
 	dump_spd_registers();
 
 	sdram_initialize(ARRAY_SIZE(mch), mch);
+	print_debug("ECHEC IMMINENT\n");
 	dump_pci_devices();
+	print_debug("ECHEC LOL\n");
 	dump_pci_device(PCI_DEV(0, 0x00, 0));
 #ifdef TRUXTON_DEBUG
 	dump_bar14(PCI_DEV(0, 0x00, 0));
Index: src/mainboard/intel/jarrell/debug.c
===================================================================
--- src/mainboard/intel/jarrell/debug.c	(revision 6427)
+++ src/mainboard/intel/jarrell/debug.c	(working copy)
@@ -1,5 +1,6 @@
 #include <spd.h>
 
+#if 0
 static void print_reg(unsigned char index)
 {
         unsigned char data;
@@ -13,7 +14,9 @@
 	print_debug("\n");
         return;
 }
+#endif
 
+#if 0
 static void xbus_en(void)
 {
         /* select the XBUS function in the SIO */
@@ -23,7 +26,9 @@
         outb(0x01, 0x2f);
 	return;
 }
+#endif
 
+#if 0
 static void setup_func(unsigned char func)
 {
         /* select the function in the SIO */
@@ -41,7 +46,9 @@
         print_reg(0x75);
         return;
 }
+#endif
 
+#if 0
 static void siodump(void)
 {
         int i;
@@ -108,6 +115,7 @@
 #endif
         return;
 }
+#endif
 
 static void print_debug_pci_dev(unsigned dev)
 {
@@ -119,6 +127,7 @@
 	print_debug_hex8((dev >> 8) & 7);
 }
 
+#if 0
 static void print_pci_devices(void)
 {
 	device_t dev;
@@ -136,6 +145,7 @@
 		print_debug("\n");
 	}
 }
+#endif
 
 static void dump_pci_device(unsigned dev)
 {
@@ -158,6 +168,7 @@
 	}
 }
 
+#if 0
 static void dump_bar14(unsigned dev)
 {
 	int i;
@@ -185,6 +196,7 @@
 	}
 	print_debug("\n");
 }
+#endif
 
 static void dump_pci_devices(void)
 {
@@ -266,6 +278,7 @@
 }
 #endif
 
+void dump_spd_registers(void);
 void dump_spd_registers(void)
 {
         unsigned device;
@@ -278,7 +291,6 @@
 		print_debug_hex8(device);
 
                 for(i = 0; (i < 256) ; i++) {
-	                unsigned char byte;
                         if ((i % 16) == 0) {
 				print_debug("\n");
 				print_debug_hex8(i);
@@ -299,6 +311,7 @@
 	}
 }
 
+void dump_ipmi_registers(void);
 void dump_ipmi_registers(void)
 {
         unsigned device;
@@ -311,7 +324,6 @@
 		print_debug_hex8(device);
 
                 for(i = 0; (i < 8) ; i++) {
-	                unsigned char byte;
 			status = smbus_read_byte(device, 2);
                         if (status < 0) {
 			         print_debug("bad device: ");
Index: src/lib/generic_sdram.c
===================================================================
--- src/lib/generic_sdram.c	(revision 6427)
+++ src/lib/generic_sdram.c	(working copy)
@@ -11,8 +11,10 @@
 
 /* Setup SDRAM */
 #if CONFIG_RAMINIT_SYSINFO
+void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo)
 #else
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
 void sdram_initialize(int controllers, const struct mem_controller *ctrl)
 #endif
 {
Index: src/northbridge/intel/i3100/raminit_ep80579.c
===================================================================
--- src/northbridge/intel/i3100/raminit_ep80579.c	(revision 6427)
+++ src/northbridge/intel/i3100/raminit_ep80579.c	(working copy)
@@ -25,18 +25,20 @@
 
 #define BAR 0x90000000
 
+//static unsigned ram_is_ecc;
+#define ram_is_ecc 1
+
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
 	static const u32 register_values[] = {
 		PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
 		PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG,
-		PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
-		PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
+		PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, // XXX???
+		PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, // XXX???
 		PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
 		PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0,
 	};
 	int i;
-	int max;
 
 	for (i = 0; i < ARRAY_SIZE(register_values); i += 3) {
 		device_t dev;
@@ -56,11 +58,11 @@
 	u32 side2;
 };
 
-static struct dimm_size spd_get_dimm_size(u16 device)
+static struct dimm_size spd_get_dimm_size(u16 device) // dubious
 {
 	/* Calculate the log base 2 size of a DIMM in bits */
 	struct dimm_size sz;
-	int value, low, ddr2;
+	int value, low;
 	sz.side1 = 0;
 	sz.side2 = 0;
 
@@ -81,7 +83,7 @@
 	value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
 	if (value < 0) goto hw_err;
 	if ((value & 0xff) == 0) goto val_err;
-	sz.side1 += log2(value & 0xff);
+	sz.side1 += log2(value & 0xff); // XXX
 
 	/* Get the module data width and convert it to a power of two */
 	value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);
@@ -147,6 +149,7 @@
 		struct dimm_size sz;
 		if (dimm_mask & (1 << i)) {
 			sz = spd_get_dimm_size(ctrl->channel0[i]);
+			print_debug("SPD GET DIMM SIZE\n");
 			if (sz.side1 < 29) {
 				return -1; /* Report SPD error */
 			}
@@ -202,7 +205,7 @@
 			print_debug(" = ");
 			print_debug_hex8(byte);
 			print_debug("\n");
-			if (byte == 8) {
+			if (byte == SPD_MEMORY_TYPE_SDRAM_DDR2) {
 				dimm_mask |= (1 << i);
 			}
 		}
@@ -249,6 +252,7 @@
 		print_debug(" reg = ");
 		print_debug_hex8(reg);
 		print_debug("\n");
+		print_debug("ECHEC");
 
 		/* set device density */
 		dra |= ((31-reg));
@@ -259,7 +263,7 @@
 		dra |= (1 << 10);
 
 		/* set device type (registered) */
-		dra |= (1 << 14);
+		if(ram_is_ecc/* XXX */) dra |= (1 << 14);
 
 		/* set number of ranks (0=single, 1=dual) */
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS);
@@ -290,15 +294,21 @@
 	u32 twtr = 0;
 	int index = drc & 0x00000003;
 	int ci;
+
+	// Does ECC induces timing differences with non-ECC?? XXX
 	static const u8 latencies[] = { /* 533, 800, 400, 667 */
 		0x10, 0x60, 0x10, 0x20 };
 	static const u32 drt0[] = { /* 533, 800, 400, 667 */
 		0x24240002, 0x24360002, 0x24220002, 0x24360002 };
 	static const u32 drt1[] = { /* 533, 800, 400, 667 */
 		0x00400000, 0x00900000, 0x00200000, 0x00700000 };
-	static const u32 magic[] = { /* 533, 800, 400, 667 */
+	static const u32 ddrrefresh[] = { /* 533, 800, 400, 667 */
+		/* 27:12 -> RRCOUNT
+		 * 11:4 -> TRFC
+		 * 3:0 -> RefreshEnable
+		 */
 		0x007b8221, 0x00b94331, 0x005ca1a1, 0x009a62b1 };
-	static const u32 mrs[] = { /* 533, 800, 400, 667 */
+	static const u32 mrs[] = { /* 533, 800, 400, 667 */ // What is this? XXX
 		0x07020000, 0x0b020000, 0x05020000, 0x09020000 };
 	static const int cycle[] = { /* 533, 800, 400, 667 */
 		15, 10, 20, 12 }; /* cycle time in 1/4 ns units */
@@ -395,11 +405,11 @@
 	print_debug("\n");
 	pci_write_config32(ctrl->f0, DRT1, val);
 
-	val = (magic[index]);
-	print_debug("magic = ");
+	val = (ddrrefresh[index]);
+	print_debug("ddrrefresh = ");
 	print_debug_hex32(val);
 	print_debug("\n");
-	pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
+	pci_write_config32(PCI_DEV(0, 0x08, 0), DDRREFRESH, val);
 
 	val = (mrs[index] | (cl << 20));
 	print_debug("mrs = ");
@@ -411,20 +421,26 @@
 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 					u8 dimm_mask)
 {
+#undef ram_is_ecc
+	unsigned ram_is_ecc;
 	int value;
 	int drc = 0;
 	int i;
 	msr_t msr;
 	u8 cycle = 0x25;
+	u8 spd_dimm_config_type;
 
 	for (i = 0; i < DIMM_SOCKETS; i++) {
 		if (!(dimm_mask & (1 << i)))
 			continue;
 		if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)
 			die("ERROR: Only 64-bit DIMMs supported\n");
-		if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))
-			die("ERROR: Only ECC DIMMs supported\n");
-		if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)
+		spd_dimm_config_type = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE);
+		//print_info("SPD_DIMM_CONFIG_TYPE: "); print_info_hex8(spd_dimm_config_type); print_info("\n");
+		ram_is_ecc = !!(spd_dimm_config_type & 0x02);
+		print_info(ram_is_ecc ? "RAM is ECC\n" : "RAM is not ECC\n");
+			//die("ERROR: Only ECC DIMMs supported\n"); // XXX should be changed
+		if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 8)
 			die("ERROR: Only x8 DIMMs supported\n");
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
@@ -435,7 +451,7 @@
 	print_debug_hex8(cycle);
 	print_debug("\n");
 
-	drc |= (1 << 20); /* enable ECC */
+	if (ram_is_ecc) drc |= (1 << 20); /* enable ECC */
 	drc |= (3 << 30); /* enable CKE on each DIMM */
 	drc |= (1 << 4); /* enable CKE globally */
 
@@ -484,11 +500,11 @@
 
 	return drc;
 }
+#define ram_is_ecc 1
 
 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
 	u8 dimm_mask;
-	int i;
 
 	/* Test if we can read the SPD */
 	dimm_mask = spd_detect_dimms(ctrl);
@@ -502,12 +518,13 @@
 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 {
 	u8 c1,c2;
-        u32 dimm,i;
+        u32 i;
         u32 data32;
-	u32 t4;
 
 	/* Set up northbridge values */
 	/* ODT enable */
+	/* WTF is this value? XXX SCH_GGT = 0x2 :/
+	 */
   	pci_write_config32(ctrl->f0, SDRC, 0xa0002c30);
 
 	c1 = pci_read_config8(ctrl->f0, DRB);
@@ -565,8 +582,6 @@
 	u32 drc;
 	u32 data32;
 	u32 mode_reg;
-	msr_t msr;
-	u16 data16;
 
 	mask = spd_detect_dimms(ctrl);
 	print_debug("Starting SDRAM Enable\n");
@@ -595,12 +610,14 @@
 
 	dump_dcal_regs();
 
+	/* see JESD79-2F p.17 (PDF p.27) */
 	/* Apply NOP */
 	for (cs = 0; cs < 2; cs++) {
 		print_debug("NOP CS");
 		print_debug_hex8(cs);
 		print_debug("\n");
 		udelay(16);
+		// XXX why is the CS written first?
 		write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
 		write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -773,7 +790,7 @@
 	dump_dcal_regs();
 
 	print_debug("Done\n");
-
+	
 	/* Set initialization complete */
 	drc |= (1 << 29);
 	drc |= (3 << 30);
Index: src/northbridge/intel/i3100/ep80579.h
===================================================================
--- src/northbridge/intel/i3100/ep80579.h	(revision 6427)
+++ src/northbridge/intel/i3100/ep80579.h	(working copy)
@@ -60,4 +60,6 @@
 #define MBDATA    0x148
 #define DDRIOMC2  0x268
 
+/* Bus 0, Device 0, Function 8 */
+#define DDRREFRESH 0xcc
 #endif
Index: src/northbridge/intel/i3100/raminit_ep80579.h
===================================================================
--- src/northbridge/intel/i3100/raminit_ep80579.h	(revision 6427)
+++ src/northbridge/intel/i3100/raminit_ep80579.h	(working copy)
@@ -25,6 +25,7 @@
 	u32 node_id;
 	device_t f0;
 	u16 channel0[DIMM_SOCKETS];
+	unsigned ram_is_ecc;
 };
 
 #endif
