

coreboot-4.0-1929-g79cfe7e-dirty-dk Fri Jan 20 17:26:01 CET 2012 starting...
BSP Family_Model: 00500f20 
cpu_init_detectedx = 00000000 
agesawrapper_amdinitmmio passed.
agesawrapper_amdinitreset 
*** !!AGESA cb_AgesaV1.1.0.3     ***


AmdInitReset: Start

AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitReset: End

passed.
agesawrapper_amdinitearly AmdInitEarly: Start 0 

AllocateExecutionCache: Start
AllocateExecutionCache: End
AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=500f20.
  Dispatch CPU features after HT discovery
Topology: Socket 0, Die 0, is Node 0, with Cores 0 thru 1. Compute Unit status (0x0,0x0).
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 0 APIC ID = 0x0
  Perform core init step 4
  Perform core init step 5
  Perform core init step 6
  Launch socket 0 core 1
  Dispatch CPU features before early power mgmt init
  Perform PM init step 0
    *WR SMUx0B:0x8600 = 0x1865000
    *WR SMUx0B:0x8604 = 0x6000fe04
    *WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
  Perform PM init step 1
  Perform PM init step 2
  Perform PM init step 3
  Transition all cores to POST P-state
  Dispatch CPU features after early power mgmt init
    IO C-state is enabled
    C6 is enabled
  Halting all APs
AmdCpuEarly: End
NbInitAtEarly Enter
    *WR SMUx0B:0x8400 = 0x0
    *WR SMUx0B:0x8404 = 0x0
    *WR SMUx0B:0x8408 = 0x0
    *WR SMUx0B:0x840c = 0x0
    *WR SMUx0B:0x8410 = 0x0
    *WR SMUx0B:0x8414 = 0x0
    *WR SMUx0B:0x8418 = 0x0
    *WR SMUx0B:0x841c = 0x0
    *WR SMUx0B:0x8420 = 0x0
    *WR SMUx0B:0x8424 = 0x0
    *WR SMUx0B:0x8428 = 0x0
    *WR SMUx0B:0x842c = 0x0
    *WR SMUx0B:0x8430 = 0x0
    *WR SMUx0B:0x8434 = 0x0
    *WR SMUx0B:0x8438 = 0x0
    *WR SMUx0B:0x843c = 0x0
    *WR SMUx0B:0x8440 = 0x0
    *WR SMUx0B:0x8444 = 0x0
    *WR SMUx0B:0x8448 = 0x0
    *WR SMUx0B:0x844c = 0x0
    *WR SMUx0B:0x8450 = 0x0
    *WR SMUx0B:0x8454 = 0x0
    *WR SMUx0B:0x8458 = 0x0
    *WR SMUx0B:0x845c = 0x0
    *WR SMUx0B:0x8460 = 0x0
    *WR SMUx0B:0x8464 = 0x0
    *WR SMUx0B:0x8468 = 0x0
    *WR SMUx0B:0x846c = 0x0
    *WR SMUx0B:0x8470 = 0x0
    *WR SMUx0B:0x8474 = 0x0
    *WR SMUx0B:0x8478 = 0x0
    *WR SMUx0B:0x847c = 0x0
    *WR SMUx0B:0x8480 = 0x0
    *WR SMUx0B:0x8484 = 0x0
    *WR SMUx0B:0x8488 = 0x0
    *WR SMUx0B:0x848c = 0x0
    *WR SMUx0B:0x8490 = 0x0
    *WR SMUx0B:0x8494 = 0x0
    *WR SMUx0B:0x8498 = 0x0
    *WR SMUx0B:0x849c = 0x0
    *WR SMUx0B:0x84a0 = 0x0
    *WR SMUx0B:0x84a4 = 0x0
    *WR SMUx0B:0x84a8 = 0x0
    *WR SMUx0B:0x84ac = 0x0
    *WR SMUx0B:0x84b0 = 0x0
    *WR SMUx0B:0x84b4 = 0x0
    *WR SMUx0B:0x84b8 = 0x0
    *WR SMUx0B:0x84bc = 0x0
    *WR SMUx0B:0x84c0 = 0x0
    *WR SMUx0B:0x84c4 = 0x0
    *WR SMUx0B:0x84c8 = 0x0
    *WR SMUx0B:0x84cc = 0x0
    *WR SMUx0B:0x84d0 = 0x0
    *WR SMUx0B:0x84d4 = 0x0
    *WR SMUx0B:0x84d8 = 0x0
    *WR SMUx0B:0x84dc = 0x0
    *WR SMUx0B:0x84e0 = 0x0
    *WR SMUx0B:0x84e4 = 0x0
    *WR SMUx0B:0x84e8 = 0x0
    *WR SMUx0B:0x84ec = 0x0
    *WR SMUx0B:0x84f0 = 0x0
    *WR SMUx0B:0x84f4 = 0x0
    *WR SMUx0B:0x84f8 = 0x0
    *WR SMUx0B:0x84fc = 0x0
    *WR SMUx0B:0x8500 = 0x0
    *WR SMUx0B:0x8504 = 0x0
    *WR SMUx0B:0x8508 = 0x0
    *WR SMUx0B:0x850c = 0x0
    *WR SMUx0B:0x8510 = 0x0
    *WR SMUx0B:0x8514 = 0x0
    *WR SMUx0B:0x8518 = 0x0
    *WR SMUx0B:0x851c = 0x0
    *WR SMUx0B:0x8520 = 0x0
    *WR SMUx0B:0x8524 = 0x0
    *WR SMUx0B:0x8528 = 0x0
    *WR SMUx0B:0x852c = 0x0
    *WR SMUx0B:0x8530 = 0x0
    *WR SMUx0B:0x8534 = 0x0
    *WR SMUx0B:0x8538 = 0x0
    *WR SMUx0B:0x853c = 0x0
    *WR SMUx0B:0x8540 = 0x0
    *WR SMUx0B:0x8544 = 0x0
    *WR SMUx0B:0x8548 = 0x0
    *WR SMUx0B:0x854c = 0x0
    *WR SMUx0B:0x8550 = 0x0
    *WR SMUx0B:0x8554 = 0x0
    *WR SMUx0B:0x8558 = 0x0
    *WR SMUx0B:0x855c = 0x0
    *WR SMUx0B:0x8560 = 0x0
    *WR SMUx0B:0x8564 = 0x0
    *WR SMUx0B:0x8568 = 0x0
    *WR SMUx0B:0x856c = 0x0
    *WR SMUx0B:0x8570 = 0x0
    *WR SMUx0B:0x8574 = 0x0
    *WR SMUx0B:0x8578 = 0x0
    *WR SMUx0B:0x857c = 0x0
    *WR SMUx0B:0x8580 = 0x0
    *WR SMUx0B:0x8584 = 0x0
    *WR SMUx0B:0x8588 = 0x0
    *WR SMUx0B:0x858c = 0x0
    *WR SMUx0B:0x8590 = 0x0
    *WR SMUx0B:0x8594 = 0x0
    *WR SMUx0B:0x8598 = 0x0
    *WR SMUx0B:0x859c = 0x0
    *WR SMUx0B:0x85a0 = 0x0
    *WR SMUx0B:0x85a4 = 0x0
    *WR SMUx0B:0x85a8 = 0x0
    *WR SMUx0B:0x85ac = 0x0
    *WR SMUx0B:0x9000 = 0x0
    *WR SMUx0B:0x9004 = 0x0
NbInitAtEarly Exit[0x0]
NbSmuInitFeature Enter
  Current SMU firmware rev 1.601
  New SMU firmware rev 1.601
NbSmuInitFeature Exit
PcieConfigurationInit Enter
PcieMapTopologyOnComplex Enter
<---------- PCIe User Config Start------------->
  ComplexDescriptor SocketId - 0
  NumberOfEngines - 7
  Engine Type - PCIe Port
    Start Phy Lane - 4
    End   Phy Lane - 4
    PortPresent - 1
    ChannelType  - 4
    DeviceNumber - 4
    FunctionNumber - 0
    LinkSpeedCapability - 2
    LinkAspm - 3
    LinkHotplug - 0
    ResetId - 4
  Engine Type - PCIe Port
    Start Phy Lane - 5
    End   Phy Lane - 5
    PortPresent - 1
    ChannelType  - 4
    DeviceNumber - 5
    FunctionNumber - 0
    LinkSpeedCapability - 2
    LinkAspm - 3
    LinkHotplug - 0
    ResetId - 5
  Engine Type - PCIe Port
    Start Phy Lane - 6
    End   Phy Lane - 6
    PortPresent - 1
    ChannelType  - 4
    DeviceNumber - 6
    FunctionNumber - 0
    LinkSpeedCapability - 2
    LinkAspm - 3
    LinkHotplug - 0
    ResetId - 6
  Engine Type - PCIe Port
    Start Phy Lane - 7
    End   Phy Lane - 7
    PortPresent - 1
    ChannelType  - 4
    DeviceNumber - 7
    FunctionNumber - 0
    LinkSpeedCapability - 2
    LinkAspm - 3
    LinkHotplug - 0
    ResetId - 7
  Engine Type - PCIe Port
    Start Phy Lane - 0
    End   Phy Lane - 3
    PortPresent - 1
    ChannelType  - 4
    DeviceNumber - 8
    FunctionNumber - 0
    LinkSpeedCapability - 2
    LinkAspm - 3
    LinkHotplug - 0
    ResetId - 0
  Engine Type - DDI Link
    Start Phy Lane - 8
    End   Phy Lane - 11
    ConnectorType - 10
    AuxIndex  - 0
    HdpIndex - 0
  Engine Type - DDI Link
    Start Phy Lane - 12
    End   Phy Lane - 15
    ConnectorType - 0
    AuxIndex  - 1
    HdpIndex - 1
<---------- PCIe User Config End-------------->
PcieEnginesToWrapper Enter
PcieEnginesToWrapper Exit [0]
PcieEnginesToWrapper Enter
PcieEnginesToWrapper Exit [0]
PcieMapTopologyOnComplex Exit [0]
<-------------- PCIe Config Start----------------->
  PSPP Policy - Disabled
  GFX Workaround - Disabled
  LinkL0Pooling - 60000us
  LinkGpioResetAssertionTime - 2000us
  LinkReceiverDetectionPooling - 60000us
  <---------Wrapper - GPPSB Config -------->
    PowerOffUnusedLanes - 1
    PowerOffUnusedPlls - 1
    ClkGating - 1
    LclkGating - 1
    TxclkGatingPllPowerDown - 1
    PllOffInL1 - 1
  <---------Wrapper - GPPSB Config End----->
  Engine Type - PCIe Port
    Start Phy Lane - 4
    End   Phy Lane - 4
    PCIe port configuration:
      Port Training - Enabled
      Start Core Lane - 4
      End Core Lane   - 4
      PCI Address - 0:4:0
      Native PCI Dev Number  - 4
      Native PCI Func Number - 0
      Hotplug - Disabled
      ASPM    - L0s & L1
      Speed   - 2
  Engine Type - PCIe Port
    Start Phy Lane - 5
    End   Phy Lane - 5
    PCIe port configuration:
      Port Training - Enabled
      Start Core Lane - 5
      End Core Lane   - 5
      PCI Address - 0:5:0
      Native PCI Dev Number  - 5
      Native PCI Func Number - 0
      Hotplug - Disabled
      ASPM    - L0s & L1
      Speed   - 2
  Engine Type - PCIe Port
    Start Phy Lane - 6
    End   Phy Lane - 6
    PCIe port configuration:
      Port Training - Enabled
      Start Core Lane - 6
      End Core Lane   - 6
      PCI Address - 0:6:0
      Native PCI Dev Number  - 6
      Native PCI Func Number - 0
      Hotplug - Disabled
      ASPM    - L0s & L1
      Speed   - 2
  Engine Type - PCIe Port
    Start Phy Lane - 7
    End   Phy Lane - 7
    PCIe port configuration:
      Port Training - Enabled
      Start Core Lane - 7
      End Core Lane   - 7
      PCI Address - 0:7:0
      Native PCI Dev Number  - 7
      Native PCI Func Number - 0
      Hotplug - Disabled
      ASPM    - L0s & L1
      Speed   - 2
  Engine Type - PCIe Port
    Start Phy Lane - 0
    End   Phy Lane - 3
    PCIe port configuration:
      Port Training - Enabled
      Start Core Lane - 0
      End Core Lane   - 3
      PCI Address - 0:8:0
      Native PCI Dev Number  - 8
      Native PCI Func Number - 0
      Hotplug - Disabled
      ASPM    - L0s & L1
      Speed   - 2
  <---------Wrapper - Virtual DDI Config -------->
    PowerOffUnusedLanes - 1
    PowerOffUnusedPlls - 1
    ClkGating - 1
    LclkGating - 1
    TxclkGatingPllPowerDown - 1
    PllOffInL1 - 0
  <---------Wrapper - Virtual DDI Config End----->
  Engine Type - DDI Link
    Start Phy Lane - 8
    End   Phy Lane - 11
    DDI configuration:
      Connector - LVDS
      Aux - Aux1
      Hdp - Hdp1
  Engine Type - DDI Link
    Start Phy Lane - 12
    End   Phy Lane - 15
    DDI configuration:
      Connector - DP
      Aux - Aux2
      Hdp - Hdp2
<-------------- PCIe Config End------------------>
PcieConfigurationInit Exit [0x0]
PcieInitAtEarly Enter

 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0

PcieInit Enter
    *WR GPP WRAP (0:0:0):0x01308063 = 0x00007c30
    *WR GPP PHY0 (0:0:0):0x01206440 = 0x000000c1
    *WR GPP PHY0 (0:0:0):0x01206480 = 0x000000c1
    *WR GPP PHY0 (0:0:0):0x01206500 = 0x000000c1
    *WR GPP PHY0 (0:0:0):0x01206600 = 0x000000c1
    *WR GPP PHY0 (0:0:0):0x01206840 = 0x000000c1
    *WR GPP PHY0 (0:0:0):0x01206880 = 0x000000c1
    *WR GPP PHY0 (0:0:0):0x01206900 = 0x000000c1
    *WR GPP PHY0 (0:0:0):0x01206a00 = 0x000000c1
    *WR GPP WRAP (0:0:0):0x01308016 = 0x00ff0000
    *WR GPP PHY0 (0:0:0):0x01204004 = 0x00000003
    *WR  !!! Something Wrong !!! (0:0:0):0x01088071 = 0x2075e003
    *WR  !!! Something Wrong !!! (0:0:0):0x01088072 = 0x0061e003
    *WR GPP WRAP (0:0:0):0x01308002 = 0x12341022
    *WR GPP CORE (0:0:0):0x01010011 = 0x0000000f
    *WR GPP WRAP (0:0:0):0x01308062 = 0x00010000
  Core Configuration: Wrapper [GPPSB], CoreID [1] - 1x4, 4x1
    *WR GPP WRAP (0:0:0):0x01300080 = 0x00000004
PcieTopologyApplyLaneMux Enter
    *WR GPP WRAP (0:0:0):0x01308021 = 0x76543210
    *WR GPP WRAP (0:0:0):0x01308022 = 0x76543210
PcieTopologyApplyLaneMux Exit
PciePifSetLs2ExitTime Enter
    *WR GPP PIF0 (0:0:0):0x01100010 = 0x01800019
PciePifSetLs2ExitTime Exit
PcieTopologySelectMasterPll Enter
    *WR GPP WRAP (0:0:0):0x01308013 = 0x00000001
PcieTopologySelectMasterPll Enter
PcieTopologyExecuteReconfig Enter
    *WR GPP WRAP (0:0:0):0x01308063 = 0x00000c00
    *WR GPP WRAP (0:0:0):0x01308062 = 0x00010001
    *WR GPP WRAP (0:0:0):0x01308060 = 0x00000005
    *WR GPP WRAP (0:0:0):0x01308062 = 0x00010800
    *WR GPP WRAP (0:0:0):0x01308063 = 0x00007c30
PcieTopologyExecuteReconfig Exit
PcieTopologySetLinkReversal Enter
PcieTopologySetLinkReversal Exit
PciePifApplyGanging Enter
    *WR GPP PIF0 (0:0:0):0x01100011 = 0x00000100
PciePifApplyGanging Exit
PciePifPllInitForDdi Enter
PciePifPllInitForDdi Exit
    *WR GPP WRAP (0:0:0):0x01308023 = 0x0000008f

 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0

PcieCommonCoreInit Enter
    *WR GPP CORE (0:0:0):0x01010020 = 0x00000250
    *WR GPP CORE (0:0:0):0x01010010 = 0x80631000
    *WR GPP CORE (0:0:0):0x0101001c = 0x00000109
    *WR GPP CORE (0:0:0):0x01010040 = 0x00008000
    *WR GPP CORE (0:0:0):0x01010002 = 0x00000001
    *WR GPP CORE (0:0:0):0x010100c1 = 0x00000007
    *WR GPP CORE (0:0:0):0x010100b0 = 0x00000005
PcieCommonCoreInit Exit
    *WR GPP PIF0 (0:0:0):0x01100010 = 0x01800019
PcieFmSetBootUpVoltage Enter
  Set Voltage for Gen 1, Vid Index 0

 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0

PcieFmSetBootUpVoltage Exit
PcieInit Exit [0]
    *WR PCIEIND_P (0:4:0):0x0002 = 0x00008000
    *WR PCIEIND_P (0:4:0):0x0070 = 0x000843f7
    *WR PCIEIND_P (0:4:0):0x00a0 = 0x40800030
    *WR PCIEIND_P (0:4:0):0x00a1 = 0x04001d80
    *WR PCIEIND_P (0:4:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:4:0):0x00a3 = 0xffff020c
    *WR PCIEIND_P (0:4:0):0x00b1 = 0x86180280
    *WR GPP WRAP (0:0:0):0x01300903 = 0x00000000
    *WR PCIEIND_P (0:4:0):0x00a4 = 0x12028040
    *WR PCIEIND_P (0:4:0):0x00c0 = 0x00008000
    *WR PCIEIND_P (0:4:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:5:0):0x0002 = 0x00008000
    *WR PCIEIND_P (0:5:0):0x0070 = 0x000843f7
    *WR PCIEIND_P (0:5:0):0x00a0 = 0x40800030
    *WR PCIEIND_P (0:5:0):0x00a1 = 0x04001d80
    *WR PCIEIND_P (0:5:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:5:0):0x00a3 = 0xffff020c
    *WR PCIEIND_P (0:5:0):0x00b1 = 0x86180280
    *WR GPP WRAP (0:0:0):0x01300a03 = 0x00000000
    *WR PCIEIND_P (0:5:0):0x00a4 = 0x12028040
    *WR PCIEIND_P (0:5:0):0x00c0 = 0x00008000
    *WR PCIEIND_P (0:5:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:6:0):0x0002 = 0x00008000
    *WR PCIEIND_P (0:6:0):0x0070 = 0x000843f7
    *WR PCIEIND_P (0:6:0):0x00a0 = 0x40800030
    *WR PCIEIND_P (0:6:0):0x00a1 = 0x04001d80
    *WR PCIEIND_P (0:6:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:6:0):0x00a3 = 0xffff020c
    *WR PCIEIND_P (0:6:0):0x00b1 = 0x86180280
    *WR GPP WRAP (0:0:0):0x01300b03 = 0x00000000
    *WR PCIEIND_P (0:6:0):0x00a4 = 0x12028040
    *WR PCIEIND_P (0:6:0):0x00c0 = 0x00008000
    *WR PCIEIND_P (0:6:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:7:0):0x0002 = 0x00008000
    *WR PCIEIND_P (0:7:0):0x0070 = 0x000843f7
    *WR PCIEIND_P (0:7:0):0x00a0 = 0x40800030
    *WR PCIEIND_P (0:7:0):0x00a1 = 0x04001c80
    *WR PCIEIND_P (0:7:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:7:0):0x00a3 = 0xffff020c
    *WR PCIEIND_P (0:7:0):0x00b1 = 0x86180286
    *WR GPP WRAP (0:0:0):0x01300c03 = 0x00000000
    *WR PCIEIND_P (0:7:0):0x00a4 = 0x1a028040
    *WR PCIEIND_P (0:7:0):0x00c0 = 0x00008000
    *WR PCIEIND_P (0:7:0):0x00a2 = 0x00201416
    *WR PCIEIND_P (0:8:0):0x0002 = 0x00008000
    *WR PCIEIND_P (0:8:0):0x0070 = 0x000843f7
    *WR PCIEIND_P (0:8:0):0x00a0 = 0x40800030
    *WR PCIEIND_P (0:8:0):0x00a1 = 0x04001c80
    *WR PCIEIND_P (0:8:0):0x00a2 = 0x00301636
    *WR PCIEIND_P (0:8:0):0x00a3 = 0x18ff020c
    *WR PCIEIND_P (0:8:0):0x00b1 = 0x86180286
    *WR GPP WRAP (0:0:0):0x01300803 = 0x00000000
    *WR PCIEIND_P (0:8:0):0x00a4 = 0x12028040
    *WR PCIEIND_P (0:8:0):0x00c0 = 0x00008000
    *WR PCIEIND_P (0:8:0):0x00a2 = 0x00301636
PcieTraining Enter
  Port 0:4:0 State [LinkTrainingResetTimeout ] Time Stamp [123482815]
  Port 0:5:0 State [LinkTrainingResetTimeout ] Time Stamp [123489151]
  Port 0:6:0 State [LinkTrainingResetTimeout ] Time Stamp [123495427]
  Port 0:7:0 State [LinkTrainingResetTimeout ] Time Stamp [123501717]
  Port 0:8:0 State [LinkStateTrainingComplete] Time Stamp [0]
  Port 0:4:0 State [LinkStateReleaseTraining ] Time Stamp [123482815]
  Port 0:5:0 State [LinkStateReleaseTraining ] Time Stamp [123489151]
  Port 0:6:0 State [LinkStateReleaseTraining ] Time Stamp [123495427]
  Port 0:7:0 State [LinkStateReleaseTraining ] Time Stamp [123501717]
    *WR GPP WRAP (0:0:0):0x01300900 = 0x00000000
  Port 0:4:0 State [LinkStateDetectPresence  ] Time Stamp [123542836]
    *WR GPP WRAP (0:0:0):0x01300a00 = 0x00000000
  Port 0:5:0 State [LinkStateDetectPresence  ] Time Stamp [123553355]
    *WR GPP WRAP (0:0:0):0x01300b00 = 0x00000000
  Port 0:6:0 State [LinkStateDetectPresence  ] Time Stamp [123563875]
    *WR GPP WRAP (0:0:0):0x01300c00 = 0x00000000
  Port 0:7:0 State [LinkStateDetectPresence  ] Time Stamp [123574397]
  Port 0:7:0 State [LinkStateDetecting       ] Time Stamp [123580778]
  Port 0:7:0 State [LinkStateL0              ] Time Stamp [123580778]
  Port 0:7:0 State [LinkStateVcoNegotiation  ] Time Stamp [123593280]
  Port 0:7:0 State [LinkStateTrainingSuccess ] Time Stamp [123593280]
  Port 0:4:0 State [LinkStateDeviceNotPresent] Time Stamp [123542836]
  Port 0:7:0 State [LinkStateTrainingComplete] Time Stamp [123593280]
    *WR GPP WRAP (0:0:0):0x01300900 = 0x00000001
  Port 0:4:0 State [LinkStateTrainingComplete] Time Stamp [123542836]
  Port 0:5:0 State [LinkStateDeviceNotPresent] Time Stamp [123553355]
  Port 0:6:0 State [LinkStateDeviceNotPresent] Time Stamp [123563875]
    *WR GPP WRAP (0:0:0):0x01300a00 = 0x00000001
  Port 0:5:0 State [LinkStateTrainingComplete] Time Stamp [123553355]
    *WR GPP WRAP (0:0:0):0x01300b00 = 0x00000001
  Port 0:6:0 State [LinkStateTrainingComplete] Time Stamp [123563875]
PcieTraining Exit [0]

 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0

PcieInitAtEarly Exit [0x0]

AmdInitEarly: End

passed.
agesawrapper_amdinitpost AmdInitPost: Start

PcieInitAtPostEarly Enter

 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0

PcieTraining Enter
PcieTraining Exit [0]

 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00a, 0, 0, 0

PcieInitAtPostEarly Exit [0x0]
GfxConfigPostInterface Enter
<-------------- GFX Config Start ------------->
  HD Audio - Enabled
  DynamicRefreshRate - 0x0
  LcdBackLightControl - 0x0
  AbmSupport - Disabled
  GmcClockGating - Enabled
  GmcPowerGating - GmcPowerGatingWidthStutter
  UmaSteering - Garlic
  iGpuVgaMode - VGA
  UmaMode - No UMA
<-------------- GFX Config End --------------->
GfxConfigPostInterface Exit [0x0]
GfxInitAtPost Enter
GfxGetDiscreteCardInfo Enter
  Evaluate device [0:7:0]
  Evaluate device [5:0:0]
  Evaluate device [6:2:0]
  Evaluate device [6:3:0]
  Evaluate device [6:4:0]
  Evaluate device [6:5:0]
  Evaluate device [0:17:0]
  Evaluate device [0:18:0]
  Evaluate device [0:18:2]
  Evaluate device [0:19:0]
  Evaluate device [0:19:2]
  Evaluate device [0:20:0]
  Evaluate device [0:20:2]
  Evaluate device [0:20:3]
  Evaluate device [0:20:4]
  Evaluate device [0:20:5]
  Evaluate device [0:21:0]
  Evaluate device [5:0:0]
  Evaluate device [0:24:0]
  Evaluate device [0:24:1]
  Evaluate device [0:24:2]
  Evaluate device [0:24:3]
  Evaluate device [0:24:4]
  Evaluate device [0:24:5]
  Evaluate device [0:24:6]
  Evaluate device [0:24:7]
GfxGetDiscreteCardInfo Exit
GfxInitAtPost Exit [0x0]
AmdMemAuto: Start
MEM PARAMS:
	BottomIo : 00e0
	MemHoleRemap : 1
	UserTimingMode : 0
	MemClockValue : 533
	BankIntlv : 1
	NodeIntlv : 0
	ChannelIntlv : 0
	EccFeature : 0
	PowerDown : 1
	OnLineSpare : 0
	Parity : 0
	BankSwizzle : 1
	MemClr : 1
	UmaMode : 2
	UmaSize : 0
	MemRestoreCtl : 0
	SaveMemContextCtl : 0

SPD Socket 0 Channel 0 Dimm 0: 00400ad1
	SocketID: 0
	DieID: 0
	PciAddr: c0000
Node 0
~Fn3_0e8 = 10001761
~Fn2_040 = 1
~Fn2_040 [31:0] = 0
~Fn2_044 = 0
~Fn2_044 [31:0] = 0
~Fn2_048 = 0
~Fn2_048 [31:0] = 0
~Fn2_04c = 0
~Fn2_04c [31:0] = 0
~Fn2_088 = fe000003
~Fn2_088 [3:0] = 2
~Fn2_0f0 = 80000040
~Fn2_0F4_40 = b050202
~Fn2_0f0 = c0000040
~Fn2_0F4_40 [3:0] = 1
~Fn2_0f0 = 80000040
~Fn2_0F4_40 = b050201
~Fn2_0f0 = c0000040
~Fn2_0F4_40 [11:8] = 1
~Fn2_0f0 = 80000041
~Fn2_0F4_41 = 0
~Fn2_0f0 = c0000041
~Fn2_0F4_41 [2:0] = 0
~Fn2_0f0 = 80000040
~Fn2_0F4_40 = b050101
~Fn2_0f0 = c0000040
~Fn2_0F4_40 [20:16] = 0
~Fn2_0f0 = 80000040
~Fn2_0F4_40 = b000101
~Fn2_0f0 = c0000040
~Fn2_0F4_40 [29:24] = 5
~Fn2_084 = 900055
~Fn2_084 [6:4] = 3
~Fn2_0f0 = 80000041
~Fn2_0F4_41 = 0
~Fn2_0f0 = c0000041
~Fn2_0F4_41 [10:8] = 0
~Fn2_0f0 = 80000041
~Fn2_0F4_41 = 0
~Fn2_0f0 = c0000041
~Fn2_0F4_41 [18:16] = 0
~Fn2_094 = 3e40888a
~Fn2_094 [31:28] = 1
~Fn2_08c = 326434
~Fn2_08c [22:20] = 3
~Fn2_08c = 326434
~Fn2_08c [25:23] = 0
~Fn2_084 = 900035
~Fn2_084 [22:20] = 0
~Fn2_08c = 326434
~Fn2_08c [17:16] = 2
~Fn2_090 = 6600000
~Fn2_090 [26:26] = 1
~Fn2_0f0 = 80000083
~Fn2_0F4_83 = 6061
~Fn2_0f0 = c0000083
~Fn2_0F4_83 [2:0] = 1
~Fn2_060 = 783fe0
~Fn2_060 [31:0] = 783fe0
~Fn2_080 = 7
~Fn2_080 [31:0] = 7
~Fn2_040 = 1
~Fn2_040 = 1
~Fn2_040 = 1
~Fn2_040 = 1

 * FATAL Event: 04011c00 Data: 0, 0, 0, 0

AmdMemAuto: End

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 2, EventInfo = 8040100.
	Param1 = a00a, Param2 = 0.
	Param3 = 0, Param4 = 0.

EventLog:	EventClass = 7, EventInfo = 4011c00.
	Param1 = 0, Param2 = 0.
	Param3 = 0, Param4 = 0.

 * BOUNDS_CHK Event: 08040100 Data: a008, 0, 0, 0

error level: 7 
agesawrapper_amdinitenv 