Hi. I compiled coreboot image for Asus m2n-e (mcp55,ite 8716f). This board turns off after few seconds<br>The log from serial<br><br>Welcome to minicom 2.5<br><br>OPTIONS: <br>
Compiled on Dec 4 2011, 11:23:38. <br>Port /dev/ttyS0 <br> <br>
Press CTRL-A Z for help on special keys <br> <br> <br>
<br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>*sysinfo range: [000cf000,000cf730] <br>
bsp_apicid=0x00 <br>Enabling routing table for node 00 done.<br>Enabling UP settings <br>Disabling read/write/fill probes for UP... done.<br>
coherent_ht_finalize <br>done <br>core0 started: <br>started ap apicid: <br>SBLink=00<br>NC node|link=00<br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x807f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 <br>dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x1 <br>
after optimize_link_read_pointers_chain, reset_needed=0x1 <br>mcp55_num:01 <br>ht reset - <br>
<br> <br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>
*sysinfo range: [000cf000,000cf730] <br>bsp_apicid=0x00 <br>Enabling routing table for node 00 done. <br>
Enabling UP settings <br>Disabling read/write/fill probes for UP... done. <br>coherent_ht_finalize <br>
done <br>core0 started: <br>started ap apicid: <br>
SBLink=00 <br>NC node|link=00 <br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x7f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x0 <br>
after optimize_link_read_pointers_chain, reset_needed=0x0 <br>mcp55_num:01 <br>Ram1.00 <br>
setting up CPU 00 northbridge registers <br>done. <br>Ram2.00 <br>
sdram_set_spd_registers: paramx :000cef20 <br>Enable 64MuxMode & BurstLength32 <br>Unbuffered <br>
333MHz <br>333MHz <br>set_ecc spd_device: 0x51 <br>
Interleaving disabled <br>RAM end at 0x00080000 kB <br>Ram3 <br>
ECC enabled <br>Initializing memory: done <br>Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>
set DQS timing:RcvrEn:Pass1: 00 <br> CTLRMaxDelay=03 <br> done <br>
set DQS timing:DQSPos: 00 <br>TrainDQSRdWrPos: buf_a:000ce9f0 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br>
done <br>set DQS timing:RcvrEn:Pass2: 00 <br> CTLRMaxDelay=58 <br>
done <br>Total DQS Training : tsc [00]=0000000012e40bef <br>Total DQS Training : tsc [01]=000000001358f446 <br>
Total DQS Training : tsc [02]=0000000018d60c82 <br>Total DQS Training : tsc [03]=0000000019771d46 <br>Ram4 <br>
v_esp=000cef68 <br>testx = 5a5a5a5a <br> <br> <br>
<br>INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- <br> <br>
Issuing SOFT_RESET... <br> <br> <br>
coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>*sysinfo range: [000cf000,000cf730] <br>bsp_apicid=0x00 <br>
Enabling routing table for node 00 done. <br>Enabling UP settings <br>Disabling read/write/fill probes for UP... done. <br>
coherent_ht_finalize <br>done <br>core0 started: <br>
started ap apicid: <br>SBLink=00 <br>NC node|link=00 <br>
entering optimize_link_incoherent_ht <br>sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>
pos=0x8a, unfiltered freq_cap=0x8075 <br>pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x7f <br>
pos=0x52, filtered freq_cap=0x7f <br>freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>
dev1 input width=0x1 <br>dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>
old dev1 input|output width=0x11 <br>dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>
after ht_optimize_link for link pair 0, reset_needed=0x0 <br>after optimize_link_read_pointers_chain, reset_needed=0x0 <br>mcp55_num:01 <br>
Ram1.00 <br>setting up CPU 00 northbridge registers <br>done. <br>
Ram2.00 <br>sdram_set_spd_registers: paramx :000cef20 <br>Enable 64MuxMode & BurstLength32 <br>
Unbuffered <br>333MHz <br>333MHz <br>
set_ecc spd_device: 0x51 <br>Interleaving disabled <br>RAM end at 0x00080000 kB <br>
Ram3 <br>ECC enabled <br>Initializing memory: done <br>
Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>set DQS timing:RcvrEn:Pass1: 00 <br> CTLRMaxDelay=03 <br>
done <br>set DQS timing:DQSPos: 00 <br>TrainDQSRdWrPos: buf_a:000ce9f0 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br> done <br>set DQS timing:RcvrEn:Pass2: 00 <br>
CTLRMaxDelay=58 <br> done <br>Total DQS Training : tsc [00]=0000000012e3eacf <br>
Total DQS Training : tsc [01]=000000001358d326 <br>Total DQS Training : tsc [02]=0000000018d97cfa <br>Total DQS Training : tsc [03]=00000000197a8c56 <br>
Ram4 <br>v_esp=000cef68 <br>testx = 5a5a5a5a <br>
Copying data from cache to RAM -- switching to use RAM as stack... D <br> <br> <br>
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- <br> <br>Issuing SOFT_RESET... <br>
<br> <br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>
*sysinfo range: [000cf000,000cf730] <br>bsp_apicid=0x00 <br>Enabling routing table for node 00 done. <br>
Enabling UP settings <br>Disabling read/write/fill probes for UP... done. <br>coherent_ht_finalize <br>
done <br>core0 started: <br>started ap apicid: <br>
SBLink=00 <br>NC node|link=00 <br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x7f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x0 <br>
after optimize_link_read_pointers_chain, reset_needed=0x0 <br>mcp55_num:01 <br>Ram1.00 <br>
setting up CPU 00 northbridge registers <br>done. <br>Ram2.00 <br>
sdram_set_spd_registers: paramx :000cef20 <br>Enable 64MuxMode & BurstLength32 <br>Unbuffered <br>
333MHz <br>333MHz <br>set_ecc spd_device: 0x51 <br>
Interleaving disabled <br>RAM end at 0x00080000 kB <br>Ram3 <br>
ECC enabled <br>Initializing memory: done <br>Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>
set DQS timing:RcvrEn:Pass1: 00 <br> CTLRMaxDelay=03 <br> done <br>
set DQS timing:DQSPos: 00 <br>TrainDQSRdWrPos: buf_a:000ce9f0 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br>
done <br>set DQS timing:RcvrEn:Pass2: 00 <br> CTLRMaxDelay=58 <br>
done <br>Total DQS Training : tsc [00]=0000000012e3ed63 <br>Total DQS Training : tsc [01]=000000001358f68a <br>
Total DQS Training : tsc [02]=0000000018d73a6a <br>Total DQS Training : tsc [03]=0000000019784e5a <br>Ram4 <br>
v_esp=000cef68 <br>testx = 5a5a5a5a <br>Copying data from cache to RAM -- switching to use RAM as stack... m <br>
<br> <br>INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- <br>
<br>Issuing SOFT_RESET... <br> <br>
<br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>*sysinfo range: [000cf000,000cf730] <br>
bsp_apicid=0x00 <br>Enabling routing table for node 00 done. <br>Enabling UP settings <br>
Disabling read/write/fill probes for UP... done. <br>coherent_ht_finalize <br>done <br>
core0 started: <br>started ap apicid: <br>SBLink=00 <br>
NC node|link=00 <br>entering optimize_link_incoherent_ht <br>sysinfo->link_pair_num=0x1 <br>
entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>pos=0x8a, filtered freq_cap=0x75 <br>
pos=0x52, unfiltered freq_cap=0x7f <br>pos=0x52, filtered freq_cap=0x7f <br>freq_cap1=0x75, freq_cap2=0x7f <br>
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>width_cap1=0x11, width_cap2=0x11 <br>
dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>dev1 output ln_width1=0x4, ln_width2=0x4 <br>
dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>dev2 input|output width=0x11 <br>
old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x0 <br>after optimize_link_read_pointers_chain, reset_needed=0x0 <br>
mcp55_num:01 <br>Ram1.00 <br>setting up CPU 00 northbridge registers <br>
done. <br>Ram2.00 <br>sdram_set_spd_registers: paramx :000cef20 <br>
Enable 64MuxMode & BurstLength32 <br>Unbuffered <br>333MHz <br>
333MHz <br>set_ecc spd_device: 0x51 <br>Interleaving disabled <br>
RAM end at 0x00080000 kB <br>Ram3 <br>ECC enabled <br>
Initializing memory: done <br>Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>set DQS timing:RcvrEn:Pass1: 00 <br>
CTLRMaxDelay=03 <br> done <br>set DQS timing:DQSPos: 00 <br>
TrainDQSRdWrPos: buf_a:000ce9f0 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br> done <br>
set DQS timing:RcvrEn:Pass2: 00 <br> CTLRMaxDelay=58 <br> done <br>
Total DQS Training : tsc [00]=0000000012e4504b <br>Total DQS Training : tsc [01]=0000000013593c4a <br>Total DQS Training : tsc [02]=0000000018d6d4b2 <br>
Total DQS Training : tsc [03]=000000001977e9ce <br>Ram4 <br>v_esp=000cef68 <br>
testx = 5a5a5a5a <br>Copying data from cache to RAM -- switching to use RAM as stack... <br><br>