I tried,there are some changes if I use 3th and 4th memory slots, last POST code is 66 and turns off <br><br>coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 starting... <br>*sysinfo range: [000cf000,000cf730] <br>
bsp_apicid=0x00 <br>Enabling routing table for node 00 done.<br>Enabling UP settings <br>Disabling read/write/fill probes for UP... done.<br>
coherent_ht_finalize <br>done <br>core0 started: <br>started ap apicid: <br>SBLink=00<br>NC node|link=00<br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x807f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 <br>dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x1 <br>
after optimize_link_read_pointers_chain, reset_needed=0x1 <br>mcp55_num:01 <br>ht reset - <br>
<br> <br>coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 starting... <br>
*sysinfo range: [000cf000,000cf730] <br>bsp_apicid=0x00 <br>Enabling routing table for node 00 done. <br>
Enabling UP settings <br>Disabling read/write/fill probes for UP... done. <br>coherent_ht_finalize <br>
done <br>core0 started: <br>started ap apicid: <br>
SBLink=00 <br>NC node|link=00 <br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x7f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x0 <br>
after optimize_link_read_pointers_chain, reset_needed=0x0 <br>mcp55_num:01 <br>Ram1.00 <br>
setting up CPU 00 northbridge registers <br>done. <br>Ram2.00 <br>
sdram_set_spd_registers: paramx :000cef20 <br>Unbuffered <br>333MHz <br>
333MHz <br>Interleaving disabled <br>RAM end at 0x00080000 kB <br>
Ram3 <br>Initializing memory: done <br>Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>
set DQS timing:RcvrEn:Pass1: 00 <br> CTLRMaxDelay=0e <br> done <br>
set DQS timing:DQSPos: 00 <br>TrainDQSRdWrPos: buf_a:000ce9f0 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br>
done <br>set DQS timing:RcvrEn:Pass2: 00 <br> CTLRMaxDelay=57 <br>
done <br>Total DQS Training : tsc [00]=000000001287da11 <br>Total DQS Training : tsc [01]=000000001302b830 <br>
Total DQS Training : tsc [02]=00000000188e7b94 <br>Total DQS Training : tsc [03]=00000000195ea260 <br>Ram4 <br>
v_esp=000cef68 <br>testx = 5a5a5a5a <br>Copying data from cache to RAM -- switching to use RAM as stack... Done <br>
testx = 5a5a5a5a <br>Disabling cache as ram now <br>Clearing initial memory region: Done <br>
Loading image. <br>Searching for fallback/coreboot_ram <br>Check cmos_layout.bin <br>
Check fallback/romstage <br>Check fallback/coreboot_ram <br>Stage: loading fallback/coreboot_ram @ 0x100000 (245760 bytes), entry @ 0x100000<br>
Stage: done loading. <br>Jumping to image. <br>coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 booting... <br>
Enumerating buses... <br>Show all devs...Before device enumeration. <br>Root Device: enabled 1 <br>
APIC_CLUSTER: 0: enabled 1 <br>APIC: 00: enabled 1 <br>PCI_DOMAIN: 0000: enabled 1 <br>
PCI: 00:18.0: enabled 1 <br>PCI: 00:00.0: enabled 1 <br>PCI: 00:01.0: enabled 1 <br>
PNP: 002e.0: enabled 1 <br>PNP: 002e.1: enabled 1 <br>PNP: 002e.2: enabled 0 <br>
PNP: 002e.3: enabled 1 <br>PNP: 002e.4: enabled 1 <br>PNP: 002e.5: enabled 1 <br>
PNP: 002e.6: enabled 1 <br>PNP: 002e.7: enabled 0 <br>PNP: 002e.8: enabled 0 <br>
PNP: 002e.9: enabled 0 <br>PNP: 002e.a: enabled 0 <br>PCI: 00:01.1: enabled 1 <br>
I2C: 00:50: enabled 1 <br>I2C: 00:51: enabled 1 <br>I2C: 00:52: enabled 1 <br>
I2C: 00:53: enabled 1 <br>PCI: 00:02.0: enabled 1 <br>PCI: 00:02.1: enabled 1 <br>
PCI: 00:04.0: enabled 1 <br>PCI: 00:05.0: enabled 1 <br>PCI: 00:05.1: enabled 1 <br>
PCI: 00:05.2: enabled 1 <br>PCI: 00:06.0: enabled 1 <br>PCI: 00:06.1: enabled 1 <br>
PCI: 00:08.0: enabled 1 <br>PCI: 00:09.0: enabled 0 <br>PCI: 00:0a.0: enabled 1 <br>
PCI: 00:0b.0: enabled 0 <br>PCI: 00:0c.0: enabled 1 <br>PCI: 00:0d.0: enabled 1 <br>
PCI: 00:0e.0: enabled 0 <br>PCI: 00:0f.0: enabled 1 <br>PCI: 00:18.1: enabled 1 <br>
PCI: 00:18.2: enabled 1 <br>PCI: 00:18.3: enabled 1 <br>Compare with tree... <br>
Root Device: enabled 1 <br> APIC_CLUSTER: 0: enabled 1 <br> APIC: 00: enabled 1 <br>
PCI_DOMAIN: 0000: enabled 1 <br> PCI: 00:18.0: enabled 1 <br> PCI: 00:00.0: enabled 1 <br>
PCI: 00:01.0: enabled 1 <br> PNP: 002e.0: enabled 1 <br> PNP: 002e.1: enabled 1 <br>
PNP: 002e.2: enabled 0 <br> PNP: 002e.3: enabled 1 <br> PNP: 002e.4: enabled 1 <br>
PNP: 002e.5: enabled 1 <br> PNP: 002e.6: enabled 1 <br> PNP: 002e.7: enabled 0 <br>
PNP: 002e.8: enabled 0 <br> PNP: 002e.9: enabled 0 <br> PNP: 002e.a: enabled 0 <br>
PCI: 00:01.1: enabled 1 <br> I2C: 00:50: enabled 1 <br> I2C: 00:51: enabled 1 <br>
I2C: 00:52: enabled 1 <br> I2C: 00:53: enabled 1 <br> PCI: 00:02.0: enabled 1 <br>
PCI: 00:02.1: enabled 1 <br> PCI: 00:04.0: enabled 1 <br> PCI: 00:05.0: enabled 1 <br>
PCI: 00:05.1: enabled 1 <br> PCI: 00:05.2: enabled 1 <br> PCI: 00:06.0: enabled 1 <br>
PCI: 00:06.1: enabled 1 <br> PCI: 00:08.0: enabled 1 <br> PCI: 00:09.0: enabled 0 <br>
PCI: 00:0a.0: enabled 1 <br> PCI: 00:0b.0: enabled 0 <br> PCI: 00:0c.0: enabled 1 <br>
PCI: 00:0d.0: enabled 1 <br> PCI: 00:0e.0: enabled 0 <br> PCI: 00:0f.0: enabled 1 <br>
PCI: 00:18.1: enabled 1 <br> PCI: 00:18.2: enabled 1 <br> PCI: 00:18.3: enabled 1 <br>
scan_static_bus for Root Device <br>APIC_CLUSTER: 0 enabled <br>PCI_DOMAIN: 0000 enabled <br>
APIC_CLUSTER: 0 scanning... <br> PCI: 00:18.3 siblings=0 <br>CPU: APIC: 00 enabled <br>
PCI_DOMAIN: 0000 scanning... <br>PCI: pci_scan_bus for bus 00 <br>PCI: 00:18.0 [1022/1100] bus ops <br>
PCI: 00:18.0 [1022/1100] enabled <br>PCI: 00:18.1 [1022/1101] enabled <br>PCI: 00:18.2 [1022/1102] enabled <br>
PCI: 00:18.3 [1022/1103] ops <br>PCI: 00:18.3 [1022/1103] enabled <br>PCI: Using configuration type 1 <br>
PCI: 00:00.0 [10de/0369] ops <br>PCI: 00:00.0 [10de/0369] enabled <br>Capability: type 0x08 @ 0x44 <br>
flags: 0x01e0 <br>PCI: 00:00.0 count: 000f static_count: 0010 <br>PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010 <br>
PCI: pci_scan_bus for bus 00 <br>PCI: 00:00.0 [10de/0369] enabled <br>PCI: 00:01.0 [10de/0360] bus ops <br>
PCI: 00:01.0 [10de/0360] enabled <br>PCI: 00:01.1 [10de/0368] bus ops <br>PCI: 00:01.1 [10de/0368] enabled <br>
PCI: 00:01.2 [10de/036a] enabled <br>PCI: 00:01.3 [10de/036b] enabled <br>PCI: 00:02.0 [10de/036c] ops <br>
PCI: 00:02.0 [10de/036c] enabled <br>PCI: 00:02.1 [10de/036d] ops <br>PCI: 00:02.1 [10de/036d] enabled <br>
PCI: 00:04.0 [10de/036e] ops <br>PCI: 00:04.0 [10de/036e] enabled <br>PCI: 00:05.0 [10de/037f] ops <br>
PCI: 00:05.0 [10de/037f] enabled <br>PCI: 00:05.1 [10de/037f] ops <br>PCI: 00:05.1 [10de/037f] enabled <br>
PCI: 00:05.2 [10de/037f] ops <br>PCI: 00:05.2 [10de/037f] enabled <br>PCI: 00:06.0 [10de/0370] bus ops <br>
PCI: 00:06.0 [10de/0370] enabled <br>PCI: 00:06.1 [10de/0371] ops <br>PCI: 00:06.1 [10de/0371] enabled <br>
PCI: 00:08.0 [10de/0373] ops <br>PCI: 00:08.0 [10de/0373] enabled <br>PCI: 00:0a.0 [10de/0376] bus ops <br>
PCI: 00:0a.0 [10de/0376] enabled <br>PCI: 00:0c.0 [10de/0374] bus ops <br>PCI: 00:0c.0 [10de/0374] enabled <br>
PCI: 00:0d.0 [10de/0378] bus ops <br>PCI: 00:0d.0 [10de/0378] enabled <br>PCI: 00:0f.0 [10de/0377] bus ops <br>
PCI: 00:0f.0 [10de/0377] enabled <br>scan_static_bus for PCI: 00:01.0 <br>PNP: 002e.0 enabled <br>
PNP: 002e.1 enabled <br>PNP: 002e.2 disabled <br>PNP: 002e.3 enabled <br>
PNP: 002e.4 enabled <br>PNP: 002e.5 enabled <br>PNP: 002e.6 enabled <br>
PNP: 002e.7 disabled <br>PNP: 002e.8 disabled <br>PNP: 002e.9 disabled <br>
PNP: 002e.a disabled <br>scan_static_bus for PCI: 00:01.0 done <br>scan_static_bus for PCI: 00:01.1 <br>
smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled <br>smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled <br>smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled <br>
smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled <br>scan_static_bus for PCI: 00:01.1 done <br>do_pci_scan_bridge for PCI: 00:06.0 <br>
PCI: pci_scan_bus for bus 01 <br>PCI: pci_scan_bus returning with max=001 <br>do_pci_scan_bridge returns max 1 <br>
do_pci_scan_bridge for PCI: 00:0a.0 <br>PCI: pci_scan_bus for bus 02 <br>PCI: pci_scan_bus returning with max=002 <br>
do_pci_scan_bridge returns max 2 <br>do_pci_scan_bridge for PCI: 00:0c.0 <br>PCI: pci_scan_bus for bus 03 <br>
PCI: pci_scan_bus returning with max=003 <br>do_pci_scan_bridge returns max 3 <br>do_pci_scan_bridge for PCI: 00:0d.0 <br>
PCI: pci_scan_bus for bus 04 <br>PCI: pci_scan_bus returning with max=004 <br>do_pci_scan_bridge returns max 4 <br>
do_pci_scan_bridge for PCI: 00:0f.0 <br>PCI: pci_scan_bus for bus 05 <br>PCI: pci_scan_bus returning with max=005 <br>
do_pci_scan_bridge returns max 5 <br>PCI: pci_scan_bus returning with max=005 <br>PCI: pci_scan_bus returning with max=005 <br>
PCI_DOMAIN: 0000 passpw: enabled <br>scan_static_bus for Root Device done <br>done <br>
Allocating resources... <br>Reading resources... <br>Root Device read_resources bus 0 link: 0 <br>
APIC_CLUSTER: 0 read_resources bus 0 link: 0 <br>APIC: 00 missing read_resources <br>APIC_CLUSTER: 0 read_resources bus 0 link: 0 done <br>
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 <br>PCI: 00:18.0 read_resources bus 0 link: 0 <br>PCI: 00:01.0 read_resources bus 0 link: 0 <br>
PCI: 00:01.0 read_resources bus 0 link: 0 done <br>PCI: 00:01.1 read_resources bus 1 link: 0 <br>I2C: 01:50 missing read_resources <br>
I2C: 01:51 missing read_resources <br>I2C: 01:52 missing read_resources <br>I2C: 01:53 missing read_resources <br>
PCI: 00:01.1 read_resources bus 1 link: 0 done <br>PCI: 00:06.0 read_resources bus 1 link: 0 <br>PCI: 00:06.0 read_resources bus 1 link: 0 done <br>
PCI: 00:0a.0 read_resources bus 2 link: 0 <br>PCI: 00:0a.0 read_resources bus 2 link: 0 done <br>PCI: 00:0c.0 read_resources bus 3 link: 0 <br>
PCI: 00:0c.0 read_resources bus 3 link: 0 done <br>PCI: 00:0d.0 read_resources bus 4 link: 0 <br>PCI: 00:0d.0 read_resources bus 4 link: 0 done <br>
PCI: 00:0f.0 read_resources bus 5 link: 0 <br>PCI: 00:0f.0 read_resources bus 5 link: 0 done <br>PCI: 00:18.0 read_resources bus 0 link: 0 done <br>
PCI: 00:18.0 read_resources bus 0 link: 1 <br>PCI: 00:18.0 read_resources bus 0 link: 1 done <br>PCI: 00:18.0 read_resources bus 0 link: 2 <br>
PCI: 00:18.0 read_resources bus 0 link: 2 done <br>PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done <br>Root Device read_resources bus 0 link: 0 done <br>
Done reading resources. <br>Show resources in subtree (Root Device)...After reading. <br> Root Device child on link 0 APIC_CLUSTER: 0 <br>
APIC_CLUSTER: 0 child on link 0 APIC: 00 <br> APIC: 00 <br> PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 <br>
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 400400<br> PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40<br> PCI: 00:18.0 child on link 0 PCI: 00:00.0 <br>
PCI: 00:18.0 resource base 33 size 0 align 0 gran 0 limit 3000 flags 1 index0<br> PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 0<br> PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 2<br>
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 801<br> PCI: 00:00.0 <br> PCI: 00:01.0 child on link 0 PNP: 002e.0 <br>
PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4<br> PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100<br> PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flag0<br>
PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags 3<br> PNP: 002e.0 <br> PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c000010<br>
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 i0<br> PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 i4<br> PNP: 002e.1 <br>
PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c000010<br> PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 i0<br> PNP: 002e.2 <br>
PNP: 002e.2 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 inde0<br> PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 0<br> PNP: 002e.3 <br>
PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c000010<br> PNP: 002e.3 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i2<br> PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 i0<br>
PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 i4<br> PNP: 002e.4 <br> PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c000010<br>
PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit 7ff flags c00001002<br> PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 i0<br> PNP: 002e.5 <br>
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c00<br> PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c02<br> PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 i0<br>
PNP: 002e.6 <br> PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 i0<br> PNP: 002e.7 <br>
PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i0<br> PNP: 002e.7 resource base 800 size 8 align 3 gran 3 limit 7ff flags c000012<br> PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags c00001004<br>
PNP: 002e.8 <br> PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 inde0<br> PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 0<br>
PNP: 002e.9 <br> PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 1000<br> PNP: 002e.a <br>
PCI: 00:01.1 child on link 0 I2C: 01:50 <br> PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in0<br> PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in0<br>
PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in4<br> PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i0<br> PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i4<br>
PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i8<br> I2C: 01:50 <br> I2C: 01:51 <br>
I2C: 01:52 <br> I2C: 01:53 <br> PCI: 00:01.2 <br>
PCI: 00:01.3 <br> PCI: 00:01.3 resource base 0 size 40000 align 18 gran 18 limit ffffffff fla0<br> PCI: 00:02.0 <br>
PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag0<br> PCI: 00:02.1 <br> PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 20<br>
PCI: 00:04.0 <br> PCI: 00:04.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0<br> PCI: 00:05.0 <br>
PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0<br> PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4<br> PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8<br>
PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc<br> PCI: 00:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0<br> PCI: 00:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4<br>
PCI: 00:05.1 <br> PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0<br> PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4<br>
PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8<br> PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc<br> PCI: 00:05.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0<br>
PCI: 00:05.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4<br> PCI: 00:05.2 <br> PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0<br>
PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4<br> PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8<br> PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc<br>
PCI: 00:05.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0<br> PCI: 00:05.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4<br> PCI: 00:06.0 <br>
PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102c<br> PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 84<br> PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80<br>
PCI: 00:06.1 <br> PCI: 00:06.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flag0<br> PCI: 00:08.0 <br>
PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag0<br> PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind4<br> PCI: 00:08.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 28<br>
PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 20c<br> PCI: 00:09.0 <br> PCI: 00:0a.0 <br>
PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c<br> PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4<br> PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80<br>
PCI: 00:0b.0 <br> PCI: 00:0c.0 <br> PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c<br>
PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4<br> PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80<br> PCI: 00:0d.0 <br>
PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c<br> PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4<br> PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80<br>
PCI: 00:0e.0 <br> PCI: 00:0f.0 <br> PCI: 00:0f.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c<br>
PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4<br> PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80<br> PCI: 00:18.1 <br>
PCI: 00:18.2 <br> PCI: 00:18.3 <br> PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff fl4<br>
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: f<br>PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff<br>PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff<br>
PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe<br>PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff<br>PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe<br>
PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff<br>PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe<br>PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff<br>
PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe<br>PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff<br>PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe<br>
PCI: 00:01.1 60 * [0x0 - 0xff] io <br>PCI: 00:01.1 64 * [0x400 - 0x4ff] io <br>PCI: 00:01.1 68 * [0x800 - 0x8ff] io <br>
PCI: 00:01.1 10 * [0xc00 - 0xc3f] io <br>PCI: 00:01.1 20 * [0xc40 - 0xc7f] io <br>PCI: 00:01.1 24 * [0xc80 - 0xcbf] io <br>
PCI: 00:04.0 20 * [0xcc0 - 0xccf] io <br>PCI: 00:05.0 20 * [0xcd0 - 0xcdf] io <br>PCI: 00:05.1 20 * [0xce0 - 0xcef] io <br>
PCI: 00:05.2 20 * [0xcf0 - 0xcff] io <br>PCI: 00:05.0 10 * [0x1000 - 0x1007] io <br>PCI: 00:05.0 18 * [0x1008 - 0x100f] io <br>
PCI: 00:05.1 10 * [0x1010 - 0x1017] io <br>PCI: 00:05.1 18 * [0x1018 - 0x101f] io <br>PCI: 00:05.2 10 * [0x1020 - 0x1027] io <br>
PCI: 00:05.2 18 * [0x1028 - 0x102f] io <br>PCI: 00:08.0 14 * [0x1030 - 0x1037] io <br>PCI: 00:05.0 14 * [0x1038 - 0x103b] io <br>
PCI: 00:05.0 1c * [0x103c - 0x103f] io <br>PCI: 00:05.1 14 * [0x1040 - 0x1043] io <br>PCI: 00:05.1 1c * [0x1044 - 0x1047] io <br>
PCI: 00:05.2 14 * [0x1048 - 0x104b] io <br>PCI: 00:05.2 1c * [0x104c - 0x104f] io <br>PCI: 00:18.0 compute_resources_io: base: 1050 size: 2000 align: 12 gran: 12 lime<br>
PCI: 00:18.0 00 * [0x0 - 0x1fff] io <br>PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 e<br>PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:f<br>
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif<br>PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif<br>PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie<br>
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif<br>PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie<br>PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif<br>
PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie<br>PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif<br>PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie<br>
PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif<br>PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie<br>PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie<br>
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff<br>PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff<br>PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe<br>
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff<br>PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe<br>PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff<br>
PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe<br>PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff<br>PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe<br>
PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff<br>PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe<br>PCI: 00:01.3 10 * [0x0 - 0x3ffff] mem <br>
PCI: 00:06.1 10 * [0x40000 - 0x43fff] mem <br>PCI: 00:01.0 14 * [0x44000 - 0x44fff] mem <br>PCI: 00:02.0 10 * [0x45000 - 0x45fff] mem <br>
PCI: 00:05.0 24 * [0x46000 - 0x46fff] mem <br>PCI: 00:05.1 24 * [0x47000 - 0x47fff] mem <br>PCI: 00:05.2 24 * [0x48000 - 0x48fff] mem <br>
PCI: 00:08.0 10 * [0x49000 - 0x49fff] mem <br>PCI: 00:02.1 10 * [0x4a000 - 0x4a0ff] mem <br>PCI: 00:08.0 18 * [0x4a100 - 0x4a1ff] mem <br>
PCI: 00:08.0 1c * [0x4a200 - 0x4a20f] mem <br>PCI: 00:18.0 compute_resources_mem: base: 4a210 size: 100000 align: 20 gran: 20e<br>PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem <br>
PCI: 00:18.0 01 * [0x4000000 - 0x40fffff] mem <br>PCI_DOMAIN: 0000 compute_resources_mem: base: 4100000 size: 4100000 align: 26 ge<br>avoid_fixed_resources: PCI_DOMAIN: 0000 <br>
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff <br>avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff <br>constrain_resources: PCI_DOMAIN: 0000 <br>
constrain_resources: PCI: 00:18.0 <br>constrain_resources: PCI: 00:00.0 <br>constrain_resources: PCI: 00:01.0 <br>
constrain_resources: PNP: 002e.0 <br>constrain_resources: PNP: 002e.1 <br>constrain_resources: PNP: 002e.3 <br>
skipping PNP: 002e.3@62 fixed resource, size=0! <br>constrain_resources: PNP: 002e.4 <br>constrain_resources: PNP: 002e.5 <br>
constrain_resources: PNP: 002e.6 <br>constrain_resources: PCI: 00:01.1 <br>constrain_resources: I2C: 01:50 <br>
constrain_resources: I2C: 01:51 <br>constrain_resources: I2C: 01:52 <br>constrain_resources: I2C: 01:53 <br>
constrain_resources: PCI: 00:01.2 <br>constrain_resources: PCI: 00:01.3 <br>constrain_resources: PCI: 00:02.0 <br>
constrain_resources: PCI: 00:02.1 <br>constrain_resources: PCI: 00:04.0 <br>constrain_resources: PCI: 00:05.0 <br>
constrain_resources: PCI: 00:05.1 <br>constrain_resources: PCI: 00:05.2 <br>constrain_resources: PCI: 00:06.0 <br>
constrain_resources: PCI: 00:06.1 <br>constrain_resources: PCI: 00:08.0 <br>constrain_resources: PCI: 00:0a.0 <br>
constrain_resources: PCI: 00:0c.0 <br>constrain_resources: PCI: 00:0d.0 <br>constrain_resources: PCI: 00:0f.0 <br>
constrain_resources: PCI: 00:18.1 <br>constrain_resources: PCI: 00:18.2 <br>constrain_resources: PCI: 00:18.3 <br>
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff <br> lim->base 00001000 lim->limit 0000ffff <br>avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff <br>
lim->base 00000000 lim->limit febfffff <br>Setting resources... <br>PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limf<br>
Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io <br>PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gre<br>PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:f<br>
Assigned: PCI: 00:01.1 60 * [0x1000 - 0x10ff] io <br>Assigned: PCI: 00:01.1 64 * [0x1400 - 0x14ff] io <br>Assigned: PCI: 00:01.1 68 * [0x1800 - 0x18ff] io <br>
Assigned: PCI: 00:01.1 10 * [0x1c00 - 0x1c3f] io <br>Assigned: PCI: 00:01.1 20 * [0x1c40 - 0x1c7f] io <br>Assigned: PCI: 00:01.1 24 * [0x1c80 - 0x1cbf] io <br>
Assigned: PCI: 00:04.0 20 * [0x1cc0 - 0x1ccf] io <br>Assigned: PCI: 00:05.0 20 * [0x1cd0 - 0x1cdf] io <br>Assigned: PCI: 00:05.1 20 * [0x1ce0 - 0x1cef] io <br>
Assigned: PCI: 00:05.2 20 * [0x1cf0 - 0x1cff] io <br>Assigned: PCI: 00:05.0 10 * [0x2000 - 0x2007] io <br>Assigned: PCI: 00:05.0 18 * [0x2008 - 0x200f] io <br>
Assigned: PCI: 00:05.1 10 * [0x2010 - 0x2017] io <br>Assigned: PCI: 00:05.1 18 * [0x2018 - 0x201f] io <br>Assigned: PCI: 00:05.2 10 * [0x2020 - 0x2027] io <br>
Assigned: PCI: 00:05.2 18 * [0x2028 - 0x202f] io <br>Assigned: PCI: 00:08.0 14 * [0x2030 - 0x2037] io <br>Assigned: PCI: 00:05.0 14 * [0x2038 - 0x203b] io <br>
Assigned: PCI: 00:05.0 1c * [0x203c - 0x203f] io <br>Assigned: PCI: 00:05.1 14 * [0x2040 - 0x2043] io <br>Assigned: PCI: 00:05.1 1c * [0x2044 - 0x2047] io <br>
Assigned: PCI: 00:05.2 14 * [0x2048 - 0x204b] io <br>Assigned: PCI: 00:05.2 1c * [0x204c - 0x204f] io <br>PCI: 00:18.0 allocate_resources_io: next_base: 2050 size: 2000 align: 12 gran: e<br>
PCI: 00:06.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff<br>PCI: 00:06.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e<br>PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff<br>
PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e<br>PCI: 00:0c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff<br>PCI: 00:0c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e<br>
PCI: 00:0d.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff<br>PCI: 00:0d.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e<br>PCI: 00:0f.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff<br>
PCI: 00:0f.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e<br>PCI_DOMAIN: 0000 allocate_resources_mem: base:f8000000 size:4100000 align:26 grf<br>Assigned: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem <br>
Assigned: PCI: 00:18.0 01 * [0xfc000000 - 0xfc0fffff] mem <br>PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fc100000 size: 4100000 alige<br>PCI: 00:18.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f<br>
PCI: 00:18.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e<br>PCI: 00:06.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f<br>PCI: 00:06.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e<br>
PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f<br>PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e<br>PCI: 00:0c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f<br>
PCI: 00:0c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e<br>PCI: 00:0d.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f<br>PCI: 00:0d.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e<br>
PCI: 00:0f.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f<br>PCI: 00:0f.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e<br>PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:100000 align:20 gran:20f<br>
Assigned: PCI: 00:01.3 10 * [0xfc000000 - 0xfc03ffff] mem <br>Assigned: PCI: 00:06.1 10 * [0xfc040000 - 0xfc043fff] mem <br>Assigned: PCI: 00:01.0 14 * [0xfc044000 - 0xfc044fff] mem <br>
Assigned: PCI: 00:02.0 10 * [0xfc045000 - 0xfc045fff] mem <br>Assigned: PCI: 00:05.0 24 * [0xfc046000 - 0xfc046fff] mem <br>Assigned: PCI: 00:05.1 24 * [0xfc047000 - 0xfc047fff] mem <br>
Assigned: PCI: 00:05.2 24 * [0xfc048000 - 0xfc048fff] mem <br>Assigned: PCI: 00:08.0 10 * [0xfc049000 - 0xfc049fff] mem <br>Assigned: PCI: 00:02.1 10 * [0xfc04a000 - 0xfc04a0ff] mem <br>
Assigned: PCI: 00:08.0 18 * [0xfc04a100 - 0xfc04a1ff] mem <br>Assigned: PCI: 00:08.0 1c * [0xfc04a200 - 0xfc04a20f] mem <br>PCI: 00:18.0 allocate_resources_mem: next_base: fc04a210 size: 100000 align: 20e<br>
PCI: 00:06.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif<br>PCI: 00:06.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane<br>PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif<br>
PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane<br>PCI: 00:0c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif<br>PCI: 00:0c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane<br>
PCI: 00:0d.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif<br>PCI: 00:0d.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane<br>PCI: 00:0f.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif<br>
PCI: 00:0f.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane<br>Root Device assign_resources, bus 0 link: 0 <br>0: mmio_basek=003e0000, basek=00000300, limitk=00080000 <br>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 <br>PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io ><br>PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 mem><br>
PCI: 00:18.0 assign_resources, bus 0 link: 0 <br>PCI: 00:01.0 14 <- [0x00fc044000 - 0x00fc044fff] size 0x00001000 gran 0x0c mem <br>PCI: 00:01.0 assign_resources, bus 0 link: 0 <br>
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io <br>PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq <br>PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq <br>
PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io <br>PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq <br>PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io <br>
PNP: 002e.3 62 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00o<br>PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq <br>PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq <br>
PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io <br>PNP: 002e.4 62 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io <br>PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq <br>
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io <br>PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io <br>PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq <br>
PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq <br>PCI: 00:01.0 assign_resources, bus 0 link: 0 <br>PCI: 00:01.1 10 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io <br>
PCI: 00:01.1 20 <- [0x0000001c40 - 0x0000001c7f] size 0x00000040 gran 0x06 io <br>PCI: 00:01.1 24 <- [0x0000001c80 - 0x0000001cbf] size 0x00000040 gran 0x06 io <br>PCI: 00:01.1 60 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io <br>
PCI: 00:01.1 64 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io <br>PCI: 00:01.1 68 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io <br>PCI: 00:01.1 assign_resources, bus 1 link: 0 <br>
PCI: 00:01.1 assign_resources, bus 1 link: 0 <br>PCI: 00:01.3 10 <- [0x00fc000000 - 0x00fc03ffff] size 0x00040000 gran 0x12 mem <br>PCI: 00:02.0 10 <- [0x00fc045000 - 0x00fc045fff] size 0x00001000 gran 0x0c mem <br>
PCI: 00:02.1 10 <- [0x00fc04a000 - 0x00fc04a0ff] size 0x00000100 gran 0x08 mem <br>PCI: 00:04.0 20 <- [0x0000001cc0 - 0x0000001ccf] size 0x00000010 gran 0x04 io <br>PCI: 00:05.0 10 <- [0x0000002000 - 0x0000002007] size 0x00000008 gran 0x03 io <br>
PCI: 00:05.0 14 <- [0x0000002038 - 0x000000203b] size 0x00000004 gran 0x02 io <br>PCI: 00:05.0 18 <- [0x0000002008 - 0x000000200f] size 0x00000008 gran 0x03 io <br>PCI: 00:05.0 1c <- [0x000000203c - 0x000000203f] size 0x00000004 gran 0x02 io <br>
PCI: 00:05.0 20 <- [0x0000001cd0 - 0x0000001cdf] size 0x00000010 gran 0x04 io <br>PCI: 00:05.0 24 <- [0x00fc046000 - 0x00fc046fff] size 0x00001000 gran 0x0c mem <br>PCI: 00:05.1 10 <- [0x0000002010 - 0x0000002017] size 0x00000008 gran 0x03 io <br>
PCI: 00:05.1 14 <- [0x0000002040 - 0x0000002043] size 0x00000004 gran 0x02 io <br>PCI: 00:05.1 18 <- [0x0000002018 - 0x000000201f] size 0x00000008 gran 0x03 io <br>PCI: 00:05.1 1c <- [0x0000002044 - 0x0000002047] size 0x00000004 gran 0x02 io <br>
PCI: 00:05.1 20 <- [0x0000001ce0 - 0x0000001cef] size 0x00000010 gran 0x04 io <br>PCI: 00:05.1 24 <- [0x00fc047000 - 0x00fc047fff] size 0x00001000 gran 0x0c mem <br>PCI: 00:05.2 10 <- [0x0000002020 - 0x0000002027] size 0x00000008 gran 0x03 io <br>
PCI: 00:05.2 14 <- [0x0000002048 - 0x000000204b] size 0x00000004 gran 0x02 io <br>PCI: 00:05.2 18 <- [0x0000002028 - 0x000000202f] size 0x00000008 gran 0x03 io <br>PCI: 00:05.2 1c <- [0x000000204c - 0x000000204f] size 0x00000004 gran 0x02 io <br>
PCI: 00:05.2 20 <- [0x0000001cf0 - 0x0000001cff] size 0x00000010 gran 0x04 io <br>PCI: 00:05.2 24 <- [0x00fc048000 - 0x00fc048fff] size 0x00001000 gran 0x0c mem <br>PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o<br>
PCI: 00:06.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>PCI: 00:06.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>PCI: 00:06.1 10 <- [0x00fc040000 - 0x00fc043fff] size 0x00004000 gran 0x0e mem <br>
PCI: 00:08.0 10 <- [0x00fc049000 - 0x00fc049fff] size 0x00001000 gran 0x0c mem <br>PCI: 00:08.0 14 <- [0x0000002030 - 0x0000002037] size 0x00000008 gran 0x03 io <br>PCI: 00:08.0 18 <- [0x00fc04a100 - 0x00fc04a1ff] size 0x00000100 gran 0x08 mem <br>
PCI: 00:08.0 1c <- [0x00fc04a200 - 0x00fc04a20f] size 0x00000010 gran 0x04 mem <br>PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o<br>PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>
PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>PCI: 00:0c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o<br>PCI: 00:0c.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>
PCI: 00:0c.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>PCI: 00:0d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o<br>PCI: 00:0d.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>
PCI: 00:0d.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>PCI: 00:0f.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o<br>PCI: 00:0f.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>
PCI: 00:0f.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m<br>PCI: 00:18.0 assign_resources, bus 0 link: 0 <br>PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem ><br>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 <br>Root Device assign_resources, bus 0 link: 0 <br>Done setting resources. <br>
Show resources in subtree (Root Device)...After assigning values. <br> Root Device child on link 0 APIC_CLUSTER: 0 <br> APIC_CLUSTER: 0 child on link 0 APIC: 00 <br>
APIC: 00 <br> PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 <br> PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flag0<br>
PCI_DOMAIN: 0000 resource base f8000000 size 4100000 align 26 gran 0 limit fe0<br> PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0000<br> PCI_DOMAIN: 0000 resource base <br><br><br><div class="gmail_quote">
2012/1/30 Julian Shulika <span dir="ltr"><<a href="mailto:hercares@gmail.com">hercares@gmail.com</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi. I compiled coreboot image for Asus m2n-e (mcp55,ite 8716f). This board turns off after few seconds<br>
The log from serial<br><br>Welcome to minicom 2.5<br><br>OPTIONS: <br>
Compiled on Dec 4 2011, 11:23:38. <br>Port /dev/ttyS0 <br> <br>
Press CTRL-A Z for help on special keys <br> <br> <br>
<br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>*sysinfo range: [000cf000,000cf730] <br>
bsp_apicid=0x00 <br>Enabling routing table for node 00 done.<br>Enabling UP settings <br>Disabling read/write/fill probes for UP... done.<br>
coherent_ht_finalize <br>done <br>core0 started: <br>started ap apicid: <br>SBLink=00<br>NC node|link=00<br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x807f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 <br>dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x1 <br>
after optimize_link_read_pointers_chain, reset_needed=0x1 <br>mcp55_num:01 <br>ht reset - <br>
<br> <br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>
*sysinfo range: [000cf000,000cf730] <br>bsp_apicid=0x00 <br>Enabling routing table for node 00 done. <br>
Enabling UP settings <br>Disabling read/write/fill probes for UP... done. <br>coherent_ht_finalize <br>
done <br>core0 started: <br>started ap apicid: <br>
SBLink=00 <br>NC node|link=00 <br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x7f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x0 <br>
after optimize_link_read_pointers_chain, reset_needed=0x0 <br>mcp55_num:01 <br>Ram1.00 <br>
setting up CPU 00 northbridge registers <br>done. <br>Ram2.00 <br>
sdram_set_spd_registers: paramx :000cef20 <br>Enable 64MuxMode & BurstLength32 <br>Unbuffered <br>
333MHz <br>333MHz <br>set_ecc spd_device: 0x51 <br>
Interleaving disabled <br>RAM end at 0x00080000 kB <br>Ram3 <br>
ECC enabled <br>Initializing memory: done <br>Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>
set DQS timing:RcvrEn:Pass1: 00 <br> CTLRMaxDelay=03 <br> done <br>
set DQS timing:DQSPos: 00 <br>TrainDQSRdWrPos: buf_a:000ce9f0 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br>
done <br>set DQS timing:RcvrEn:Pass2: 00 <br> CTLRMaxDelay=58 <br>
done <br>Total DQS Training : tsc [00]=0000000012e40bef <br>Total DQS Training : tsc [01]=000000001358f446 <br>
Total DQS Training : tsc [02]=0000000018d60c82 <br>Total DQS Training : tsc [03]=0000000019771d46 <br>Ram4 <br>
v_esp=000cef68 <br>testx = 5a5a5a5a <br> <br> <br>
<br>INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- <br> <br>
Issuing SOFT_RESET... <br> <br> <br>
coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>*sysinfo range: [000cf000,000cf730] <br>bsp_apicid=0x00 <br>
Enabling routing table for node 00 done. <br>Enabling UP settings <br>Disabling read/write/fill probes for UP... done. <br>
coherent_ht_finalize <br>done <br>core0 started: <br>
started ap apicid: <br>SBLink=00 <br>NC node|link=00 <br>
entering optimize_link_incoherent_ht <br>sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>
pos=0x8a, unfiltered freq_cap=0x8075 <br>pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x7f <br>
pos=0x52, filtered freq_cap=0x7f <br>freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>
dev1 input width=0x1 <br>dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>
old dev1 input|output width=0x11 <br>dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>
after ht_optimize_link for link pair 0, reset_needed=0x0 <br>after optimize_link_read_pointers_chain, reset_needed=0x0 <br>mcp55_num:01 <br>
Ram1.00 <br>setting up CPU 00 northbridge registers <br>done. <br>
Ram2.00 <br>sdram_set_spd_registers: paramx :000cef20 <br>Enable 64MuxMode & BurstLength32 <br>
Unbuffered <br>333MHz <br>333MHz <br>
set_ecc spd_device: 0x51 <br>Interleaving disabled <br>RAM end at 0x00080000 kB <br>
Ram3 <br>ECC enabled <br>Initializing memory: done <br>
Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>set DQS timing:RcvrEn:Pass1: 00 <br> CTLRMaxDelay=03 <br>
done <br>set DQS timing:DQSPos: 00 <br>TrainDQSRdWrPos: buf_a:000ce9f0 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br> done <br>set DQS timing:RcvrEn:Pass2: 00 <br>
CTLRMaxDelay=58 <br> done <br>Total DQS Training : tsc [00]=0000000012e3eacf <br>
Total DQS Training : tsc [01]=000000001358d326 <br>Total DQS Training : tsc [02]=0000000018d97cfa <br>Total DQS Training : tsc [03]=00000000197a8c56 <br>
Ram4 <br>v_esp=000cef68 <br>testx = 5a5a5a5a <br>
Copying data from cache to RAM -- switching to use RAM as stack... D <br> <br> <br>
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- <br> <br>Issuing SOFT_RESET... <br>
<br> <br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>
*sysinfo range: [000cf000,000cf730] <br>bsp_apicid=0x00 <br>Enabling routing table for node 00 done. <br>
Enabling UP settings <br>Disabling read/write/fill probes for UP... done. <br>coherent_ht_finalize <br>
done <br>core0 started: <br>started ap apicid: <br>
SBLink=00 <br>NC node|link=00 <br>entering optimize_link_incoherent_ht <br>
sysinfo->link_pair_num=0x1 <br>entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>
pos=0x8a, filtered freq_cap=0x75 <br>pos=0x52, unfiltered freq_cap=0x7f <br>pos=0x52, filtered freq_cap=0x7f <br>
freq_cap1=0x75, freq_cap2=0x7f <br>dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>
width_cap1=0x11, width_cap2=0x11 <br>dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>
dev1 output ln_width1=0x4, ln_width2=0x4 <br>dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>
dev2 input|output width=0x11 <br>old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x0 <br>
after optimize_link_read_pointers_chain, reset_needed=0x0 <br>mcp55_num:01 <br>Ram1.00 <br>
setting up CPU 00 northbridge registers <br>done. <br>Ram2.00 <br>
sdram_set_spd_registers: paramx :000cef20 <br>Enable 64MuxMode & BurstLength32 <br>Unbuffered <br>
333MHz <br>333MHz <br>set_ecc spd_device: 0x51 <br>
Interleaving disabled <br>RAM end at 0x00080000 kB <br>Ram3 <br>
ECC enabled <br>Initializing memory: done <br>Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>
set DQS timing:RcvrEn:Pass1: 00 <br> CTLRMaxDelay=03 <br> done <br>
set DQS timing:DQSPos: 00 <br>TrainDQSRdWrPos: buf_a:000ce9f0 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br>
done <br>set DQS timing:RcvrEn:Pass2: 00 <br> CTLRMaxDelay=58 <br>
done <br>Total DQS Training : tsc [00]=0000000012e3ed63 <br>Total DQS Training : tsc [01]=000000001358f68a <br>
Total DQS Training : tsc [02]=0000000018d73a6a <br>Total DQS Training : tsc [03]=0000000019784e5a <br>Ram4 <br>
v_esp=000cef68 <br>testx = 5a5a5a5a <br>Copying data from cache to RAM -- switching to use RAM as stack... m <br>
<br> <br>INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- <br>
<br>Issuing SOFT_RESET... <br> <br>
<br>coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... <br>*sysinfo range: [000cf000,000cf730] <br>
bsp_apicid=0x00 <br>Enabling routing table for node 00 done. <br>Enabling UP settings <br>
Disabling read/write/fill probes for UP... done. <br>coherent_ht_finalize <br>done <br>
core0 started: <br>started ap apicid: <br>SBLink=00 <br>
NC node|link=00 <br>entering optimize_link_incoherent_ht <br>sysinfo->link_pair_num=0x1 <br>
entering ht_optimize_link <br>pos=0x8a, unfiltered freq_cap=0x8075 <br>pos=0x8a, filtered freq_cap=0x75 <br>
pos=0x52, unfiltered freq_cap=0x7f <br>pos=0x52, filtered freq_cap=0x7f <br>freq_cap1=0x75, freq_cap2=0x7f <br>
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 <br>width_cap1=0x11, width_cap2=0x11 <br>
dev1 input ln_width1=0x4, ln_width2=0x4 <br>dev1 input width=0x1 <br>dev1 output ln_width1=0x4, ln_width2=0x4 <br>
dev1 input|output width=0x11 <br>old dev1 input|output width=0x11 <br>dev2 input|output width=0x11 <br>
old dev2 input|output width=0x11 <br>after ht_optimize_link for link pair 0, reset_needed=0x0 <br>after optimize_link_read_pointers_chain, reset_needed=0x0 <br>
mcp55_num:01 <br>Ram1.00 <br>setting up CPU 00 northbridge registers <br>
done. <br>Ram2.00 <br>sdram_set_spd_registers: paramx :000cef20 <br>
Enable 64MuxMode & BurstLength32 <br>Unbuffered <br>333MHz <br>
333MHz <br>set_ecc spd_device: 0x51 <br>Interleaving disabled <br>
RAM end at 0x00080000 kB <br>Ram3 <br>ECC enabled <br>
Initializing memory: done <br>Setting variable MTRR 2, base: 0MB, range: 512MB, type WB <br>set DQS timing:RcvrEn:Pass1: 00 <br>
CTLRMaxDelay=03 <br> done <br>set DQS timing:DQSPos: 00 <br>
TrainDQSRdWrPos: buf_a:000ce9f0 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>
TrainDQSPos: MutualCSPassW[48] :000ce8c8 <br>TrainDQSPos: MutualCSPassW[48] :000ce8d8 <br> done <br>
set DQS timing:RcvrEn:Pass2: 00 <br> CTLRMaxDelay=58 <br> done <br>
Total DQS Training : tsc [00]=0000000012e4504b <br>Total DQS Training : tsc [01]=0000000013593c4a <br>Total DQS Training : tsc [02]=0000000018d6d4b2 <br>
Total DQS Training : tsc [03]=000000001977e9ce <br>Ram4 <br>v_esp=000cef68 <br>
testx = 5a5a5a5a <br>Copying data from cache to RAM -- switching to use RAM as stack... <br><br>
</blockquote></div><br>