<br><br><div class="gmail_quote">---------- Forwarded message ----------<br>From: <b class="gmail_sendername">Julian Shulika</b> <span dir="ltr"><<a href="mailto:hercares@gmail.com">hercares@gmail.com</a>></span><br>
Date: 2012/3/26<br>Subject: Re: coreboot and opteron 8431<br>To: Arne Georg Gleditsch <<a href="mailto:arne@gledits.ch">arne@gledits.ch</a>><br><br><br>I tried to port asus l1n64 more than one year. This board also based on mcp55,this is only one board for AMD 4x4 platform. <span lang="en"><span>It differs</span> <span>from other similar board by different scheme<div class="im">
<br>
<br>Tyan S2912, supermicro h8dmr have </div></span></span><span lang="en"><span>connection diagram, if I use just cpu0,I can't use second mcp55 </span></span><span lang="en"><span><b>mcp55 <->cpu1 <-> cpu0 <-> mcp55<br>
<br><br></b>Asus L1N64 has different </span></span><span lang="en"><span>connection diagram <b>mcp55 <-> mcp55<->cpu0 <-> cpu1<br></b><div class="im">I saw your posts when you try to help guy with supermicro board,but </div>
</span></span><span lang="en"><span>I'm stuck</span> <span>in one place</span></span><span lang="en"><span>,because </span></span><span lang="en"><span>I have not</span> <span>reached</span></span>
to memory init, I think it's because of wrong devicetree. Could you
please look at lspci output, may be you can see something...<br>
<span lang="en"><span>Thanks for your </span></span><span lang="en"><span>work done<br><br>chip northbridge/amd/amdfam10/root_complex # Root complex<br> device lapic_cluster 0 on # (L)APIC cluster<br> chip cpu/amd/socket_F_1207 # CPU socket<br>
device lapic 0 on end # Local APIC of the CPU<br> end<br> end<br> device pci_domain 0 on # PCI domain<br> subsystemid 0x10de 0x81fb inherit<br> chip northbridge/amd/amdfam10 # Northbridge / RAM controller<br>
device pci 18.0 on end<br> device pci 18.0 on end<br> chip southbridge/nvidia/mcp55 # Southbridge<br> device pci 0.0 on end # HT<br> device pci 1.0 on end # LPC<br> device pci 1.1 on end # LPC<br>
device pci 5.1 on end # SATA 1<br> device pci 5.2 on end # SATA 2<br> device pci a.0 off end # PCI E 5<br> device pci f.0 off end # PCI E 5 <br> end<br> device pci 18.0 on # SB on link 2<br>
chip southbridge/nvidia/mcp55 # Southbridge<br> device pci 0.0 on end # HT<br> device pci 1.0 on # LPC<br> chip superio/ite/it8716f # Super I/O<br>
device pnp 2e.0 on # Floppy<br>
io 0x60 = 0x3f0<br> irq 0x70 = 6<br> drq 0x74 = 2<br> end<br> device pnp 2e.1 on # Com1<br> io 0x60 = 0x3f8<br> irq 0x70 = 4<br>
end<br> device pnp 2e.2 off # Com2 (N/A)<br> end<br> device pnp 2e.3 on # Parallel port<br> io 0x60 = 0x378<br> io 0x62 = 0x000<br>
irq 0x70 = 7<br> drq 0x74 = 4<br> end<br> device pnp 2e.4 on # Environment controller<br> io 0x60 = 0x290<br> io 0x62 = 0x000<br>
irq 0x70 = 0<br> end<br> device pnp 2e.5 on # PS/2 keyboard<br> io 0x60 = 0x60<br> io 0x62 = 0x64<br> irq 0x70 = 1 # PS/2 keyboard IRQ<br>
end<br> device pnp 2e.6 on # PS/2 mouse<br> irq 0x70 = 12 # PS/2 mouse IRQ<br> end<br> device pnp 2e.7 off # GPIO<br> io 0x60 = 0x0000 # SMI# Normal Run Access<br>
io 0x62 = 0x800 # Simple I/O<br> io 0x64 = 0x0000 # Serial Flash I/F<br> end<br> device pnp 2e.8 off # MIDI (N/A)<br> end<br>
device pnp 2e.9 off # Game port (N/A)<br>
end<br> device pnp 2e.a off # Consumer IR (N/A)<br> end<br> end # Super I/O<br> end<br> device pci 1.1 on # SM 0<br>
chip drivers/generic/generic # DIMM 0-0-0<br> device i2c 50 on end<br> end<br> chip drivers/generic/generic # DIMM 0-0-1<br> device i2c 51 on end<br> end<br>
chip drivers/generic/generic # DIMM 0-1-0<br> device i2c 52 on end<br> end<br> chip drivers/generic/generic # DIMM 0-1-1<br> device i2c 53 on end<br> end<br>
<br> end<br> <br> device pci 2.0 on end # USB 1.1<br> device pci 2.1 on end # USB 2<br> device pci 4.0 on end # IDE<br> device pci 5.0 on end # SATA 0<br>
device pci 5.1 on end # SATA 1<br> device pci 5.2 on end # SATA 2<br> device pci 6.0 on # PCI<br> device pci 6.0 on end<br> end<br> device pci 6.1 on end # AZA<br>
device pci 8.0 on end # NIC<br> device pci 9.0 on end # NIC<br> device pci a.0 on end # PCI E 5<br> device pci d.0 on end # PCI E 2<br> device pci e.0 on end # PCI E 1<br>
device pci f.0 on end # PCI E 0<br> register "ide0_enable" = "1"<br> register "sata0_enable" = "1"<br> register "sata1_enable" = "1"<br>
# 1: SMBus under 2e.8, 2: SM0 3: SM1<br> register "mac_eeprom_smbus" = "3"<br> register "mac_eeprom_addr" = "0x51"<br> end<br> end<br> device pci 18.1 on end<br>
device pci 18.2 on end<br> device pci 18.3 on end<br> device pci 18.4 on end<br> end<br> end<br> # chip drivers/generic/debug<br> # device pnp 0.0 off end # chip name<br> # device pnp 0.1 on end # pci_regs_all<br>
# device pnp 0.2 on end # mem<br> # device pnp 0.3 off end # cpuid<br> # device pnp 0.4 on end # smbus_regs_all<br> # device pnp 0.5 off end # dual core msr<br> # device pnp 0.6 off end # cache size<br>
# device pnp 0.7 off end # tsc<br> # device pnp 0.8 off end # io<br> # device pnp 0.9 off end # io<br> # end<br>end<br><br></span></span>
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