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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Don’t worry.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">If the hardware is ok, you can try my last patch which was sent to list and CC to you. I am pretty sure it can work.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Joe<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org]
<b>On Behalf Of </b>Andy Sharp<br>
<b>Sent:</b> Tuesday, June 12, 2012 2:58 AM<br>
<b>To:</b> She Kairui<br>
<b>Cc:</b> coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] PCIe devices not enabled on amd/persimmon<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I can now confirm this. Despite the hardware documentation for the board clearly showing the PCIe slot as being on the south bridge, it is not. I got a PCIe extension cable this morning that would actually fit, and the device plugged
in shows to be a child of device 6.0, which is the third PCIe port on the northbridge/cpu. Sigh.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">This is a big bummer for me, as my employer has a design based on persimmon, except all the devices are on the southbridge instead of the northbridge, and we are struggling to get coreboot to see them and yet not hang. I know it can be
done, because the BIOS does enable all the devices and boots, so it's just coreboot that isn't quite getting it right.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Cheers,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">a<o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><o:p> </o:p></p>
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<p class="MsoNormal">On Sat, Jun 9, 2012 at 11:10 AM, She Kairui <<a href="mailto:shekairui@gmail.com" target="_blank">shekairui@gmail.com</a>> wrote:<o:p></o:p></p>
<p class="MsoNormal">2012/6/9, Andy Sharp <<a href="mailto:andywyse6@gmail.com">andywyse6@gmail.com</a>>:<br>
> It's a persimmon board ~:^)<br>
><br>
> I'd be happy to test any patches. Meanwhile, I'm working on a patch to<br>
> properly enable the southbridge PCIe devices so they can be scanned.<br>
> Wolfgang (Wolfie?) is quite correct, the code that enables/deresets those<br>
> PCIe ports happens after the bus is scanned. When nothing shows up on the<br>
> bus scan, the code powers down those devices right after it [too late]<br>
> powers them up. Broken.<br>
><br>
> This persimmon board is made by iBASE. and is a mini-ITX. It has a PCIe<br>
> slot and a mini-PCIe card socket on the sb800 PCIe ports.<br>
I have a persimmon Rev. D board, I found NONE of the PCIe devices is<br>
from SB800 GPP.<br>
You can double check it by booting from the factory BIOS.<br>
Thanks<br>
<br>
--<br>
Kerry Sheh<br>
> I may have earlier said that it had a USB3 ctlr, that was my bad. So many twisty<br>
> passages....<br>
><br>
> I'll try out various combinations of the various patches you good folks<br>
> have been throwing my way, plus some of my own ideas and let the list know<br>
> what happens.<br>
><br>
> Cheers,<br>
><br>
> a<br>
><br>
><br>
><br>
> On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <<a href="mailto:dave@se-eng.com">dave@se-eng.com</a>> wrote:<br>
><br>
>> There shouldn't be any need to guess if it is a Persimmon. On a<br>
>> Persimmon board, next to the SATA connectors there should be<br>
>> printing that says "DB FT1".<br>
>><br>
>> The Persimmon can also have up to two PCIe Ethernet chips on it.<br>
>><br>
>> dave<br>
>><br>
>> ----- Original Message -----<br>
>> > From: "Zheng Bao" <<a href="mailto:Zheng.Bao@amd.com">Zheng.Bao@amd.com</a>><br>
>> > To: "Andy Sharp" <<a href="mailto:andywyse6@gmail.com">andywyse6@gmail.com</a>><br>
>> > Cc: "<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>" <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>><br>
>> > Sent: Friday, June 8, 2012 5:37:58 AM<br>
>> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon<br>
>> ><br>
>> > Hi, Andy,<br>
>> > The persimmon board I have got doesn't have any PCIe slot or onboard<br>
>> > PCIe device attached to SB800. And I am wondering if you actually<br>
>> > use a inagua board, which has the same APU & SB with persimmon and 2<br>
>> > minipcie slots other than that.<br>
>> ><br>
>> > Let us assume you are testing on Inagua.<br>
>> > Here is my patch for the PCIe on SB800. There was a bug. It is just a<br>
>> > workaround patch, not ready for submitting.<br>
>> ><br>
>> > This patch can fix the sb800/pcie issue on Inagua. If you have your<br>
>> > work based on persimmon, please note the devicetree.cb should be<br>
>> > modify as Inagua.<br>
>> > The dev15func[0123] should be enabled and the gpp_configuration<br>
>> > should be 4.<br>
>> ><br>
>> > Joe<br>
>> ><br>
>> > diff --git a/src/southbridge/amd/cimx/sb800/late.c<br>
>> > b/src/southbridge/amd/cimx/sb800/late.c<br>
>> > index 0ce82b3..34cd937 100644<br>
>> > --- a/src/southbridge/amd/cimx/sb800/late.c<br>
>> > +++ b/src/southbridge/amd/cimx/sb800/late.c<br>
>> > @@ -29,6 +29,7 @@<br>
>> > #include "SBPLATFORM.h" /* Platfrom Specific Definitions */<br>
>> > #include "cfg.h" /* sb800 Cimx configuration */<br>
>> > #include "chip.h" /* struct<br>
>> southbridge_amd_cimx_sb800_config */<br>
>> > +#include "smbus.h"<br>
>> > #include "sb_cimx.h" /* AMD CIMX wrapper entries */<br>
>> ><br>
>> ><br>
>> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = {<br>
>> > .set_resources = pci_dev_set_resources,<br>
>> > .enable_resources = pci_bus_enable_resources,<br>
>> > .init = pci_init,<br>
>> > + .enable = 0,<br>
>> > .scan_bus = pci_scan_bridge,<br>
>> > .reset_bus = pci_bus_reset,<br>
>> > .ops_pci = &lops_pci,<br>
>> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = {<br>
>> > .reset_bus = pci_bus_reset,<br>
>> > .ops_pci = &lops_pci,<br>
>> > };<br>
>> > -<br>
>> > +#if 0<br>
>> > /* 0:15:0 PCIe PortA */<br>
>> > static const struct pci_driver PORTA_driver __pci_driver = {<br>
>> > .ops = &bridge_ops,<br>
>> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver<br>
>> > __pci_driver = {<br>
>> > .vendor = PCI_VENDOR_ID_ATI,<br>
>> > .device = PCI_DEVICE_ID_ATI_SB800_PCIED,<br>
>> > };<br>
>> > -<br>
>> > +#endif<br>
>> ><br>
>> > /**<br>
>> > * South Bridge CIMx ramstage entry point wrapper.<br>
>> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)<br>
>> > switch (dev->path.pci.devfn) {<br>
>> > case (0x11 << 3) | 0: /* 0:11.0 SATA */<br>
>> > /* the first sb800 device */<br>
>> > + abcfg_reg(0xc0, 0x1FF, 0x0F4);<br>
>> > sb800_cimx_config(sb_config);<br>
>> ><br>
>> > if (dev->enabled) {<br>
>> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)<br>
>> > sb_config->GppLinkConfig =<br>
>> sb_chip->gpp_configuration;<br>
>> > }<br>
>> > break;<br>
>> > + case (0x15 << 3) | 1:<br>
>> > + case (0x15 << 3) | 2:<br>
>> > + case (0x15 << 3) | 3:<br>
>> > + //abcfg_reg(0xc0, 0xF0, 0x00);<br>
>> > + break;<br>
>> ><br>
>> > case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */<br>
>> > sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;<br>
>> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)<br>
>> > /* call the CIMX entry at the last sb800 device,<br>
>> > * so make sure the mainboard devicetree is complete<br>
>> > */<br>
>> > + abcfg_reg(0xc0, 0x100, 0x100);<br>
>> > #if CONFIG_HAVE_ACPI_RESUME<br>
>> > if (acpi_slp_type != 3)<br>
>> > sb_Before_Pci_Init();<br>
>> ><br>
>> ><br>
>> ><br>
>> ><br>
>> > From: <a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a><br>
>> > [mailto:<a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a>] On Behalf Of Andy Sharp<br>
>> > Sent: Friday, June 08, 2012 8:57 AM<br>
>> > To: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
>> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon<br>
>> ><br>
>> > Hi Steve,<br>
>> ><br>
>> > Makes no [substantive] difference. All that does is cause 4 extra<br>
>> > lines to be added to the console output:<br>
>> ><br>
>> > .<br>
>> > .<br>
>> > .<br>
>> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling<br>
>> > it.<br>
>> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling<br>
>> > it.<br>
>> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling<br>
>> > it.<br>
>> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling<br>
>> > it.<br>
>> > .<br>
>> > .<br>
>> > .<br>
>> ><br>
>> ><br>
>> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich<br>
>> > <<a href="mailto:steve.goodrich@se-eng.com">steve.goodrich@se-eng.com</a>> wrote:<br>
>> > ARG.. Thanks, Outlook. :P<br>
>> ><br>
>> > Andy,<br>
>> ><br>
>> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon<br>
>> > folder. Mine shows:<br>
>> ><br>
>> > device pci 15.0 off end # PCIe PortA<br>
>> > device pci 15.1 off end # PCIe PortB<br>
>> > device pci 15.2 off end # PCIe PortC<br>
>> > device pci 15.3 off end # PCIe PortD<br>
>> ><br>
>> > I'm not 100% certain, but I suspect that changing these from "off" to<br>
>> > "on" will enable the devices. Try the change and see if the console<br>
>> > output starts reflecting the devices you're looking for.<br>
>> ><br>
>> > -- Steve G.<br>
>> ><br>
>> ><br>
>> ><br>
>> > From: <a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a><br>
>> > [mailto:<a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@coreboot.org</a>] On Behalf Of Andy Sharp<br>
>> > Sent: Thursday, June 07, 2012 2:31 PM<br>
>> > To: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
>> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon<br>
>> ><br>
>> > Howdy,<br>
>> ><br>
>> > I've got an AMD/persimmon board, with the agesa family 14 northbridge<br>
>> > on the CPU, and the SB800 southbridge. Both have 4 PCIe ports on<br>
>> > them, but coreboot isn't enabling or enumerating any of the PCIe<br>
>> > devices on the SB800. Does anyone have any ideas for me? The two<br>
>> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.<br>
>> ><br>
>> ><br>
>> > Pasting the console output below for those interested:<br>
>> ><br>
>> ><br>
>> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012<br>
>> > starting...<br>
>> > POST: 0x34<br>
>> > BSP Family_Model: 00500f20<br>
>> > cpu_init_detectedx = 00000000<br>
>> > POST: 0x35<br>
>> > agesawrapper_amdinitmmio passed.<br>
>> > POST: 0x37<br>
>> > agesawrapper_amdinitreset passed.<br>
>> > POST: 0x39<br>
>> > agesawrapper_amdinitearly POST: 0x34<br>
>> > BSP Family_Model: 00500f20<br>
>> > cpu_init_detectedx = 00000001<br>
>> > POST: 0x35<br>
>> > agesawrapper_amdinitmmio passed.<br>
>> > POST: 0x37<br>
>> > agesawrapper_amdinitreset passed.<br>
>> > POST: 0x39<br>
>> > agesawrapper_amdinitearly passed.<br>
>> > SLP_TYP type was 0<br>
>> > POST: 0x40<br>
>> > agesawrapper_amdinitpost<br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> ><br>
>> > EventLog: EventClass = 2, EventInfo = 8040100.<br>
>> > Param1 = a00a, Param2 = 0.<br>
>> > Param3 = 0, Param4 = 0.<br>
>> > SLP_TYP type was 0<br>
>> > error level: 4<br>
>> > POST: 0x42<br>
>> > agesawrapper_amdinitenv SLP_TYP type was 0<br>
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000<br>
>> > SLP_TYP type was 0<br>
>> > SLP_TYP type was 0<br>
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000<br>
>> > SLP_TYP type was 0<br>
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000<br>
>> > SLP_TYP type was 0<br>
>> > SLP_TYP type was 0<br>
>> > SLP_TYP type was 0<br>
>> > passed.<br>
>> > POST: 0x43<br>
>> > POST: 0x44<br>
>> > POST: 0x50<br>
>> > Loading image.<br>
>> > CBFS: Looking for 'fallback/coreboot_ram'<br>
>> > CBFS: found.<br>
>> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),<br>
>> > entry @ 0x200000<br>
>> > Jumping to image.<br>
>> > POST: 0x80<br>
>> > POST: 0x39<br>
>> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012<br>
>> > booting...<br>
>> > POST: 0x40<br>
>> > Enumerating buses...<br>
>> > Show all devs...Before device enumeration.<br>
>> > Root Device: enabled 1<br>
>> > APIC_CLUSTER: 0: enabled 1<br>
>> > APIC: 00: enabled 1<br>
>> > PCI_DOMAIN: 0000: enabled 1<br>
>> > PCI: 00:00.0: enabled 1<br>
>> > PCI: 00:01.0: enabled 1<br>
>> > PCI: 00:01.1: enabled 1<br>
>> > PCI: 00:04.0: enabled 1<br>
>> > PCI: 00:05.0: enabled 0<br>
>> > PCI: 00:06.0: enabled 0<br>
>> > PCI: 00:07.0: enabled 0<br>
>> > PCI: 00:08.0: enabled 0<br>
>> > PCI: 00:11.0: enabled 1<br>
>> > PCI: 00:12.0: enabled 1<br>
>> > PCI: 00:12.1: enabled 1<br>
>> > PCI: 00:12.2: enabled 1<br>
>> > PCI: 00:13.0: enabled 1<br>
>> > PCI: 00:13.1: enabled 1<br>
>> > PCI: 00:13.2: enabled 1<br>
>> > PCI: 00:14.0: enabled 1<br>
>> > I2C: 00:50: enabled 1<br>
>> > I2C: 00:51: enabled 1<br>
>> > PCI: 00:14.1: enabled 1<br>
>> > PCI: 00:14.2: enabled 1<br>
>> > PCI: 00:14.3: enabled 1<br>
>> > PNP: 004e.0: enabled 0<br>
>> > PNP: 004e.3: enabled 0<br>
>> > PNP: 004e.4: enabled 0<br>
>> > PNP: 004e.5: enabled 1<br>
>> > PNP: 004e.6: enabled 0<br>
>> > PNP: 004e.a: enabled 0<br>
>> > PNP: 004e.10: enabled 1<br>
>> > PNP: 004e.11: enabled 0<br>
>> > PCI: 00:14.4: enabled 1<br>
>> > PCI: 00:14.5: enabled 1<br>
>> > PCI: 00:15.0: enabled 0<br>
>> > PCI: 00:15.1: enabled 0<br>
>> > PCI: 00:15.2: enabled 0<br>
>> > PCI: 00:15.3: enabled 0<br>
>> > PCI: 00:16.0: enabled 0<br>
>> > PCI: 00:16.2: enabled 0<br>
>> > PCI: 00:18.0: enabled 1<br>
>> > PCI: 00:18.1: enabled 1<br>
>> > PCI: 00:18.2: enabled 1<br>
>> > PCI: 00:18.3: enabled 1<br>
>> > PCI: 00:18.4: enabled 1<br>
>> > PCI: 00:18.5: enabled 1<br>
>> > PCI: 00:18.6: enabled 1<br>
>> > PCI: 00:18.7: enabled 1<br>
>> > Compare with tree...<br>
>> > Root Device: enabled 1<br>
>> > APIC_CLUSTER: 0: enabled 1<br>
>> > APIC: 00: enabled 1<br>
>> > PCI_DOMAIN: 0000: enabled 1<br>
>> > PCI: 00:00.0: enabled 1<br>
>> > PCI: 00:01.0: enabled 1<br>
>> > PCI: 00:01.1: enabled 1<br>
>> > PCI: 00:04.0: enabled 1<br>
>> > PCI: 00:05.0: enabled 0<br>
>> > PCI: 00:06.0: enabled 0<br>
>> > PCI: 00:07.0: enabled 0<br>
>> > PCI: 00:08.0: enabled 0<br>
>> > PCI: 00:11.0: enabled 1<br>
>> > PCI: 00:12.0: enabled 1<br>
>> > PCI: 00:12.1: enabled 1<br>
>> > PCI: 00:12.2: enabled 1<br>
>> > PCI: 00:13.0: enabled 1<br>
>> > PCI: 00:13.1: enabled 1<br>
>> > PCI: 00:13.2: enabled 1<br>
>> > PCI: 00:14.0: enabled 1<br>
>> > I2C: 00:50: enabled 1<br>
>> > I2C: 00:51: enabled 1<br>
>> > PCI: 00:14.1: enabled 1<br>
>> > PCI: 00:14.2: enabled 1<br>
>> > PCI: 00:14.3: enabled 1<br>
>> > PNP: 004e.0: enabled 0<br>
>> > PNP: 004e.3: enabled 0<br>
>> > PNP: 004e.4: enabled 0<br>
>> > PNP: 004e.5: enabled 1<br>
>> > PNP: 004e.6: enabled 0<br>
>> > PNP: 004e.a: enabled 0<br>
>> > PNP: 004e.10: enabled 1<br>
>> > PNP: 004e.11: enabled 0<br>
>> > PCI: 00:14.4: enabled 1<br>
>> > PCI: 00:14.5: enabled 1<br>
>> > PCI: 00:15.0: enabled 0<br>
>> > PCI: 00:15.1: enabled 0<br>
>> > PCI: 00:15.2: enabled 0<br>
>> > PCI: 00:15.3: enabled 0<br>
>> > PCI: 00:16.0: enabled 0<br>
>> > PCI: 00:16.2: enabled 0<br>
>> > PCI: 00:18.0: enabled 1<br>
>> > PCI: 00:18.1: enabled 1<br>
>> > PCI: 00:18.2: enabled 1<br>
>> > PCI: 00:18.3: enabled 1<br>
>> > PCI: 00:18.4: enabled 1<br>
>> > PCI: 00:18.5: enabled 1<br>
>> > PCI: 00:18.6: enabled 1<br>
>> > PCI: 00:18.7: enabled 1<br>
>> > Mainboard Persimmon Enable.<br>
>> > SLP_TYP type was 0<br>
>> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000<br>
>> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =<br>
>> > 0x00000000<br>
>> > persimmon_enable: uma size 0x18000000, memory start 0x67000000<br>
>> > scan_static_bus for Root Device<br>
>> > APIC_CLUSTER: 0 enabled<br>
>> > PCI_DOMAIN: 0000 enabled<br>
>> > APIC_CLUSTER: 0 scanning...<br>
>> > AP siblings=1<br>
>> > CPU: APIC: 00 enabled<br>
>> > CPU: APIC: 01 enabled<br>
>> > PCI_DOMAIN: 0000 scanning...<br>
>> > PCI: pci_scan_bus for bus 00<br>
>> > POST: 0x24<br>
>> > PCI: 00:00.0 [1022/1510] ops<br>
>> > PCI: 00:00.0 [1022/1510] enabled<br>
>> > PCI: 00:01.0 [1002/9804] enabled<br>
>> > Capability: type 0x01 @ 0x50<br>
>> > Capability: type 0x10 @ 0x58<br>
>> > Capability: type 0x05 @ 0xa0<br>
>> > Capability: type 0x0d @ 0xb0<br>
>> > Capability: type 0x08 @ 0xb8<br>
>> > Capability: type 0x01 @ 0x50<br>
>> > Capability: type 0x10 @ 0x58<br>
>> > PCI: 00:04.0 subordinate bus PCI Express<br>
>> > PCI: 00:04.0 [1022/1512] enabled<br>
>> > sb800_enable() SLP_TYP type was 0<br>
>> > PCI: 00:11.0 [1002/4393] ops<br>
>> > PCI: 00:11.0 [1002/4393] enabled<br>
>> > sb800_enable() PCI: 00:12.0 [1002/4397] ops<br>
>> > PCI: 00:12.0 [1002/4397] enabled<br>
>> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling<br>
>> > it.<br>
>> > sb800_enable() PCI: 00:12.2 [1002/4396] ops<br>
>> > PCI: 00:12.2 [1002/4396] enabled<br>
>> > sb800_enable() PCI: 00:13.0 [1002/4397] ops<br>
>> > PCI: 00:13.0 [1002/4397] enabled<br>
>> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling<br>
>> > it.<br>
>> > sb800_enable() PCI: 00:13.2 [1002/4396] ops<br>
>> > PCI: 00:13.2 [1002/4396] enabled<br>
>> > sb800_enable() sm_init().<br>
>> > IOAPIC: Clearing IOAPIC at 0xfec00000<br>
>> > IOAPIC: 23 interrupts<br>
>> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000<br>
>> > IOAPIC: Initializing IOAPIC at 0xfec00000<br>
>> > IOAPIC: Bootstrap Processor Local APIC = 0x00<br>
>> > IOAPIC: ID = 0x02<br>
>> > IOAPIC: 23 interrupts<br>
>> > IOAPIC: Enabling interrupts on FSB<br>
>> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700<br>
>> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000<br>
>> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000<br>
>> > PCI: 00:14.0 [1002/4385] enabled<br>
>> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling<br>
>> > it.<br>
>> > sb800_enable() hda enabled<br>
>> > PCI: 00:14.2 [1002/4383] ops<br>
>> > PCI: 00:14.2 [1002/4383] enabled<br>
>> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops<br>
>> > PCI: 00:14.3 [1002/439d] enabled<br>
>> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops<br>
>> > PCI: 00:14.4 [1002/4384] enabled<br>
>> > sb800_enable() PCI: 00:14.5 [1002/4399] ops<br>
>> > PCI: 00:14.5 [1002/4399] enabled<br>
>> > sb800_enable() sb800_enable() sb800_enable() sb800_enable()<br>
>> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled<br>
>> > PCI: 00:18.1 [1022/1701] enabled<br>
>> > PCI: 00:18.2 [1022/1702] enabled<br>
>> > PCI: 00:18.3 [1022/1703] enabled<br>
>> > PCI: 00:18.4 [1022/1704] enabled<br>
>> > PCI: 00:18.5 [1022/1718] enabled<br>
>> > PCI: 00:18.6 [1022/1716] enabled<br>
>> > PCI: 00:18.7 [1022/1719] enabled<br>
>> > POST: 0x25<br>
>> > PCI: Left over static devices:<br>
>> > PCI: 00:01.1<br>
>> > PCI: Check your devicetree.cb.<br>
>> > do_pci_scan_bridge for PCI: 00:04.0<br>
>> > PCI: pci_scan_bus for bus 01<br>
>> > POST: 0x24<br>
>> > PCI: 01:00.0 [10ec/8168] enabled<br>
>> > POST: 0x25<br>
>> > PCI: pci_scan_bus returning with max=001<br>
>> > POST: 0x55<br>
>> ><br>
>> > --<br>
>> > coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
>> > <a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">
http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
>> ><br>
>> ><br>
>> > --<br>
>> > coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
>> > <a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">
http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
>><br>
><o:p></o:p></p>
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