

coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000000 
agesawrapper_amdinitreset passed
cimx/rd890 early.c nb_Poweron_Init() Start
NbPowerOnResetInit entry
[NB]NbInitializer Enter
[NB]NbMiscInitializer Enter
[NB]NbMiscInitializer Exit
[NBHT]HtLibInitializer Enter
[NBHT]HtLibInitializer Exit
[NBPCIE]PcieLibInitializer Enter
[NBPCIE]PcieLibInitializer Exit
[NB]NbInitializer Exit
[NBPOR]NbPowerOnResetInit Enter
[NBPOR]NbPowerOnResetInit Exit
cimx/rd890 early.c nb_Poweron_Init() End. return status=0
cimx/sb700 early.c, sb_Poweron_Init() Start:
SB700 - Cfg.c - sb700_cimx_config - Start.
SB700 - Cfg.c - sb700_cimx_config - End.
CIMx - Entering sbPowerOnInit 
PFA=A000D2  AND=0, OR=1
PFA=A00040  AND=0, OR=44
PFA=A00041  AND=FF, OR=E9
PFA=A00064  AND=0, OR=BF
PFA=A00065  AND=0, OR=78
PFA=A00066  AND=BF, OR=9E
PFA=A00067  AND=F, OR=2
PFA=A00069  AND=0, OR=90
PFA=A0006C  AND=0, OR=20
PFA=A00078  AND=0, OR=FF
PFA=A00004  AND=0, OR=7
PFA=A00005  AND=0, OR=4
PFA=A000E1  AND=0, OR=99
PFA=A000AC  AND=EF, OR=2
PFA=A00062  AND=FC, OR=24
PFA=A30000  AND=A3, OR=0
PFA=A30040  AND=0, OR=4
PFA=A30048  AND=0, OR=7
PFA=A3004A  AND=0, OR=20
PFA=A30078  AND=FE, OR=0
PFA=A3007C  AND=0, OR=5
PFA=A300BB  AND=FE, OR=E9
PFA=A40000  AND=A4, OR=0
PFA=A40040  AND=0, OR=26
PFA=A4004B  AND=FF, OR=D0
PFA=A4001C  AND=0, OR=11
PFA=A4001D  AND=0, OR=11
PFA=A40004  AND=0, OR=21
PFA=A40050  AND=2, OR=1
PMIO Reg = 67   AndMask = FF  OrMask = 2
PMIO Reg = 37   AndMask = FF  OrMask = 4
PMIO Reg = 50   AndMask = 0  OrMask = E0
PMIO Reg = 60   AndMask = FF  OrMask = 20
PMIO Reg = 65   AndMask = 6F  OrMask = 0
PMIO Reg = 55   AndMask = BF  OrMask = 7
PMIO Reg = 66   AndMask = FF  OrMask = 20
PMIO Reg = B2   AndMask = FF  OrMask = 80
PMIO Reg = E   AndMask = FF  OrMask = 8
PMIO Reg = D7   AndMask = F6  OrMask = 80
PMIO Reg = 7C   AndMask = FF  OrMask = 10
PMIO Reg = 75   AndMask = C0  OrMask = 5
PMIO Reg = 52   AndMask = C0  OrMask = 8
PMIO Reg = 8B   AndMask = 0  OrMask = 10
PMIO Reg = 69   AndMask = F9  OrMask = 2
PFA=A00043  AND=F7, OR=0
PFA=A00038  AND=7F, OR=0
PFA=A000AD  AND=DF, OR=0
PFA=A00043  AND=FF, OR=8
PMIO Reg = D7   AndMask = FF  OrMask = 21
PMIO Reg = BB   AndMask = 7F  OrMask = 60
PFA=A3008E  AND=FD, OR=0
cimx/sb700 early.c, sb_Poweron_Init() End
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
Adding Node 1.

 * SUCCESS Event: 10041000 Data: 0, 2, 1, 1

Adding Node 2.

 * SUCCESS Event: 10041000 Data: 0, 0, 2, 1

Adding Node 3.

 * SUCCESS Event: 10041000 Data: 2, 2, 3, 3

Adding Node 4.

 * SUCCESS Event: 10041000 Data: 0, 3, 4, 1

Adding Node 5.

 * SUCCESS Event: 10041000 Data: 4, 2, 5, 5

Adding Node 6.

 * SUCCESS Event: 10041000 Data: 0, 7, 6, 1

Adding Node 7.

 * SUCCESS Event: 10041000 Data: 6, 2, 7, 7

  Dispatch CPU features after HT discovery
System routed as MCM max I/O.
Topology: Socket 0, Die 0, is Node 0, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 0, Die 1, is Node 1, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Topology: Socket 1, Die 0, is Node 4, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 1, Die 1, is Node 5, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Topology: Socket 2, Die 0, is Node 2, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 2, Die 1, is Node 3, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Topology: Socket 3, Die 0, is Node 6, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 3, Die 1, is Node 7, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Link Frequency: Node 00: Link 02: is running at 3200MHz
Link Frequency: Node 01: Link 01: is running at 3200MHz
Link Frequency: Node 00: Link 00: is running at 3200MHz
Link Frequency: Node 02: Link 07: is running at 3200MHz
Link Frequency: Node 02: Link 02: is running at 3200MHz
Link Frequency: Node 03: Link 01: is running at 3200MHz
Link Frequency: Node 00: Link 03: is running at 3200MHz
Link Frequency: Node 04: Link 00: is running at 3200MHz
Link Frequency: Node 04: Link 02: is running at 3200MHz
Link Frequency: Node 05: Link 01: is running at 3200MHz
Link Frequency: Node 00: Link 07: is running at 3200MHz
Link Frequency: Node 06: Link 00: is running at 3200MHz
Link Frequency: Node 06: Link 02: is running at 3200MHz
Link Frequency: Node 07: Link 01: is running at 3200MHz
Link Frequency: Node 01: Link 00: is running at 3200MHz
Link Frequency: Node 05: Link 00: is running at 3200MHz
Link Frequency: Node 01: Link 03: is running at 3200MHz
Link Frequency: Node 03: Link 03: is running at 3200MHz
Link Frequency: Node 01: Link 04: is running at 3200MHz
Link Frequency: Node 07: Link 04: is running at 3200MHz
Link Frequency: Node 02: Link 00: is running at 3200MHz
Link Frequency: Node 04: Link 03: is running at 3200MHz
Link Frequency: Node 02: Link 03: is running at 3200MHz
Link Frequency: Node 06: Link 03: is running at 3200MHz
Link Frequency: Node 03: Link 00: is running at 3200MHz
Link Frequency: Node 07: Link 03: is running at 3200MHz
Link Frequency: Node 03: Link 04: is running at 3200MHz
Link Frequency: Node 05: Link 04: is running at 3200MHz
Link Frequency: Node 04: Link 07: is running at 3200MHz
Link Frequency: Node 06: Link 07: is running at 3200MHz
Link Frequency: Node 05: Link 03: is running at 3200MHz
Link Frequency: Node 07: Link 00: is running at 3200MHz
Link Frequency: Node 00: Link 01: is running at 2600MHz
Link Frequency: Node 00: Link 00: is running at 2600MHz
Link Frequency: Node 04: Link 01: is running at 2600MHz
Link Frequency: Node 04: Link 00: is running at 2600MHz
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 0 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 0 Sub-link 1 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 0 Module 0 Sub-link 5 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 0 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 0 core 0 APIC ID = 0x20
  Launch socket 0 core 1
  Waiting for socket 0 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000001 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 1 APIC ID = 0x21
  Socket 0 core 1 begin AP tasking engine
  Launch socket 0 core 2
  Waiting for socket 0 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000002 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 2 APIC ID = 0x22
  Socket 0 core 2 begin AP tasking engine
  Launch socket 0 core 3
  Waiting for socket 0 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000003 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 3 APIC ID = 0x23
  Socket 0 core 3 begin AP tasking engine
  Launch socket 0 core 4
  Waiting for socket 0 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000004 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 4 APIC ID = 0x24
  Socket 0 core 4 begin AP tasking engine
  Launch socket 0 core 5
  Waiting for socket 0 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000005 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 5 APIC ID = 0x25
  Socket 0 core 5 begin AP tasking engine
  Launch socket 0 core 6
  Waiting for socket 0 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000030 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 0 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 1 core 6 APIC ID = 0x26
  Socket 0 core 6 begin AP tasking engine
  Launch socket 0 core 7
  Waiting for socket 0 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000007 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 7 APIC ID = 0x27
  Socket 0 core 7 begin AP tasking engine
  Launch socket 0 core 8
  Waiting for socket 0 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000008 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 8 APIC ID = 0x28
  Socket 0 core 8 begin AP tasking engine
  Launch socket 0 core 9
  Waiting for socket 0 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000009 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 9 APIC ID = 0x29
  Socket 0 core 9 begin AP tasking engine
  Launch socket 0 core 10
  Waiting for socket 0 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000000a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 10 APIC ID = 0x2a
  Socket 0 core 10 begin AP tasking engine
  Launch socket 0 core 11
  Waiting for socket 0 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000000b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 11 APIC ID = 0x2b
  Socket 0 core 11 begin AP tasking engine
  Launch socket 2 core 0
  Waiting for socket 2 core 0


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000001 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 2 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 2 core 0 APIC ID = 0x40
  Socket 2 core 0 begin AP tasking engine
  Launch socket 2 core 1
  Waiting for socket 2 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000021 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 1 APIC ID = 0x41
  Socket 2 core 1 begin AP tasking engine
  Launch socket 2 core 2
  Waiting for socket 2 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000022 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 2 APIC ID = 0x42
  Socket 2 core 2 begin AP tasking engine
  Launch socket 2 core 3
  Waiting for socket 2 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000023 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 3 APIC ID = 0x43
  Socket 2 core 3 begin AP tasking engine
  Launch socket 2 core 4
  Waiting for socket 2 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000024 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 4 APIC ID = 0x44
  Socket 2 core 4 begin AP tasking engine
  Launch socket 2 core 5
  Waiting for socket 2 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000025 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 5 APIC ID = 0x45
  Socket 2 core 5 begin AP tasking engine
  Launch socket 2 core 6
  Waiting for socket 2 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000031 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 2 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 3 core 6 APIC ID = 0x46
  Socket 2 core 6 begin AP tasking engine
  Launch socket 2 core 7
  Waiting for socket 2 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000027 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 7 APIC ID = 0x47
  Socket 2 core 7 begin AP tasking engine
  Launch socket 2 core 8
  Waiting for socket 2 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000028 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 8 APIC ID = 0x48
  Socket 2 core 8 begin AP tasking engine
  Launch socket 2 core 9
  Waiting for socket 2 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000029 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 9 APIC ID = 0x49
  Socket 2 core 9 begin AP tasking engine
  Launch socket 2 core 10
  Waiting for socket 2 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000002a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 10 APIC ID = 0x4a
  Socket 2 core 10 begin AP tasking engine
  Launch socket 2 core 11
  Waiting for socket 2 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000002b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 11 APIC ID = 0x4b
  Socket 2 core 11 begin AP tasking engine
  Launch socket 1 core 0
  Waiting for socket 1 core 0


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000002 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 1 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 0 Sub-link 1 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 1 Module 0 Sub-link 5 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 1 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 4 core 0 APIC ID = 0x60
  Socket 1 core 0 begin AP tasking engine
  Launch socket 1 core 1
  Waiting for socket 1 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000041 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 1 APIC ID = 0x61
  Socket 1 core 1 begin AP tasking engine
  Launch socket 1 core 2
  Waiting for socket 1 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000042 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 2 APIC ID = 0x62
  Socket 1 core 2 begin AP tasking engine
  Launch socket 1 core 3
  Waiting for socket 1 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000043 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 3 APIC ID = 0x63
  Socket 1 core 3 begin AP tasking engine
  Launch socket 1 core 4
  Waiting for socket 1 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000044 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 4 APIC ID = 0x64
  Socket 1 core 4 begin AP tasking engine
  Launch socket 1 core 5
  Waiting for socket 1 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000045 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 5 APIC ID = 0x65
  Socket 1 core 5 begin AP tasking engine
  Launch socket 1 core 6
  Waiting for socket 1 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000032 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 1 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 5 core 6 APIC ID = 0x66
  Socket 1 core 6 begin AP tasking engine
  Launch socket 1 core 7
  Waiting for socket 1 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000047 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 7 APIC ID = 0x67
  Socket 1 core 7 begin AP tasking engine
  Launch socket 1 core 8
  Waiting for socket 1 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000048 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 8 APIC ID = 0x68
  Socket 1 core 8 begin AP tasking engine
  Launch socket 1 core 9
  Waiting for socket 1 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000049 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 9 APIC ID = 0x69
  Socket 1 core 9 begin AP tasking engine
  Launch socket 1 core 10
  Waiting for socket 1 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000004a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 10 APIC ID = 0x6a
  Socket 1 core 10 begin AP tasking engine
  Launch socket 1 core 11
  Waiting for socket 1 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000004b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 11 APIC ID = 0x6b
  Socket 1 core 11 begin AP tasking engine
  Launch socket 3 core 0
  Waiting for socket 3 core 0


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000003 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 3 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 6 core 0 APIC ID = 0x80
  Socket 3 core 0 begin AP tasking engine
  Launch socket 3 core 1
  Waiting for socket 3 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000061 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 1 APIC ID = 0x81
  Socket 3 core 1 begin AP tasking engine
  Launch socket 3 core 2
  Waiting for socket 3 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000062 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 2 APIC ID = 0x82
  Socket 3 core 2 begin AP tasking engine
  Launch socket 3 core 3
  Waiting for socket 3 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000063 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 3 APIC ID = 0x83
  Socket 3 core 3 begin AP tasking engine
  Launch socket 3 core 4
  Waiting for socket 3 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000064 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 4 APIC ID = 0x84
  Socket 3 core 4 begin AP tasking engine
  Launch socket 3 core 5
  Waiting for socket 3 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000065 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 5 APIC ID = 0x85
  Socket 3 core 5 begin AP tasking engine
  Launch socket 3 core 6
  Waiting for socket 3 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000033 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 3 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 7 core 6 APIC ID = 0x86
  Socket 3 core 6 begin AP tasking engine
  Launch socket 3 core 7
  Waiting for socket 3 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000067 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 7 APIC ID = 0x87
  Socket 3 core 7 begin AP tasking engine
  Launch socket 3 core 8
  Waiting for socket 3 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000068 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 8 APIC ID = 0x88
  Socket 3 core 8 begin AP tasking engine
  Launch socket 3 core 9
  Waiting for socket 3 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000069 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 9 APIC ID = 0x89
  Socket 3 core 9 begin AP tasking engine
  Launch socket 3 core 10
  Waiting for socket 3 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000006a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 10 APIC ID = 0x8a
  Socket 3 core 10 begin AP tasking engine
  Launch socket 3 core 11
  Waiting for socket 3 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000006b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 11 APIC ID = 0x8b
  Socket 3 core 11 begin AP tasking engine
  Dispatch CPU features before early power mgmt init
    Boost is enabled
  Perform PM init step 0

 * BOUNDS_CHK Event: 08040100 Data: a00c, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00c, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00c, 0, 0, 0

  Perform PM init step 1
  NB Pstat  es NdB i s P s aNbBtNBa l teePds
sP ts
datitasetasebs dl edisdi
sab
ablleed
d

  Perform PM init step 2
  Perform PM init step 3
  Perform PM init step 4
  Perform PM init step 5
  Perform PM init step 6
  Dispatch CPU features after early power mgmt init
    MT C1e is enabled
CoreLevelingAtEarly
  CoreLevelMode: 0
  Socket 0 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 0 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 1 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 1 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 2 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 2 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 3 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 3 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
    Boost is enabled
  Halting all APs
AmdCpuEarly: End

AmdInitEarly: End

BSP Frequency: 2400MHz
agesawrapper_amdinitearly passed
[NB]NbInitializer Enter
[NB]NbMiscInitializer Enter
[NB]NbMiscInitializer Exit
[NBHT]HtLibInitializer Enter
[NBHT]HtLibInitializer Exit
[NBPCIE]PcieLibInitializer Enter
[NBPCIE]PcieLibInitializer Exit
[NB]NbInitializer Exit
[NBHT]HtLibInitializer Enter
[NBHT]AmdHtInit Enter
[NBHT]NbHtInit Enter
[NBHT]HtLibEarlyInit Enter
    Node 0 Link 1 PciAddress c0000
    Ht speed Cpu e Nb 0
[NBHT]HtLibEarlyInit Exit [0x0]
[NBHT]NbHtInit Exit [0x0]
[NBHT]AmdHtInit Exit [0x0]
AmdHtInit status: 0
..WARM RESET...




coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000000 
agesawrapper_amdinitreset passed
cimx/rd890 early.c nb_Poweron_Init() Start
NbPowerOnResetInit entry
[NB]NbInitializer Enter
[NB]NbMiscInitializer Enter
[NB]NbMiscInitializer Exit
[NBHT]HtLibInitializer Enter
[NBHT]HtLibInitializer Exit
[NBPCIE]PcieLibInitializer Enter
[NBPCIE]PcieLibInitializer Exit
[NB]NbInitializer Exit
[NBPOR]NbPowerOnResetInit Enter
[NBPOR]NbPowerOnResetInit Exit
cimx/rd890 early.c nb_Poweron_Init() End. return status=0
cimx/sb700 early.c, sb_Poweron_Init() Start:
SB700 - Cfg.c - sb700_cimx_config - Start.
SB700 - Cfg.c - sb700_cimx_config - End.
CIMx - Entering sbPowerOnInit 
PFA=A000D2  AND=0, OR=1
PFA=A00040  AND=0, OR=44
PFA=A00041  AND=FF, OR=E9
PFA=A00064  AND=0, OR=BF
PFA=A00065  AND=0, OR=78
PFA=A00066  AND=BF, OR=9E
PFA=A00067  AND=F, OR=2
PFA=A00069  AND=0, OR=90
PFA=A0006C  AND=0, OR=20
PFA=A00078  AND=0, OR=FF
PFA=A00004  AND=0, OR=7
PFA=A00005  AND=0, OR=4
PFA=A000E1  AND=0, OR=99
PFA=A000AC  AND=EF, OR=2
PFA=A00062  AND=FC, OR=24
PFA=A30000  AND=A3, OR=0
PFA=A30040  AND=0, OR=4
PFA=A30048  AND=0, OR=7
PFA=A3004A  AND=0, OR=20
PFA=A30078  AND=FE, OR=0
PFA=A3007C  AND=0, OR=5
PFA=A300BB  AND=FE, OR=E9
PFA=A40000  AND=A4, OR=0
PFA=A40040  AND=0, OR=26
PFA=A4004B  AND=FF, OR=D0
PFA=A4001C  AND=0, OR=11
PFA=A4001D  AND=0, OR=11
PFA=A40004  AND=0, OR=21
PFA=A40050  AND=2, OR=1
PMIO Reg = 67   AndMask = FF  OrMask = 2
PMIO Reg = 37   AndMask = FF  OrMask = 4
PMIO Reg = 50   AndMask = 0  OrMask = E0
PMIO Reg = 60   AndMask = FF  OrMask = 20
PMIO Reg = 65   AndMask = 6F  OrMask = 0
PMIO Reg = 55   AndMask = BF  OrMask = 7
PMIO Reg = 66   AndMask = FF  OrMask = 20
PMIO Reg = B2   AndMask = FF  OrMask = 80
PMIO Reg = E   AndMask = FF  OrMask = 8
PMIO Reg = D7   AndMask = F6  OrMask = 80
PMIO Reg = 7C   AndMask = FF  OrMask = 10
PMIO Reg = 75   AndMask = C0  OrMask = 5
PMIO Reg = 52   AndMask = C0  OrMask = 8
PMIO Reg = 8B   AndMask = 0  OrMask = 10
PMIO Reg = 69   AndMask = F9  OrMask = 2
PFA=A00043  AND=F7, OR=0
PFA=A00038  AND=7F, OR=0
PFA=A000AD  AND=DF, OR=0
PFA=A00043  AND=FF, OR=8
PMIO Reg = D7   AndMask = FF  OrMask = 21
PMIO Reg = BB   AndMask = 7F  OrMask = 60
PFA=A3008E  AND=FD, OR=0
cimx/sb700 early.c, sb_Poweron_Init() End
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
Adding Node 1.

 * SUCCESS Event: 10041000 Data: 0, 2, 1, 1

Adding Node 2.

 * SUCCESS Event: 10041000 Data: 0, 0, 2, 1

Adding Node 3.

 * SUCCESS Event: 10041000 Data: 2, 2, 3, 3

Adding Node 4.

 * SUCCESS Event: 10041000 Data: 0, 3, 4, 1

Adding Node 5.

 * SUCCESS Event: 10041000 Data: 4, 2, 5, 5

Adding Node 6.

 * SUCCESS Event: 10041000 Data: 0, 7, 6, 1

Adding Node 7.

 * SUCCESS Event: 10041000 Data: 6, 2, 7, 7

  Dispatch CPU features after HT discovery
System routed as MCM max I/O.
Topology: Socket 0, Die 0, is Node 0, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 0, Die 1, is Node 1, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Topology: Socket 1, Die 0, is Node 4, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 1, Die 1, is Node 5, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Topology: Socket 2, Die 0, is Node 2, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 2, Die 1, is Node 3, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Topology: Socket 3, Die 0, is Node 6, with Cores 0 thru 5. Compute Unit status (0x7,0x7).
Topology: Socket 3, Die 1, is Node 7, with Cores 6 thru 11. Compute Unit status (0x7,0x7).
Link Frequency: Node 00: Link 02: is running at 3200MHz
Link Frequency: Node 01: Link 01: is running at 3200MHz
Link Frequency: Node 00: Link 00: is running at 3200MHz
Link Frequency: Node 02: Link 07: is running at 3200MHz
Link Frequency: Node 02: Link 02: is running at 3200MHz
Link Frequency: Node 03: Link 01: is running at 3200MHz
Link Frequency: Node 00: Link 03: is running at 3200MHz
Link Frequency: Node 04: Link 00: is running at 3200MHz
Link Frequency: Node 04: Link 02: is running at 3200MHz
Link Frequency: Node 05: Link 01: is running at 3200MHz
Link Frequency: Node 00: Link 07: is running at 3200MHz
Link Frequency: Node 06: Link 00: is running at 3200MHz
Link Frequency: Node 06: Link 02: is running at 3200MHz
Link Frequency: Node 07: Link 01: is running at 3200MHz
Link Frequency: Node 01: Link 00: is running at 3200MHz
Link Frequency: Node 05: Link 00: is running at 3200MHz
Link Frequency: Node 01: Link 03: is running at 3200MHz
Link Frequency: Node 03: Link 03: is running at 3200MHz
Link Frequency: Node 01: Link 04: is running at 3200MHz
Link Frequency: Node 07: Link 04: is running at 3200MHz
Link Frequency: Node 02: Link 00: is running at 3200MHz
Link Frequency: Node 04: Link 03: is running at 3200MHz
Link Frequency: Node 02: Link 03: is running at 3200MHz
Link Frequency: Node 06: Link 03: is running at 3200MHz
Link Frequency: Node 03: Link 00: is running at 3200MHz
Link Frequency: Node 07: Link 03: is running at 3200MHz
Link Frequency: Node 03: Link 04: is running at 3200MHz
Link Frequency: Node 05: Link 04: is running at 3200MHz
Link Frequency: Node 04: Link 07: is running at 3200MHz
Link Frequency: Node 06: Link 07: is running at 3200MHz
Link Frequency: Node 05: Link 03: is running at 3200MHz
Link Frequency: Node 07: Link 00: is running at 3200MHz
Link Frequency: Node 00: Link 01: is running at 2600MHz
Link Frequency: Node 00: Link 00: is running at 2600MHz
Link Frequency: Node 04: Link 01: is running at 2600MHz
Link Frequency: Node 04: Link 00: is running at 2600MHz
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 0 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 0 Sub-link 1 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 0 Module 0 Sub-link 5 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 0 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 0 core 0 APIC ID = 0x20
  Perform core init step 4
  Launch socket 0 core 1
  Waiting for socket 0 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000001 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 1 APIC ID = 0x21
  Perform core init step 4
  Socket 0 core 1 begin AP tasking engine
  Launch socket 0 core 2
  Waiting for socket 0 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000002 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 2 APIC ID = 0x22
  Perform core init step 4
  Socket 0 core 2 begin AP tasking engine
  Launch socket 0 core 3
  Waiting for socket 0 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000003 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 3 APIC ID = 0x23
  Perform core init step 4
  Socket 0 core 3 begin AP tasking engine
  Launch socket 0 core 4
  Waiting for socket 0 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000004 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 4 APIC ID = 0x24
  Perform core init step 4
  Socket 0 core 4 begin AP tasking engine
  Launch socket 0 core 5
  Waiting for socket 0 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000005 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 0 core 5 APIC ID = 0x25
  Perform core init step 4
  Socket 0 core 5 begin AP tasking engine
  Launch socket 0 core 6
  Waiting for socket 0 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000030 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 0 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 0 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 0 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 0 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 0 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 1 core 6 APIC ID = 0x26
  Perform core init step 4
  Socket 0 core 6 begin AP tasking engine
  Launch socket 0 core 7
  Waiting for socket 0 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000007 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 7 APIC ID = 0x27
  Perform core init step 4
  Socket 0 core 7 begin AP tasking engine
  Launch socket 0 core 8
  Waiting for socket 0 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000008 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 8 APIC ID = 0x28
  Perform core init step 4
  Socket 0 core 8 begin AP tasking engine
  Launch socket 0 core 9
  Waiting for socket 0 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000009 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 9 APIC ID = 0x29
  Perform core init step 4
  Socket 0 core 9 begin AP tasking engine
  Launch socket 0 core 10
  Waiting for socket 0 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000000a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 10 APIC ID = 0x2a
  Perform core init step 4
  Socket 0 core 10 begin AP tasking engine
  Launch socket 0 core 11
  Waiting for socket 0 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000000b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 1 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 1 core 11 APIC ID = 0x2b
  Perform core init step 4
  Socket 0 core 11 begin AP tasking engine
  Launch socket 2 core 0
  Waiting for socket 2 core 0


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000001 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 2 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 2 core 0 APIC ID = 0x40
  Perform core init step 4
  Socket 2 core 0 begin AP tasking engine
  Launch socket 2 core 1
  Waiting for socket 2 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000021 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 1 APIC ID = 0x41
  Perform core init step 4
  Socket 2 core 1 begin AP tasking engine
  Launch socket 2 core 2
  Waiting for socket 2 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000022 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 2 APIC ID = 0x42
  Perform core init step 4
  Socket 2 core 2 begin AP tasking engine
  Launch socket 2 core 3
  Waiting for socket 2 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000023 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 3 APIC ID = 0x43
  Perform core init step 4
  Socket 2 core 3 begin AP tasking engine
  Launch socket 2 core 4
  Waiting for socket 2 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000024 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 4 APIC ID = 0x44
  Perform core init step 4
  Socket 2 core 4 begin AP tasking engine
  Launch socket 2 core 5
  Waiting for socket 2 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000025 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 2 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 2 core 5 APIC ID = 0x45
  Perform core init step 4
  Socket 2 core 5 begin AP tasking engine
  Launch socket 2 core 6
  Waiting for socket 2 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000031 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 2 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 2 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 2 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 2 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 2 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 3 core 6 APIC ID = 0x46
  Perform core init step 4
  Socket 2 core 6 begin AP tasking engine
  Launch socket 2 core 7
  Waiting for socket 2 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000027 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 7 APIC ID = 0x47
  Perform core init step 4
  Socket 2 core 7 begin AP tasking engine
  Launch socket 2 core 8
  Waiting for socket 2 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000028 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 8 APIC ID = 0x48
  Perform core init step 4
  Socket 2 core 8 begin AP tasking engine
  Launch socket 2 core 9
  Waiting for socket 2 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000029 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 9 APIC ID = 0x49
  Perform core init step 4
  Socket 2 core 9 begin AP tasking engine
  Launch socket 2 core 10
  Waiting for socket 2 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000002a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 10 APIC ID = 0x4a
  Perform core init step 4
  Socket 2 core 10 begin AP tasking engine
  Launch socket 2 core 11
  Waiting for socket 2 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000002b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 3 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 3 core 11 APIC ID = 0x4b
  Perform core init step 4
  Socket 2 core 11 begin AP tasking engine
  Launch socket 1 core 0
  Waiting for socket 1 core 0


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000002 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 1 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 0 Sub-link 1 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 1 Module 0 Sub-link 5 :
  ----> running on HT3, DCV Level is  - 9 dB
Socket 1 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 4 core 0 APIC ID = 0x60
  Perform core init step 4
  Socket 1 core 0 begin AP tasking engine
  Launch socket 1 core 1
  Waiting for socket 1 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000041 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 1 APIC ID = 0x61
  Perform core init step 4
  Socket 1 core 1 begin AP tasking engine
  Launch socket 1 core 2
  Waiting for socket 1 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000042 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 2 APIC ID = 0x62
  Perform core init step 4
  Socket 1 core 2 begin AP tasking engine
  Launch socket 1 core 3
  Waiting for socket 1 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000043 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 3 APIC ID = 0x63
  Perform core init step 4
  Socket 1 core 3 begin AP tasking engine
  Launch socket 1 core 4
  Waiting for socket 1 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000044 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 4 APIC ID = 0x64
  Perform core init step 4
  Socket 1 core 4 begin AP tasking engine
  Launch socket 1 core 5
  Waiting for socket 1 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000045 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 4 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 4 core 5 APIC ID = 0x65
  Perform core init step 4
  Socket 1 core 5 begin AP tasking engine
  Launch socket 1 core 6
  Waiting for socket 1 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000032 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 1 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 1 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 1 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 1 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 1 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 5 core 6 APIC ID = 0x66
  Perform core init step 4
  Socket 1 core 6 begin AP tasking engine
  Launch socket 1 core 7
  Waiting for socket 1 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000047 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 7 APIC ID = 0x67
  Perform core init step 4
  Socket 1 core 7 begin AP tasking engine
  Launch socket 1 core 8
  Waiting for socket 1 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000048 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 8 APIC ID = 0x68
  Perform core init step 4
  Socket 1 core 8 begin AP tasking engine
  Launch socket 1 core 9
  Waiting for socket 1 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000049 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 9 APIC ID = 0x69
  Perform core init step 4
  Socket 1 core 9 begin AP tasking engine
  Launch socket 1 core 10
  Waiting for socket 1 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000004a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 10 APIC ID = 0x6a
  Perform core init step 4
  Socket 1 core 10 begin AP tasking engine
  Launch socket 1 core 11
  Waiting for socket 1 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000004b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 5 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 5 core 11 APIC ID = 0x6b
  Perform core init step 4
  Socket 1 core 11 begin AP tasking engine
  Launch socket 3 core 0
  Waiting for socket 3 core 0


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000003 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 3 Module 0 Sub-link 2 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 0 Sub-link 6 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 0 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 0 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 0 Sub-link 7 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 0 Sub-link 2 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 0 Sub-link 6 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 0 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 0 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 0 Sub-link 7 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 6 core 0 APIC ID = 0x80
  Perform core init step 4
  Socket 3 core 0 begin AP tasking engine
  Launch socket 3 core 1
  Waiting for socket 3 core 1


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000061 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 1 APIC ID = 0x81
  Perform core init step 4
  Socket 3 core 1 begin AP tasking engine
  Launch socket 3 core 2
  Waiting for socket 3 core 2


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000062 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 2 APIC ID = 0x82
  Perform core init step 4
  Socket 3 core 2 begin AP tasking engine
  Launch socket 3 core 3
  Waiting for socket 3 core 3


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000063 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 3 APIC ID = 0x83
  Perform core init step 4
  Socket 3 core 3 begin AP tasking engine
  Launch socket 3 core 4
  Waiting for socket 3 core 4


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000064 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 4 APIC ID = 0x84
  Perform core init step 4
  Socket 3 core 4 begin AP tasking engine
  Launch socket 3 core 5
  Waiting for socket 3 core 5


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000065 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 6 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 6 core 5 APIC ID = 0x85
  Perform core init step 4
  Socket 3 core 5 begin AP tasking engine
  Launch socket 3 core 6
  Waiting for socket 3 core 6


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000033 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
Socket 3 Module 1 Sub-link 1 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 1 Sub-link 5 :
  ----> running on HT3, Deemphasis Level is  0 dB
Socket 3 Module 1 Sub-link 0 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 1 Sub-link 3 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 1 Sub-link 4 :
  ----> running on HT3, Deemphasis Level is  - 11 dB postcursor with - 8 dB precursor
Socket 3 Module 1 Sub-link 1 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 1 Sub-link 5 :
  ----> running on HT3, DCV Level is  0 dB
Socket 3 Module 1 Sub-link 0 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 1 Sub-link 3 :
  ----> running on HT3, DCV Level is  - 11 dB
Socket 3 Module 1 Sub-link 4 :
  ----> running on HT3, DCV Level is  - 11 dB
  Perform core init step 2
  Perform core init step 3
  Node 7 core 6 APIC ID = 0x86
  Perform core init step 4
  Socket 3 core 6 begin AP tasking engine
  Launch socket 3 core 7
  Waiting for socket 3 core 7


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000067 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 7 APIC ID = 0x87
  Perform core init step 4
  Socket 3 core 7 begin AP tasking engine
  Launch socket 3 core 8
  Waiting for socket 3 core 8


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000068 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 8 APIC ID = 0x88
  Perform core init step 4
  Socket 3 core 8 begin AP tasking engine
  Launch socket 3 core 9
  Waiting for socket 3 core 9


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000069 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 9 APIC ID = 0x89
  Perform core init step 4
  Socket 3 core 9 begin AP tasking engine
  Launch socket 3 core 10
  Waiting for socket 3 core 10


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000006a 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 10 APIC ID = 0x8a
  Perform core init step 4
  Socket 3 core 10 begin AP tasking engine
  Launch socket 3 core 11
  Waiting for socket 3 core 11


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 0000006b 
agesawrapper_amdinitreset passed
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 7 has raw CPUID=600f12.
AmdHtInitialize: End
AmdCpuEarly: Start
  Perform core init step 0
  Perform core init step 1
  Perform core init step 2
  Perform core init step 3
  Node 7 core 11 APIC ID = 0x8b
  Perform core init step 4
  Socket 3 core 11 begin AP tasking engine
  Dispatch CPU features before early power mgmt init
    Boost is enabled
  Perform PM init step 0

 * BOUNDS_CHK Event: 08040100 Data: a00c, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00c, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: a00c, 0, 0, 0

  Perform PM init step 1
  NB     NP  sNNBBB t Pa stPPesstttasat aedttieesss s da ibddlsiiasseaadbb
lb
elldee
dd


  Perform PM init step 2
  Perform PM init step 3



 
*

    **B  O*U BBONBODOUUUNNSDD_NSCDSHS___CCKHH CKEHKvK   EEevvnEetve:ennntt ::0t 8: 0 00084800081404040001010 01D000 0 a DtDaaaD:tatata a:a:0 : a a0a0c00,00 c0c,c,0, ,  00 ,,00 ,,   000,,0  
,0
 0
0












  
 * ***   BB BOBOOOUUUNNNUDDNDSDSSS___CCC_HHCHKHKKK   EEE vvEveveeennntttn::t: :   0000888000844040400011100010000 0   DDDaaaDttattaaaa:::   :aa aa0000000ccc0,,c, ,   000,,,0  , 0 00,0,,,   000 


0













   
** * *   BBBOOBOUOUUUNNNDDDNSSDS_S___CCCHHHCKKHK K   EEEvvvEeevenennnttt:::t  :  00088800080404440001110001000000   DDD aaDatatttaaa:::a  : a aaa0000000cc0c,c,,,   000 ,,0, ,   000,,,0  , 0 000












  

* 
**   *BB  OOBBOUUUNNODDUNSNDSDS__CCS_H_CHCHKKK  H EKEv vEEevenenvntet:n:tt :  00:08 8000884040400014100011000 0 0 D0Da aDDtatataaa:t: a ::a a0a0 00a0c0c00,c, , c 00,0,,   ,00 ,00 ,,0  ,00 ,
0 
0










   *
*  *B*  BBO OOUBUNOUNDUNSNDDSS_D_CS_H_CCCHHKKK H EK v EEEvveeenvnten:nttt::   :00 80008840084400041000110001000  0D  aDDtaaDttaaat:aa ::a  :aa 00a000c00,cc0,,c  , 0 0,0, ,00 , 0 0,0, , 0 ,
0 0
0










 
 
 * ***  BB  OOBBUOOUUUNNNDDNSSDD_SS___CCCHHCKKHH KK   EEEEvvveevenentntn:tt:::  0 0 08080808040440401010101000000 0 D D aDDaaatttaat::aa :: a  aaa000000cc00,cc,,,   0 00,0, , , 0 0,0,0, ,  00 

00











 

   ***  *B  BOOBBUOOUUNNUDDNNSDDSSS___C_CHCHCHKHK K K E EvEvEvevenenentnt:t:t: : 0 0 0808080804040404010101010000 0 0 D DaDaDatatatata:a: : : a aaa000000cc00,cc,,,    00,0,0, , 0 0 0,0, , , 0 0
0
0












   ***   *  BBBBOOOUUUONNUNDNDDDSSS___SCC_CHCHHHKKK  K E EEEvvveeevnnentnttt:::   :0 008088800044400040101110000000  0 D DDDaaaatttaaat::a: :   aaa000a0000c0ccc,,,   ,00 0,0,,,   000 ,,0, ,   000


0











 


 * *   *B*O B BBOUOUNONDUUSNNDDDS_S_CSCH__KCCHHHK K EKEv  eEEvvvenentet:nn: tt0::   08800084800040404110001010 0000 0DD a atDDaaattta:a: a a::0  aaa0000c0c,00 cc,,, 0 0, , 000,,   0,0, 0 0,,
  000













   ***   * BB BOOBOUOUUUNNNDDDNSSDS_S___CCCHHKKHC KH  KEEv vEEevenenvntet::nt t: 0 0:08 800084804040001140001010000   DD0aa DttDaaata:ta:a:   a:a0 0aa000cc00,c0,, c 0,0  ,,0  ,00 ,00 ,, 0 ,,0 0

0 

0









 
 *

   *** BO  BOUBBNOOUUUNDNDSNS_DDCSS___CHCHKCK HHEKK   EvEveEenvvteennnt:t: t 0::8  00080804840001440001010010 00D00   DaDatDtaaa:ttaaa: : a:a0  0aa0000c0c,0, cc0,,   0,0, 0 0,,,  000, , 0,0
  
00







  Perform PM init step 4
  Perform PM init step 5
  Perform PM init step 6
  Transition all cores to POST P-state
  Dispatch CPU features after early power mgmt init
    MT C1e is enabled
CoreLevelingAtEarly
  CoreLevelMode: 0
  Socket 0 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 0 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 1 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 1 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 2 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 2 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 3 Module 0 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
  Socket 3 Module 1 MaxCoreCountOnNode 6 MinCoreCountOnNode 6 TotalEnabledCoresOnNode 6 EnabledComputeUnit 3 MinNumOfComputeUnit 3
    Boost is enabled
  Halting all APs
AmdCpuEarly: End

AmdInitEarly: End

BSP Frequency: 2400MHz
agesawrapper_amdinitearly passed
[NB]NbInitializer Enter
[NB]NbMiscInitializer Enter
[NB]NbMiscInitializer Exit
[NBHT]HtLibInitializer Enter
[NBHT]HtLibInitializer Exit
[NBPCIE]PcieLibInitializer Enter
[NBPCIE]PcieLibInitializer Exit
[NB]NbInitializer Exit
[NBHT]HtLibInitializer Enter
[NBHT]AmdHtInit Enter
[NBHT]NbHtInit Enter
[NBHT]HtLibEarlyInit Enter
    Node 0 Link 1 PciAddress c0000
    Ht speed Cpu e Nb e
    Enable HT LS2
[NBHT]HtLibEarlyInit Exit [0x0]
[NBHT]NbHtInit Exit [0x0]
[NBHT]AmdHtInit Exit [0x0]
AmdHtInit status: 0
AmdInitPost: Start

AmdMemAuto: Start
MEM PARAMS:
	BottomIo : 00e0
	MemHoleRemap : 1
	LimitBelow1TB : 1
	UserTimingMode : 0
	MemClockValue : 667
	BankIntlv : 0
	NodeIntlv : 0
	ChannelIntlv : 0
	EccFeature : 1
	PowerDown : 0
	OnLineSpare : 0
	Parity : 0
	BankSwizzle : 1
	MemClr : 1
	UmaMode : 2
	UmaSize : 0
	MemRestoreCtl : 0
	SaveMemContextCtl : 0
	ExternalVrefCtl : 0
	ForceTrainMode : 2

SPD Socket 0 Channel 0 Dimm 1: 00401392
SPD Socket 0 Channel 2 Dimm 1: 00401796
SPD Socket 1 Channel 0 Dimm 1: 00401b9a
SPD Socket 1 Channel 2 Dimm 1: 00401f9e
SPD Socket 2 Channel 0 Dimm 1: 004023a2
SPD Socket 2 Channel 2 Dimm 1: 004027a6
SPD Socket 3 Channel 0 Dimm 1: 00402baa
SPD Socket 3 Channel 2 Dimm 1: 00402fae

 * BOUNDS_CHK Event: 08040100 Data: 1247000, 0, 0, 0

MemFInitTableDrive [0] Start
MemFInitTableDrive End
MemFInitTableDrive [0] Start
MemFInitTableDrive End
MemFInitTableDrive [0] Start
MemFInitTableDrive End
MemFInitTableDrive [0] Start
MemFInitTableDrive End
MemFInitTableDrive [0] Start
MemFInitTableDrive End
MemFInitTableDrive [0] Start
MemFInitTableDrive End
MemFInitTableDrive [0] Start
MemFInitTableDrive End
MemFInitTableDrive [0] Start
MemFInitTableDrive End

Maximize Performance
Node0 DCT0 Channel0 Dimm1 VDD Byte: 0x00
Node1 DCT0 Channel0 Dimm1 VDD Byte: 0x00
Node2 DCT0 Channel0 Dimm1 VDD Byte: 0x00
Node3 DCT0 Channel0 Dimm1 VDD Byte: 0x00
Node4 DCT0 Channel0 Dimm1 VDD Byte: 0x00
Node5 DCT0 Channel0 Dimm1 VDD Byte: 0x00
Node6 DCT0 Channel0 Dimm1 VDD Byte: 0x00
Node7 DCT0 Channel0 Dimm1 VDD Byte: 0x00

Commonly supported VDDIO is: 1.5V, .

Check speed supported for each VDDIO for Node0 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Check speed supported for each VDDIO for Node1 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Check speed supported for each VDDIO for Node2 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Check speed supported for each VDDIO for Node3 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Check speed supported for each VDDIO for Node4 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Check speed supported for each VDDIO for Node5 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Check speed supported for each VDDIO for Node6 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Check speed supported for each VDDIO for Node7 DCT0: 1.5V -> 800MHz 

			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
MemFInitTableDrive [3] Start
MemFInitTableDrive End

Searching for VDDIO that can maximize frequency: 
Node0: 1.5V -> 667MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Node1: 1.5V -> 667MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Node2: 1.5V -> 533MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Node3: 1.5V -> 533MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Node4: 1.5V -> 667MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Node5: 1.5V -> 667MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Node6: 1.5V -> 667MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Node7: 1.5V -> 667MHz, 1.35V -> 0MHz, 1.25V -> 0MHz
Number of nodes that can run at maximize performance: 1.5V -> 8 Nodes 1.35V -> 0 Nodes 1.25V -> 0 Nodes.

Calling out to Platform BIOS on Socket 0 Module 0...

VDDIO = 1.5V

Calling out to Platform BIOS on Socket 0 Module 1...

VDDIO = 1.5V

Calling out to Platform BIOS on Socket 2 Module 0...

VDDIO = 1.5V

Calling out to Platform BIOS on Socket 2 Module 1...

VDDIO = 1.5V

Calling out to Platform BIOS on Socket 1 Module 0...

VDDIO = 1.5V

Calling out to Platform BIOS on Socket 1 Module 1...

VDDIO = 1.5V

Calling out to Platform BIOS on Socket 3 Module 0...

VDDIO = 1.5V

Calling out to Platform BIOS on Socket 3 Module 1...

VDDIO = 1.5V
	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1d 1b 1b 1b 1c 1c 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1b 1b 1b 1b 1b 1c 1b 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1c 1c 1c 1c 1c 1d 1c 
		Fence: 17

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042

 * BOUNDS_CHK Event: 08040100 Data: a014, 0, 0, 0

	Log last MR0
		Node: 0, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1c 1b 1b 1c 1c 1b 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1c 1c 1c 1c 1c 1c 1c 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1c 1c 1c 1c 1d 1c 1b 
		Fence: 16

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 1, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1d 1d 1c 1c 1d 1b 1c 
		Fence: 17

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1c 1c 1c 1b 1d 1c 1d 
		Fence: 17

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1c 1c 1c 1c 1c 1d 1c 
		Fence: 17

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 2, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1d 1d 1c 1d 1c 1b 1c 1d 
		Fence: 17

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1c 1b 1b 1b 1b 1b 1b 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1d 1c 1c 1c 1c 1b 1b 1c 
		Fence: 16

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 3, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1d 1c 1d 1b 1c 1c 1c 1c 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1c 1b 1c 1b 1b 1b 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1d 1d 1d 1d 1c 1c 1d 1d 
		Fence: 17

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 4, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1d 1c 1c 1d 1d 1d 1d 1c 1c 
		Fence: 17

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1c 1c 1d 1c 1c 1c 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1d 1c 1c 1d 1d 1d 1d 1d 
		Fence: 17

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 5, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1b 1d 1c 1c 1c 1d 1b 1d 
		Fence: 17

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1c 1c 1b 1d 1b 1b 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1b 1c 1d 1c 1c 1d 1c 1c 
		Fence: 17

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 6, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

	NB P0: 2000MHz
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1d 1c 1b 1c 1c 1c 1b 1c 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1b 1c 1c 1c 1c 1c 1c 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1c 1c 1d 1c 1c 1b 1c 
		Fence: 16

MemClkFreq: 333 MHz
	EnDramInit = 1 for both DCTs
			CS2 RC00 0002
			CS2 RC01 000c
			CS2 RC02 0004
			CS2 RC03 0005
			CS2 RC04 0005
			CS2 RC05 0005
			CS2 RC08 0000
			CS2 RC09 000d
			CS2 RC10 0000
			CS2 RC11 0000
			CS2 RC12 0000
			CS2 RC13 0000
			CS2 RC14 0000
			CS2 RC15 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 7, Dct: 0, CS: 2, MR0: 00001328
			CS2 MR0 01328
End Dram Init

TOP_MEM:  0000e0000000
TOP_MEM2: 000420000000
Sub1THoleBase: 000420000000
MemFInitTableDrive [4] Start
MemFInitTableDrive End
MemFInitTableDrive [4] Start
MemFInitTableDrive End
MemFInitTableDrive [4] Start
MemFInitTableDrive End
MemFInitTableDrive [4] Start
MemFInitTableDrive End
MemFInitTableDrive [4] Start
MemFInitTableDrive End
MemFInitTableDrive [4] Start
MemFInitTableDrive End
MemFInitTableDrive [4] Start
MemFInitTableDrive End
MemFInitTableDrive [4] Start
MemFInitTableDrive End

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 4a 47 48 46 3e 41 42 45 3e    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 49 48 47 45 3f 40 43 43 3e    <<< Nibble 1			WrDqs: 4a 48 48 46 3f 41 43 44 3e    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 052 04e 046 041 040 044 04b 051 03e    <<< Nibble 0		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 054 04d 045 040 03f 044 04b 051 03f    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1a 1c 1c 1c 1c 1c 1b 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1a 1b 1b 1b 1a 1b 1b 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1c 1c 1b 1b 1c 1b 
		Fence: 16
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 0, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 52 50 50 4d 45 47 4a 4b 44 
			WrtLvTrEn = 1
			  PRE: 4a 48 48 45 3d 41 42 44 3c    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 52 50 50 4d 45 47 4a 4b 44 
			WrtLvTrEn = 1
			  PRE: 4a 48 47 45 3c 40 42 44 3b    <<< Nibble 1			WrDqs: 4a 48 48 45 3d 41 42 44 3c    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 023 01e 054 04e 04d 052 01a 020 04b    <<< Nibble 0		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 024 01e 055 04e 04d 053 01a 020 04c    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1a 1a 1a 1b 1b 1a 1a 1a 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 1a 1a 1b 1a 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 1a 1a 1a 1a 
		Fence: 14
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 0, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 57 55 55 51 46 4b 4d 4f 45 
			WrtLvTrEn = 1
			  PRE: 5c 58 58 53 48 4d 50 53 48    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 57 55 55 51 46 4b 4d 4f 45 
			WrtLvTrEn = 1
			  PRE: 5a 58 55 51 47 4c 4f 51 46    <<< Nibble 1			WrDqs: 5b 58 57 52 48 4d 50 52 47    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04c 045 038 030 02e 036 03f 049 02c    <<< Nibble 0		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04e 046 03a 030 02e 036 041 04a 02f    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 533 MHz -> 667 MHz
			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 19 1a 1a 19 
		Fence: 14

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 18 19 18 1a 18 19 18 1a 18 
		Fence: 13

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 1a 1a 1a 1a 
		Fence: 14
			CS2 RC10 0002
			CS2 MR2 00090
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 0, Dct: 0, CS: 2, MR0: 00001B58
			CS2 MR0 01b58
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 29 26 24 5e 52 58 5c 5e 50 
			WrtLvTrEn = 1
			  PRE: 28 26 23 5e 50 57 5b 5e 52    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 29 26 24 5e 52 58 5c 5e 50 
			WrtLvTrEn = 1
			  PRE: 27 25 23 5d 4f 56 5a 5d 51    <<< Nibble 1			WrDqs: 28 26 23 5e 50 57 5b 5e 52    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00090
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 033 02c 05c 052 04e 059 027 031 04e    <<< Nibble 0		TestAddr 200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 036 02b 05c 051 04f 059 027 034 050    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 03e
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 115 10c 0fc 0f2 0ef 0f9 107 113 0ef 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 125 11c 10c 102 0ff 109 117 123 0ff 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 03f
	TestAddr: 200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  P  .  P  .  P  P  . 
				ResultFound  :  Y  Y     Y     Y        Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 18 1c 18 1c 18 18 1c
				Result       :        .     .     .  .    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 19 1d 19 1d 19 19 1d
				Result       :  P  P  .  P  .  P  .  .  P 
				ResultFound  :  Y  Y     Y     Y        Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1a 1d 1a 1d 1a 1a 1d
				Result       :        .     .     .  .    
				ResultFound  :  Y  Y     Y     Y        Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1b 1d 1b 1d 1b 1b 1d
				Result       :        P     .     .  .    
				ResultFound  :  Y  Y  Y  Y     Y        Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1b 1d 1c 1d 1c 1c 1d
				Result       :              P     .  P    
				ResultFound  :  Y  Y  Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1b 1d 1c 1d 1d 1c 1d
				Result       :                    P       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 0f
				Result       :                          P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 10
				Result       :  P  .  .  .  P  P  .  .  P 
				ResultFound  :     Y  Y  Y        Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 14 15 15 14 14 11
				Result       :  P           .  P        P 
				ResultFound  :     Y  Y  Y  Y     Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 14 14 14 15 16 14 14 12
				Result       :  .              .        P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 14 14 14 15 16 14 14 13
				Result       :                          . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1d       12       15         08
		 1        1c       13       17         08
		 2        1d       13       16         08
		 3        1d       15       18         09
		 4        1c       14       18         08
		 5        1d       13       16         08
		 6        1b       13       18         07
		 7        1d       13       16         08
		 8        1d       15       18         09

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 042
	TestAddr: 200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 03e
	TestAddr: 200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  P  .  .  .  .  P  . 
				ResultFound  :  Y  Y     Y  Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 18 1c 1c 1c 1c 18 1c
				Result       :        .              .    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 19 1d 1d 1d 1d 19 1d
				Result       :  P  P  .  P  P  P  P  .  P 
				ResultFound  :  Y  Y     Y  Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1a 1d 1d 1d 1d 1a 1d
				Result       :        .              .    
				ResultFound  :  Y  Y     Y  Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1b 1d 1d 1d 1d 1b 1d
				Result       :        .              .    
				ResultFound  :  Y  Y     Y  Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1c 1d 1d 1d 1d 1c 1d
				Result       :        P              P    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 0f
				Result       :                          P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 10
				Result       :  P  .  .  .  P  P  .  .  P 
				ResultFound  :     Y  Y  Y        Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 14 15 15 14 14 11
				Result       :  P           .  .        P 
				ResultFound  :     Y  Y  Y  Y  Y  Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 14 14 14 15 15 14 14 12
				Result       :  .                       P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 14 14 14 15 15 14 14 13
				Result       :                          . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1d       12       15         08
		 1        1c       13       17         08
		 2        1d       13       16         08
		 3        1d       14       17         09
		 4        1d       14       17         09
		 5        1d       13       16         08
		 6        1c       13       17         08
		 7        1d       13       16         08
		 8        1d       15       18         09


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  .  .  .  .  P  P  P  . 
				ResultFound  :  Y              Y  Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 04 04 04 04 00 00 00 04
				Result       :     P  P  P  P           P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  P  .  .  .  .  .  .  .  . 
				ResultFound  :  Y                         

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 17 17 17 17 17 17 17 17
				Result       :     P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 18 18 18 18 18 18 18 18
				Result       :  .  P  P  P  P  P  P  P  P 
				ResultFound  :  Y                         

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 19 19 19 19 19 19 19 19
				Result       :     P  P  P  P  P  P  P  P 
				ResultFound  :  Y                         

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :     .  P  .  P  P  .  .  P 
				ResultFound  :  Y  Y     Y        Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1a 1b 1a 1b 1b 1a 1a 1b
				Result       :        .     .  .        . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        03       1a       17         0f
		 1        00       19       19         0d
		 2        00       19       19         0d
		 3        00       1a       1a         0d
		 4        04       1a       16         0f
		 5        04       19       15         0f
		 6        04       1a       16         0f
		 7        04       19       15         0f
		 8        00       1b       1b         0e
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 00200000
			Dly  2e
			Dly  2f
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36
			Dly  37  P		Final MaxRdLat: 03d
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 41 3f 3d 3c 3d 41 40 42 39    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 41 40 3d 3d 3f 40 40 43 3a    <<< Nibble 1			WrDqs: 41 40 3d 3d 3e 41 40 43 3a    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 047 041 03b 033 02c 030 039 03d 02e    <<< Nibble 0		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 048 042 03c 034 02d 032 039 03f 02e    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1b 1b 1b 1c 1b 1b 1b 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1b 1b 1a 1c 1b 1a 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1c 1b 1c 1c 1c 1b 
		Fence: 16
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 1, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 46 42 42 44 47 46 4a 3f 
			WrtLvTrEn = 1
			  PRE: 40 3f 3c 3b 3c 41 40 42 37    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 46 42 42 44 47 46 4a 3f 
			WrtLvTrEn = 1
			  PRE: 41 40 3d 3d 3f 41 41 43 39    <<< Nibble 1			WrDqs: 41 40 3d 3c 3e 41 41 43 38    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 055 04e 048 03e 034 03a 045 04a 037    <<< Nibble 0		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 055 04e 048 03e 035 03c 044 04a 036    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1b 1a 1a 1b 1a 1b 1b 1a 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 19 1a 1a 1a 19 1a 19 19 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1b 1b 1a 1a 1b 1a 1a 1a 
		Fence: 15
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 1, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4b 4a 46 45 47 4b 4b 4e 3f 
			WrtLvTrEn = 1
			  PRE: 4f 4c 49 47 47 4f 4e 51 42    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4b 4a 46 45 47 4b 4b 4e 3f 
			WrtLvTrEn = 1
			  PRE: 50 4e 49 49 4b 4f 4e 52 43    <<< Nibble 1			WrDqs: 50 4d 49 48 49 4f 4e 52 43    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03c 033 02c 05e 050 059 028 02f 055    <<< Nibble 0		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03d 034 02c 05f 053 05c 028 030 056    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 533 MHz -> 667 MHz
			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 1a 19 19 19 19 19 19 19 
		Fence: 14

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 19 1a 19 19 18 1a 19 19 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 1a 1a 1a 19 1a 1a 1a 1a 
		Fence: 14
			CS2 RC10 0002
			CS2 MR2 00090
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 1, Dct: 0, CS: 2, MR0: 00001B58
			CS2 MR0 01b58
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 5c 58 53 52 53 5a 59 5e 4b 
			WrtLvTrEn = 1
			  PRE: 59 56 50 4f 50 59 5a 5d 4c    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 5c 58 53 52 53 5a 59 5e 4b 
			WrtLvTrEn = 1
			  PRE: 59 57 50 51 53 58 59 5c 4c    <<< Nibble 1			WrDqs: 59 57 50 50 52 59 5a 5d 4c    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00090
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 023 056 04c 03b 02c 038 049 04f 032    <<< Nibble 0		TestAddr 80200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 01f 056 04a 03a 02d 037 045 050 031    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 03c
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 101 0f6 0eb 0db 0cd 0d8 0e7 0f0 0d2 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 111 106 0fb 0eb 0dd 0e8 0f7 100 0e2 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 03e
	TestAddr: 80200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  P  .  .  .  . 
				ResultFound  :              Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1d 1e 1e 1e 1e
				Result       :  P  P  P  P     .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1d 1f 1f 1f 1f
				Result       :                 P  .  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1d 1f 00 1f 1f
				Result       :                    P       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  .  P  .  .  P  P 
				ResultFound  :  Y  Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 0f 13 0f 0f 13 13
				Result       :           P     P  P       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 10 14 10 10 14 14
				Result       :  P  .  .  P  .  P  P  .  . 
				ResultFound  :     Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 11 14 11 11 14 14
				Result       :  .        P     P  P       
				ResultFound  :  Y  Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 12 14 12 12 14 14
				Result       :           P     P  .       
				ResultFound  :  Y  Y  Y     Y     Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 13 14 13 12 14 14
				Result       :           .     .          
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1f       13       14         09
		 1        1f       13       14         09
		 2        00       11       11         09
		 3        1f       12       13         09
		 4        1d       13       16         08
		 5        1e       12       14         08
		 6        1e       13       15         09
		 7        1e       13       15         09
		 8        1e       14       16         09

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 041
	TestAddr: 80200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 03e
	TestAddr: 80200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  P  P  P  P  P  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1f 1f 1f 1f
				Result       :                 P  .  .  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y        Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1f 00 00 1f
				Result       :                    P  P    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  .  P  .  .  P  P 
				ResultFound  :  Y  Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 0f 13 0f 0f 13 13
				Result       :           P     P  P       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 10 14 10 10 14 14
				Result       :  P  .  .  P  .  P  P  .  . 
				ResultFound  :     Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 11 14 11 11 14 14
				Result       :  .        P     P  P       
				ResultFound  :  Y  Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 12 14 12 12 14 14
				Result       :           P     P  .       
				ResultFound  :  Y  Y  Y     Y     Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 14 13 14 13 12 14 14
				Result       :           .     .          
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1f       13       14         09
		 1        00       13       13         0a
		 2        00       11       11         09
		 3        1f       12       13         09
		 4        1e       13       15         09
		 5        1e       12       14         08
		 6        1e       13       15         09
		 7        1e       13       15         09
		 8        1e       14       16         09


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  P  .  .  .  P  .  .  . 
				ResultFound  :     Y           Y          

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 00 04 04 04 00 04 04 04
				Result       :  P     P  P  P     P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  P  P  .  P  P  P  P  .  P 
				ResultFound  :        Y              Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 18 19 19 19 19 18 19
				Result       :  .  .     .  P  .  .     . 
				ResultFound  :  Y  Y  Y  Y     Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 18 19 1a 19 19 18 19
				Result       :              .             
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        03       18       15         0e
		 1        03       17       14         0d
		 2        03       18       15         0e
		 3        00       18       18         0c
		 4        04       19       15         0f
		 5        04       18       14         0e
		 6        04       17       13         0e
		 7        00       18       18         0c
		 8        04       18       14         0e
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 80200000
			Dly  2e
			Dly  2f
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36  P		Final MaxRdLat: 03c
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 49 47 46 44 3e 40 41 44 3d    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 49 47 46 44 3d 3f 41 43 3c    <<< Nibble 1			WrDqs: 49 47 46 44 3e 40 41 44 3d    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 120200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 053 04e 046 040 040 045 04c 051 03f    <<< Nibble 0		TestAddr 120200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 052 04d 046 040 040 045 04b 051 03f    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1b 1c 1c 1c 1c 1b 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1b 1c 1c 1b 1a 1c 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1b 1b 1b 1b 1b 1b 
		Fence: 15
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 2, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 51 4e 4d 4b 44 46 47 4b 42 
			WrtLvTrEn = 1
			  PRE: 4b 48 47 45 3c 40 41 44 3c    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 51 4e 4d 4b 44 46 47 4b 42 
			WrtLvTrEn = 1
			  PRE: 4a 48 47 44 3b 3f 41 44 3c    <<< Nibble 1			WrDqs: 4b 48 47 45 3c 40 41 44 3c    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 120200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 022 01d 053 04c 04c 051 01a 020 04a    <<< Nibble 0		TestAddr 120200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 023 01d 054 04d 04d 053 01a 020 04b    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1b 1b 1b 1a 1a 1a 1b 1a 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1b 1a 1b 1b 1a 1a 1a 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1a 1c 1a 1a 1a 1b 
		Fence: 15
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 2, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 59 55 53 51 45 4a 4b 4f 45 
			WrtLvTrEn = 1
			  PRE: 5c 57 56 52 48 4e 50 52 47    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 59 55 53 51 45 4a 4b 4f 45 
			WrtLvTrEn = 1
			  PRE: 5c 59 57 53 47 4c 50 52 48    <<< Nibble 1			WrDqs: 5c 58 57 53 48 4d 50 52 48    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 120200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04e 047 03c 031 02f 038 042 04c 02e    <<< Nibble 0		TestAddr 120200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04d 045 03a 031 02f 037 041 04b 02e    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 044
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 0ee 0e6 0db 0d1 0cf 0d8 0e2 0ec 0ce 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 0fe 0f6 0eb 0e1 0df 0e8 0f2 0fc 0de 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 044
	TestAddr: 120200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  P  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y     Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 18 1c 1c 1c
				Result       :                 .          
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 19 1d 1d 1d
				Result       :  P  .  .  P  .  .  P  P  . 
				ResultFound  :  Y        Y        Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1e 1e 1d 1e 1a 1d 1d 1e
				Result       :     .  P     P  .        P 
				ResultFound  :  Y     Y  Y  Y     Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1f 1e 1d 1e 1b 1d 1d 1e
				Result       :     P           .          
				ResultFound  :  Y  Y  Y  Y  Y     Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1f 1e 1d 1e 1c 1d 1d 1e
				Result       :                 P          
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  P  P  P  P  P  .  .  P  P 
				ResultFound  :                 Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 14 14 15 15
				Result       :  .  P  .  P  P        P  . 
				ResultFound  :  Y     Y        Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 16 15 16 16 14 14 16 15
				Result       :     .     .  .        .    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1e       14       16         09
		 1        1d       15       18         09
		 2        1d       13       16         08
		 3        1c       13       17         08
		 4        1e       15       17         0a
		 5        1d       15       18         09
		 6        1e       14       16         09
		 7        1f       15       16         0a
		 8        1d       14       17         09

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 049
	TestAddr: 120200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 044
	TestAddr: 120200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  P  .  .  P  .  P  P  P  . 
				ResultFound  :  Y        Y     Y  Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1e 1e 1d 1e 1d 1d 1d 1e
				Result       :     .  P     P           P 
				ResultFound  :  Y     Y  Y  Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1f 1e 1d 1e 1d 1d 1d 1e
				Result       :     P                      
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  P  P  P  P  P  .  .  P  P 
				ResultFound  :                 Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 14 14 15 15
				Result       :  P  P  P  P  P        P  P 
				ResultFound  :                 Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 14 14 16 16
				Result       :  .  .  .  .  .        .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1e       15       17         0a
		 1        1d       15       18         09
		 2        1d       13       16         08
		 3        1d       13       16         08
		 4        1e       15       17         0a
		 5        1d       15       18         09
		 6        1e       15       17         0a
		 7        1f       15       16         0a
		 8        1d       15       18         09


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  P  .  .  .  P  P  P  P  P 
				ResultFound  :     Y  Y  Y                

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 01 01 01 00 00 00 00 00
				Result       :  .           .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  P  P  P  .  .  P  .  .  P 
				ResultFound  :           Y  Y     Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1c 1c 1d 1c 1c 1d
				Result       :  .  .  .        .        . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        01       1c       1b         0f
		 1        01       1b       1a         0e
		 2        01       1b       1a         0e
		 3        01       1c       1b         0f
		 4        01       1b       1a         0e
		 5        02       1b       19         0f
		 6        02       1c       1a         0f
		 7        02       1c       1a         0f
		 8        01       1c       1b         0f
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 120200000
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36
			Dly  37
			Dly  38
			Dly  39
			Dly  3a  P		Final MaxRdLat: 041
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 42 3f 3d 3e 3d 40 3f 43 3a    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 40 40 3d 3e 3e 40 3f 43 3a    <<< Nibble 1			WrDqs: 41 40 3d 3e 3e 40 3f 43 3a    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 1a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 046 041 03c 033 02d 031 039 03d 02e    <<< Nibble 0		TestAddr 1a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 047 041 03c 035 02e 032 039 03e 02f    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1c 1b 1c 1b 1c 1c 1c 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1c 1b 1b 1b 1b 1b 1c 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1c 1b 1b 1b 1b 1b 
		Fence: 16
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 3, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 46 42 44 44 46 45 4a 3f 
			WrtLvTrEn = 1
			  PRE: 42 40 3d 3d 3e 41 40 44 39    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 46 42 44 44 46 45 4a 3f 
			WrtLvTrEn = 1
			  PRE: 41 40 3d 3c 3d 40 40 44 39    <<< Nibble 1			WrDqs: 42 40 3d 3d 3e 41 40 44 39    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 1a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 055 050 049 03e 036 03c 046 04c 038    <<< Nibble 0		TestAddr 1a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 055 04e 049 03e 035 03c 044 04a 038    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1a 1b 1a 1b 1a 1b 1b 1a 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 19 1a 1a 1a 19 1a 1a 1a 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1b 1b 1b 1b 1a 1b 
		Fence: 15
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 3, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4d 4a 46 46 47 4b 4a 4f 41 
			WrtLvTrEn = 1
			  PRE: 4f 4d 48 48 48 4d 4c 51 42    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4d 4a 46 46 47 4b 4a 4f 41 
			WrtLvTrEn = 1
			  PRE: 4f 4c 47 47 47 4c 4c 51 43    <<< Nibble 1			WrDqs: 4f 4d 48 48 48 4d 4c 51 43    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 1a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03c 035 02c 05e 052 05c 029 030 056    <<< Nibble 0		TestAddr 1a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03b 033 02c 060 052 05c 027 02f 056    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 042
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 0dc 0d4 0cc 0bf 0b2 0bc 0c8 0d0 0b6 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 0ec 0e4 0dc 0cf 0c2 0cc 0d8 0e0 0c6 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 044
	TestAddr: 1a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  P  .  .  .  .  .  . 
				ResultFound  :        Y                   

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1d 1e 1e 1e 1e 1e 1e
				Result       :  .  P     .  P  P  .  .  . 
				ResultFound  :     Y  Y     Y  Y          

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1e 1d 1f 1e 1e 1f 1f 1f
				Result       :  P        P        P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  P  .  .  .  P  .  .  P  P 
				ResultFound  :     Y  Y  Y     Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 15 15 15 16 15 15 16 16
				Result       :  .           .        P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 15 15 15 16 15 15 17 17
				Result       :                       .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1f       16       17         0b
		 1        1f       16       17         0b
		 2        1f       14       15         0a
		 3        1e       14       16         09
		 4        1e       15       17         0a
		 5        1f       14       15         0a
		 6        1d       14       17         09
		 7        1e       14       16         09
		 8        1f       15       16         0a

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 047
	TestAddr: 1a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 044
	TestAddr: 1a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  P  .  .  .  .  .  . 
				ResultFound  :        Y                   

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1d 1e 1e 1e 1e 1e 1e
				Result       :  P  P     .  P  P  .  .  . 
				ResultFound  :  Y  Y  Y     Y  Y          

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1d 1f 1e 1e 1f 1f 1f
				Result       :           .        P  P  P 
				ResultFound  :  Y  Y  Y     Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1d 00 1e 1e 1f 1f 1f
				Result       :           P                
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  P  .  P  P  P  P  P  P  P 
				ResultFound  :     Y                      

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 14 15 15 15 15 15 15 15
				Result       :  P     .  P  P  .  .  P  P 
				ResultFound  :     Y  Y        Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 14 15 16 16 15 15 16 16
				Result       :  .        .  .        P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 14 15 16 16 15 15 17 17
				Result       :                       P  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 14 15 16 16 15 15 18 17
				Result       :                       .    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1f       16       17         0b
		 1        1f       17       18         0b
		 2        1f       14       15         0a
		 3        1e       14       16         09
		 4        1e       15       17         0a
		 5        00       15       15         0b
		 6        1d       14       17         09
		 7        1e       13       15         09
		 8        1e       15       17         0a


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  P  P  .  P  .  .  .  P  P 
				ResultFound  :        Y     Y  Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 01 00 01 01 01 00 00
				Result       :  .  .     .           .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  P  .  .  .  .  .  .  . 
				ResultFound  :     Y                      

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 1b 17 17 17 17 17 17 17
				Result       :  P     P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 1c 18 18 18 18 18 18 18
				Result       :  P  .  P  P  P  P  P  P  P 
				ResultFound  :     Y                      

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 1c 19 19 19 19 19 19 19
				Result       :  P     P  P  P  P  P  .  P 
				ResultFound  :     Y                 Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1c 1a 1a 1a 1a 1a 19 1a
				Result       :  .     P  .  P  P  .     . 
				ResultFound  :  Y  Y     Y        Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1c 1b 1a 1b 1b 1a 19 1a
				Result       :        P     .  .          
				ResultFound  :  Y  Y     Y  Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1c 1c 1a 1b 1b 1a 19 1a
				Result       :        .                   
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        01       19       18         0d
		 1        01       18       17         0d
		 2        02       19       17         0e
		 3        02       1a       18         0e
		 4        02       1a       18         0e
		 5        01       19       18         0d
		 6        02       1b       19         0f
		 7        01       1b       1a         0e
		 8        01       19       18         0d
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 1a0200000
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36
			Dly  37
			Dly  38
			Dly  39
			Dly  3a  P		Final MaxRdLat: 041
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 48 45 44 43 3c 3f 40 41 3c    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 48 46 45 44 3d 3f 41 42 3c    <<< Nibble 1			WrDqs: 48 46 45 44 3d 3f 41 42 3c    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 052 04d 046 03f 03f 044 04a 050 03d    <<< Nibble 0		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 052 04d 045 03f 03f 044 049 04f 03e    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1c 1b 1c 1b 1c 1c 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1c 1b 1b 1b 1b 1a 1c 1b 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1c 1b 1c 1b 1c 1c 
		Fence: 16
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 4, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 50 4d 4c 4b 42 45 47 48 41 
			WrtLvTrEn = 1
			  PRE: 49 46 45 43 3c 40 41 43 3c    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 50 4d 4c 4b 42 45 47 48 41 
			WrtLvTrEn = 1
			  PRE: 48 46 45 43 3b 3f 3f 42 3b    <<< Nibble 1			WrDqs: 49 46 45 43 3c 40 40 43 3c    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 023 01d 054 04d 04c 053 05a 020 04a    <<< Nibble 0		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 023 01d 055 04d 04d 053 059 01f 04b    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1b 1b 1b 1b 19 1a 1b 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 19 1b 1a 1a 1a 1a 1a 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1b 1a 1b 1a 1a 1b 1a 1a 
		Fence: 15
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 4, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 56 52 51 4e 45 4a 4a 4e 45 
			WrtLvTrEn = 1
			  PRE: 5b 56 54 51 48 4d 4e 50 47    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 56 52 51 4e 45 4a 4a 4e 45 
			WrtLvTrEn = 1
			  PRE: 58 56 55 51 46 4c 4e 51 46    <<< Nibble 1			WrDqs: 5a 56 55 51 47 4d 4e 51 47    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04f 047 03c 032 030 038 042 04b 02e    <<< Nibble 0		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04d 045 039 030 02d 037 03f 049 02e    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 533 MHz -> 667 MHz
			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 19 19 1a 1a 
		Fence: 14

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 18 1a 18 1a 19 1a 19 19 1a 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 1a 19 1a 1a 
		Fence: 14
			CS2 RC10 0002
			CS2 MR2 00090
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 4, Dct: 0, CS: 2, MR0: 00001B58
			CS2 MR0 01b58
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 28 23 22 5d 50 58 59 5d 50 
			WrtLvTrEn = 1
			  PRE: 26 21 1f 5b 4e 55 58 5a 50    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 28 23 22 5d 50 58 59 5d 50 
			WrtLvTrEn = 1
			  PRE: 24 22 1f 5c 4e 54 58 5b 4f    <<< Nibble 1			WrDqs: 25 22 1f 5c 4e 55 58 5b 50    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00090
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 034 02b 01b 04f 04d 058 025 02f 04d    <<< Nibble 0		TestAddr 220200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 037 02e 01e 052 050 05b 027 032 052    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 03e
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 116 10d 0fd 0f1 0ef 0fa 106 111 0f0 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 126 11d 10d 101 0ff 10a 116 121 100 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 03f
	TestAddr: 220200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  P  .  P  .  .  P  .  P  P 
				ResultFound  :     Y     Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 1c 18 1c 1c 18 1c 18 18
				Result       :  .     .        .     .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 1d 19 1d 1d 19 1d 19 19
				Result       :  .  P  .  P  .  .  P  .  . 
				ResultFound  :     Y     Y        Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1d 1a 1d 1e 1a 1d 1a 1a
				Result       :  .     .     P  .     .  . 
				ResultFound  :     Y     Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1d 1b 1d 1e 1b 1d 1b 1b
				Result       :  .     .        .     .  . 
				ResultFound  :     Y     Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1d 1c 1d 1e 1c 1d 1c 1c
				Result       :  P     .        P     P  P 
				ResultFound  :  Y  Y     Y  Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1d 1d 1d 1e 1c 1d 1c 1c
				Result       :        P                   
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  P  P  P  P  P  P  P  P  . 
				ResultFound  :                          Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 14
				Result       :  .  .  .  P  P  P  P  .    
				ResultFound  :  Y  Y  Y              Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 16 16 16 16 15 14
				Result       :           .  .  .  .       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1c       13       17         08
		 1        1c       14       18         08
		 2        1d       15       18         09
		 3        1c       15       19         09
		 4        1e       15       17         0a
		 5        1d       15       18         09
		 6        1d       14       17         09
		 7        1d       14       17         09
		 8        1c       14       18         08

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 042
	TestAddr: 220200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 03e
	TestAddr: 220200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  P  .  P  .  .  P  .  P  P 
				ResultFound  :     Y     Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 1c 18 1c 1c 18 1c 18 18
				Result       :  .     .        .     .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 1d 19 1d 1d 19 1d 19 19
				Result       :  .  P  .  .  .  .  P  .  . 
				ResultFound  :     Y              Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1d 1a 1e 1e 1a 1d 1a 1a
				Result       :  .     .  P  P  .     .  . 
				ResultFound  :     Y     Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1d 1b 1e 1e 1b 1d 1b 1b
				Result       :  .     .        .     .  . 
				ResultFound  :     Y     Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1d 1c 1e 1e 1c 1d 1c 1c
				Result       :  P     .        P     P  P 
				ResultFound  :  Y  Y     Y  Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1d 1d 1e 1e 1c 1d 1c 1c
				Result       :        P                   
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  P  P  P  P  P  P  P  P  . 
				ResultFound  :                          Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 14
				Result       :  .  .  .  P  P  P  P  .    
				ResultFound  :  Y  Y  Y              Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 16 16 16 16 15 14
				Result       :           .  .  .  .       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1c       13       17         08
		 1        1c       14       18         08
		 2        1d       15       18         09
		 3        1c       15       19         09
		 4        1e       15       17         0a
		 5        1e       15       17         0a
		 6        1d       14       17         09
		 7        1d       14       17         09
		 8        1c       14       18         08


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  P  .  . 
				ResultFound  :                    Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 00 04 04
				Result       :  P  P  P  P  P  P     P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  P  .  .  .  .  .  .  .  . 
				ResultFound  :  Y                         

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 17 17 17 17 17 17 17 17
				Result       :     P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 18 18 18 18 18 18 18 18
				Result       :  .  P  P  P  P  P  P  P  P 
				ResultFound  :  Y                         

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 19 19 19 19 19 19 19 19
				Result       :     P  P  .  P  P  P  P  P 
				ResultFound  :  Y        Y                

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1a 1a 19 1a 1a 1a 1a 1a
				Result       :     .  P     .  .  .  P  P 
				ResultFound  :  Y  Y     Y  Y  Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1a 1b 19 1a 1a 1a 1b 1b
				Result       :        .              .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        03       1a       17         0f
		 1        03       1a       17         0f
		 2        00       19       19         0d
		 3        04       19       15         0f
		 4        04       19       15         0f
		 5        04       18       14         0e
		 6        04       1a       16         0f
		 7        04       19       15         0f
		 8        04       1b       17         10
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 220200000
			Dly  2e
			Dly  2f
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36
			Dly  37
			Dly  38
			Dly  39  P		Final MaxRdLat: 03f
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 41 3f 3d 3e 3e 40 3f 43 3b    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 41 3f 3b 3d 3d 3f 40 43 3a    <<< Nibble 1			WrDqs: 41 3f 3c 3e 3e 40 40 43 3b    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 047 042 03c 034 02d 031 039 03f 02f    <<< Nibble 0		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 047 041 03c 034 02d 031 039 03e 02f    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1b 1b 1b 1b 1c 1b 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1b 1b 1c 1c 1c 1c 1b 1b 
		Fence: 16

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1b 1b 1b 1b 1c 1b 
		Fence: 16
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 5, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 45 41 44 44 46 46 4a 40 
			WrtLvTrEn = 1
			  PRE: 41 3f 3c 3d 3d 40 40 43 39    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 45 41 44 44 46 46 4a 40 
			WrtLvTrEn = 1
			  PRE: 42 3f 3b 3c 3d 40 40 44 39    <<< Nibble 1			WrDqs: 42 3f 3c 3d 3d 40 40 44 39    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 056 04f 049 03f 035 03c 045 04c 039    <<< Nibble 0		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 057 050 04a 03f 036 03d 046 04c 039    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1b 1b 1b 1a 1b 1b 1b 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 19 1b 1b 1a 1b 1b 1b 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1a 1b 1b 1b 1b 1c 
		Fence: 15
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 5, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4d 49 45 46 46 4a 4a 4f 41 
			WrtLvTrEn = 1
			  PRE: 4f 4c 48 48 48 4d 4d 50 43    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4d 49 45 46 46 4a 4a 4f 41 
			WrtLvTrEn = 1
			  PRE: 4f 4c 46 47 48 4d 4d 52 42    <<< Nibble 1			WrDqs: 4f 4c 47 48 48 4d 4d 51 43    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03c 034 02c 05d 051 05b 027 030 056    <<< Nibble 0		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03d 035 02b 05e 052 05c 028 02f 056    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 533 MHz -> 667 MHz
			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 19 1a 19 19 1a 19 1a 
		Fence: 14

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 1a 19 1a 1a 1a 1a 1a 1a 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1b 19 1b 1a 1a 
		Fence: 15
			CS2 RC10 0002
			CS2 MR2 00090
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 5, Dct: 0, CS: 2, MR0: 00001B58
			CS2 MR0 01b58
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 5a 57 50 52 52 58 58 5d 4b 
			WrtLvTrEn = 1
			  PRE: 58 55 4f 50 50 55 58 5c 4c    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 5a 57 50 52 52 58 58 5d 4b 
			WrtLvTrEn = 1
			  PRE: 59 56 4d 4f 50 56 58 5e 4b    <<< Nibble 1			WrDqs: 59 56 4e 50 50 56 58 5d 4c    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00090
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 020 055 049 039 02c 037 045 04f 032    <<< Nibble 0		TestAddr 2a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 01d 054 049 039 02b 035 046 04d 031    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 03c
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 0ff 0f5 0e9 0d9 0cc 0d6 0e6 0ee 0d2 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 10f 105 0f9 0e9 0dc 0e6 0f6 0fe 0e2 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 03e
	TestAddr: 2a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  P  P  P  P  P  .  .  P 
				ResultFound  :     Y  Y  Y  Y  Y        Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1e 1e 1e 1e 1e 1f 1f 1e
				Result       :  P                 P  P    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  .  P  P  P  P  P 
				ResultFound  :  Y  Y  Y     Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 0f 13 13 13 13 13
				Result       :           P                
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 10 14 14 14 14 14
				Result       :  P  P  .  P  P  .  .  P  P 
				ResultFound  :        Y        Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 14 11 15 14 14 15 15
				Result       :  .  .     P  .        P  . 
				ResultFound  :  Y  Y  Y     Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 14 12 15 14 14 16 15
				Result       :           P           .    
				ResultFound  :  Y  Y  Y     Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 14 13 15 14 14 16 15
				Result       :           P                
				ResultFound  :  Y  Y  Y     Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 14 14 15 14 14 16 15
				Result       :           .                
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1e       14       16         09
		 1        1f       15       16         0a
		 2        1f       13       14         09
		 3        1e       13       15         09
		 4        1e       14       16         09
		 5        1e       13       15         09
		 6        1e       13       15         09
		 7        1e       14       16         09
		 8        1f       14       15         0a

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 041
	TestAddr: 2a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 03e
	TestAddr: 2a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  P  P  P  P  P  P  .  .  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y        Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1f 1f 1e
				Result       :                    P  P    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  .  .  P  P  P  P  P 
				ResultFound  :  Y  Y        Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 0f 0f 13 13 13 13 13
				Result       :        P  P                
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 10 10 14 14 14 14 14
				Result       :  P  P  P  P  P  .  .  P  P 
				ResultFound  :                 Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 11 11 15 14 14 15 15
				Result       :  .  .  P  P  .        P  . 
				ResultFound  :  Y  Y        Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 12 12 15 14 14 16 15
				Result       :        P  P           .    
				ResultFound  :  Y  Y        Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 13 13 15 14 14 16 15
				Result       :        .  .                
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1e       14       16         09
		 1        1f       15       16         0a
		 2        1f       13       14         09
		 3        1e       13       15         09
		 4        1e       14       16         09
		 5        1e       12       14         08
		 6        1e       12       14         08
		 7        1e       14       16         09
		 8        1e       14       16         09


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  .  .  .  .  .  .  P  . 
				ResultFound  :  Y                    Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 04 04 04 04 04 04 00 04
				Result       :     P  P  P  P  P  P     P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  P  P  P  P  P  P  P  .  P 
				ResultFound  :                       Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 18 19
				Result       :  .  .  .  P  P  .  .     . 
				ResultFound  :  Y  Y  Y        Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 1a 1a 19 19 18 19
				Result       :           .  .             
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        03       18       15         0e
		 1        00       17       17         0c
		 2        04       18       14         0e
		 3        04       18       14         0e
		 4        04       19       15         0f
		 5        04       19       15         0f
		 6        04       18       14         0e
		 7        04       18       14         0e
		 8        00       18       18         0c
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 2a0200000
			Dly  2e
			Dly  2f
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36
			Dly  37  P		Final MaxRdLat: 03d
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 4a 47 46 45 3e 3f 42 44 3e    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 4a 46 46 45 3d 40 42 43 3d    <<< Nibble 1			WrDqs: 4a 47 46 45 3e 40 42 44 3e    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 051 04d 046 03f 040 044 04b 051 03e    <<< Nibble 0		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 052 04e 046 040 040 045 04c 051 03f    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1b 1b 1c 1b 1b 1b 1b 1b 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1a 1b 1b 1b 1b 1c 1b 1b 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1c 1b 1b 1b 1b 1c 1b 
		Fence: 16
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 6, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 52 4e 4d 4c 44 46 48 4b 44 
			WrtLvTrEn = 1
			  PRE: 4c 47 47 45 3c 3f 42 45 3d    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 52 4e 4d 4c 44 46 48 4b 44 
			WrtLvTrEn = 1
			  PRE: 4a 47 47 45 3c 3f 42 43 3c    <<< Nibble 1			WrDqs: 4b 47 47 45 3c 3f 42 44 3d    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 022 01d 055 04d 04c 053 01a 021 04b    <<< Nibble 0		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 023 01e 055 04e 04d 054 01b 021 04c    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1b 1b 1b 1b 1b 1b 1b 1b 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 1a 1a 1a 1a 19 1a 1a 1a 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1b 1b 1b 1b 1b 1a 1b 1a 
		Fence: 15
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 6, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 59 53 53 51 45 49 4d 4f 46 
			WrtLvTrEn = 1
			  PRE: 5e 58 56 53 49 4d 51 55 49    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 59 53 53 51 45 49 4d 4f 46 
			WrtLvTrEn = 1
			  PRE: 5b 58 56 52 48 4c 50 52 48    <<< Nibble 1			WrDqs: 5d 58 56 53 49 4d 51 54 49    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04c 046 03b 031 02f 037 041 04b 02f    <<< Nibble 0		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 04f 048 03c 032 02f 039 043 04c 030    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 533 MHz -> 667 MHz
			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 1a 1a 1a 1a 
		Fence: 14

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 18 18 18 18 19 18 19 19 1a 
		Fence: 13

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 19 19 19 19 19 19 19 1a 
		Fence: 14
			CS2 RC10 0002
			CS2 MR2 00090
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 6, Dct: 0, CS: 2, MR0: 00001B58
			CS2 MR0 01b58
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 2c 26 23 5f 53 58 5d 21 53 
			WrtLvTrEn = 1
			  PRE: 2a 24 21 5e 51 56 5d 1f 54    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 2c 26 23 5f 53 58 5d 21 53 
			WrtLvTrEn = 1
			  PRE: 28 23 21 5e 50 56 5c 1e 52    <<< Nibble 1			WrDqs: 29 24 21 5e 51 56 5d 1f 53    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00090
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 036 02e 01f 052 050 05d 02a 035 050    <<< Nibble 0		TestAddr 320200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 037 02f 01f 053 052 05c 02a 034 053    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 03e
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 117 10f 0ff 0f3 0f1 0fd 10a 115 0f2 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 127 11f 10f 103 101 10d 11a 125 102 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 03f
	TestAddr: 320200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  P  .  .  .  .  P  .  P  P 
				ResultFound  :     Y  Y  Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 1c 1c 1c 1c 18 1c 18 18
				Result       :  .              .     .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 1d 1d 1d 1d 19 1d 19 19
				Result       :  .  .  .  .  P  .  P  .  . 
				ResultFound  :              Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1e 1e 1e 1d 1a 1d 1a 1a
				Result       :  .  .  P  .     .     .  . 
				ResultFound  :        Y     Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1f 1e 1f 1d 1b 1d 1b 1b
				Result       :  .  P     P     .     .  . 
				ResultFound  :     Y  Y  Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1f 1e 1f 1d 1c 1d 1c 1c
				Result       :  .              P     P  P 
				ResultFound  :     Y  Y  Y  Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1f 1e 1f 1d 1c 1d 1c 1c
				Result       :  P                         
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  .  P  P  P  P  .  P  P 
				ResultFound  :  Y     Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 0f 13 13 13 13 0f 13 13
				Result       :     P              P       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 10 14 14 14 14 10 14 14
				Result       :  P  P  .  P  P  .  P  .  . 
				ResultFound  :        Y        Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 11 14 15 15 14 11 14 14
				Result       :  .  P     .  .     P       
				ResultFound  :  Y     Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 12 14 15 15 14 12 14 14
				Result       :     P              P       
				ResultFound  :  Y     Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 13 14 15 15 14 13 14 14
				Result       :     .              .       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1c       13       17         08
		 1        1c       13       17         08
		 2        1d       12       15         08
		 3        1c       13       17         08
		 4        1d       14       17         09
		 5        1f       14       15         0a
		 6        1e       13       15         09
		 7        1f       12       13         09
		 8        1d       14       17         09

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 042
	TestAddr: 320200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 03e
	TestAddr: 320200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  P  .  P  P 
				ResultFound  :  Y  Y  Y  Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 18 1c 18 18
				Result       :                 .     .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 19 1d 19 19
				Result       :  P  .  .  .  P  .  P  .  . 
				ResultFound  :  Y           Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1e 1e 1e 1d 1a 1d 1a 1a
				Result       :     .  P  .     .     .  . 
				ResultFound  :  Y     Y     Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1f 1e 1f 1d 1b 1d 1b 1b
				Result       :     P     P     .     .  . 
				ResultFound  :  Y  Y  Y  Y  Y     Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1f 1e 1f 1d 1c 1d 1c 1c
				Result       :                 P     P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  .  P  P  P  P  .  P  P 
				ResultFound  :  Y     Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 0f 13 13 13 13 0f 13 13
				Result       :     P              P       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 10 14 14 14 14 10 14 14
				Result       :  .  P  .  P  P  .  P  .  . 
				ResultFound  :  Y     Y        Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 11 14 15 15 14 11 14 14
				Result       :     P     .  .     P       
				ResultFound  :  Y     Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 12 14 15 15 14 12 14 14
				Result       :     P              P       
				ResultFound  :  Y     Y  Y  Y  Y     Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 13 14 15 15 14 13 14 14
				Result       :     P              .       
				ResultFound  :  Y     Y  Y  Y  Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 15 15 14 13 14 14
				Result       :     .                      
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        1c       13       17         08
		 1        1c       13       17         08
		 2        1d       12       15         08
		 3        1c       13       17         08
		 4        1d       14       17         09
		 5        1f       14       15         0a
		 6        1e       13       15         09
		 7        1f       13       14         09
		 8        1d       13       16         08


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  P  P  P  .  . 
				ResultFound  :              Y  Y  Y       

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 00 00 00 04 04
				Result       :  P  P  P  P           P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1b 1b 1b 1b
				Result       :                 .  .  P  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y     Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1b 1b 1c 1b
				Result       :                       .    
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        03       1a       17         0f
		 1        03       1b       18         0f
		 2        00       1a       1a         0d
		 3        00       1a       1a         0d
		 4        00       19       19         0d
		 5        04       19       15         0f
		 6        04       19       15         0f
		 7        04       19       15         0f
		 8        04       19       15         0f
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 320200000
			Dly  2e
			Dly  2f
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36
			Dly  37
			Dly  38  P		Final MaxRdLat: 03e
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

Calling out to Platform BIOS...
MemFInitTableDrive [7] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 41 40 3e 3e 3e 40 40 43 3a    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 3b 3b 3b 3b 3b 3b 3b 3b 3b 
			WrtLvTrEn = 1
			  PRE: 40 3f 3c 3d 3d 3f 40 43 39    <<< Nibble 1			WrDqs: 41 40 3d 3e 3e 40 40 43 3a    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [8] Start
MemFInitTableDrive End
		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 048 043 03d 035 02d 032 03a 03e 02f    <<< Nibble 0		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 048 042 03c 035 02e 031 039 03e 030    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [9] Start
MemFInitTableDrive End

MemClkFreq changed: 333 MHz -> 400 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1c 1c 1b 1b 1b 1b 1b 1c 1b 
		Fence: 16

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1b 1b 1a 1b 1a 1a 1a 1a 
		Fence: 15

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1b 1c 1b 1b 1b 1b 1c 1b 1c 
		Fence: 16
			CS2 RC10 0000
			CS2 MR2 00080
			CS2 MR3 00000
			CS2 MR1 00042
	Log last MR0
		Node: 7, Dct: 0, CS: 2, MR0: 00001528
			CS2 MR0 01528
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 46 42 44 44 46 46 4a 3f 
			WrtLvTrEn = 1
			  PRE: 42 40 3d 3d 3d 41 41 44 39    <<< Nibble 0			CS2 MR1 000c2
			CS2 MR2 00080

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 47 46 42 44 44 46 46 4a 3f 
			WrtLvTrEn = 1
			  PRE: 41 3f 3d 3c 3d 41 40 44 38    <<< Nibble 1			WrDqs: 42 40 3d 3d 3d 41 41 44 39    <<< Nibble AVG

			CS2 MR1 00042
			CS2 MR2 00080
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 057 050 049 03e 035 03b 045 04b 039    <<< Nibble 0		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 057 050 04b 040 036 03d 045 04b 039    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 400 MHz -> 533 MHz
			RdOdtTrnOnDly = 1
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1b 1b 1a 1a 1a 1a 1b 
		Fence: 15

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 19 19 1a 19 1a 1a 
		Fence: 14

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1b 1a 1b 1b 1b 1b 1b 
		Fence: 15
			CS2 RC10 0001
			CS2 MR2 00088
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 7, Dct: 0, CS: 2, MR0: 00001938
			CS2 MR0 01938
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4d 4a 46 46 46 4b 4b 4f 41 
			WrtLvTrEn = 1
			  PRE: 51 4e 4a 49 48 4f 4e 52 43    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00088

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 4d 4a 46 46 46 4b 4b 4f 41 
			WrtLvTrEn = 1
			  PRE: 4f 4c 48 48 47 4d 4d 51 41    <<< Nibble 1			WrDqs: 50 4d 49 49 48 4e 4e 52 42    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00088
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03d 035 02c 05f 051 05c 028 02f 056    <<< Nibble 0		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 03f 036 02e 061 054 05d 027 030 058    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End

MemClkFreq changed: 533 MHz -> 667 MHz
			RdOdtTrnOnDly = 2
			RdOdtOnDuration = 6
MemFInitTableDrive [1] Start
MemFInitTableDrive End
MemFInitTableDrive [2] Start
MemFInitTableDrive End
		RdPtr: 6
MemFInitTableDrive [10] Start
MemFInitTableDrive End
		FenceThresholdTxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 1a 1a 1a 1a 1a 1a 1a 1a 19 
		Fence: 14

		FenceThresholdRxDll
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 19 19 19 18 19 19 18 18 
		Fence: 13

		FenceThresholdTxPad
		Seeds: 13 13 13 13 13 13 13 13 13 
		PhyFenceTrEn = 1
		  PRE: 19 1a 19 19 19 19 19 19 19 
		Fence: 14
			CS2 RC10 0002
			CS2 MR2 00090
			CS2 MR3 00000
			CS2 MR1 00006
	Log last MR0
		Node: 7, Dct: 0, CS: 2, MR0: 00001B58
			CS2 MR0 01b58
MemFInitTableDrive [A] Start
MemFInitTableDrive End
			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 5c 58 53 53 52 59 59 5e 4a 
			WrtLvTrEn = 1
			  PRE: 5a 57 51 50 50 57 58 5d 4c    <<< Nibble 0			CS2 MR1 00086
			CS2 MR2 00090

			 Byte: 00 01 02 03 04 05 06 07 ECC
			Seeds: 5c 58 53 53 52 59 59 5e 4a 
			WrtLvTrEn = 1
			  PRE: 58 56 4f 4f 4f 56 58 5c 4a    <<< Nibble 1			WrDqs: 59 57 50 50 50 57 58 5d 4b    <<< Nibble AVG

			CS2 MR1 00006
			CS2 MR2 00090
End write leveling

MemFInitTableDrive [B] Start
MemFInitTableDrive End
		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 022 058 04b 03b 02d 037 047 050 034    <<< Nibble 0		TestAddr 3a0200000
			     Byte:  00  01  02  03  04  05  06  07  ECC
			      PRE: 022 057 04c 03c 02f 039 047 050 034    <<< Nibble 1End HW RxEn training

MemFInitTableDrive [C] Start
MemFInitTableDrive End
		MaxRdLat: 03e
MemFInitTableDrive [D] Start
MemFInitTableDrive End
			Increase WrDat, Train RdDqs:

			Write Delay: 10

Start HW RxEn Seedless training

	Chip Select: 02 
			       Byte:  00  01  02  03  04  05  06  07  ECC
				RxEn Orig: 102 0f8 0ec 0dc 0ce 0d8 0e7 0f0 0d4 
		i: 00

		j: 00

		 Setting PassTestRxEnDly
	  PassTestRxEnDly: 112 108 0fc 0ec 0de 0e8 0f7 100 0e4 
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
		 Checking if PassTestRxEnDly Passes?

		MaxRdLat: 03e
	TestAddr: 3a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  P  .  .  .  . 
				ResultFound  :              Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1d 1e 1e 1e 1e
				Result       :  .  P  P  P     P  .  .  . 
				ResultFound  :     Y  Y  Y  Y  Y          

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1e 1e 1e 1d 1e 1f 1f 1f
				Result       :  .                 .  P  . 
				ResultFound  :     Y  Y  Y  Y  Y     Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 1e 1e 1e 1d 1e 00 1f 00
				Result       :  P                 P     P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  .  P  .  .  P  . 
				ResultFound  :  Y  Y  Y     Y        Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 0f 13 0f 0f 13 0f
				Result       :           P     P  P     P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 10 14 10 10 14 10
				Result       :  .  P  .  P  .  P  P  P  P 
				ResultFound  :  Y     Y     Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 15 14 11 14 11 11 15 11
				Result       :     .     P     P  P  .  . 
				ResultFound  :  Y  Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 15 14 12 14 12 12 15 11
				Result       :           P     P  P       
				ResultFound  :  Y  Y  Y     Y        Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 15 14 13 14 13 13 15 11
				Result       :           .     .  .       
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        00       10       10         08
		 1        1f       14       15         0a
		 2        00       12       12         09
		 3        1e       12       14         08
		 4        1d       13       16         08
		 5        1e       12       14         08
		 6        1e       13       15         09
		 7        1e       14       16         09
		 8        00       13       13         0a

		Setting FailTestRxEnDly
	       OutOfRange:  N   N   N   N   N   N   N   N   N  
	  FailTestRxEnDly:  Y   Y   Y   Y   Y   Y   Y   Y   Y  

		 Checking if FailTestRxEnDly Fails?
		MaxRdLat: 041
	TestAddr: 3a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 01 01 01 01 01 01 01 01 01
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 02 02 02 02 02 02 02 02 02
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 03 03 03 03 03 03 03 03 03
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 04 04 04 04 04 04 04 04 04
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 05 05 05 05 05 05 05 05 05
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 06 06 06 06 06 06 06 06 06
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 07 07 07 07 07 07 07 07 07
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 08 08 08 08 08 08 08 08 08
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 09 09 09 09 09 09 09 09 09
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0a 0a 0a 0a 0a 0a 0a 0a 0a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0b 0b 0b 0b 0b 0b 0b 0b 0b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0c 0c 0c 0c 0c 0c 0c 0c 0c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0d 0d 0d 0d 0d 0d 0d 0d 0d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0e 0e 0e 0e 0e 0e 0e 0e 0e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 0f 0f 0f 0f 0f 0f 0f 0f 0f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 10 10 10 10 10 10 10 10 10
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 11 11 11 11 11 11 11 11 11
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 12 12 12 12 12 12 12 12 12
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 14 14 14 14 14 14
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 15 15 15 15 15 15 15 15 15
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 16 16 16 16 16 16 16 16 16
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 19 19 19 19 19 19 19 19 19
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1a 1a 1a 1a 1a 1a 1a 1a 1a
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1e 1e 1e 1e 1e
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

		--DATA EYE NOT FOUND--


   Set FinalRxEnCycle:  Y   Y   Y   Y   Y   Y   Y   Y   Y  
	       OutOfRange:  N   N   N   N   N   N   N   N   N  

			 Setting new RDQS based on FinalRxEnCycle 

		MaxRdLat: 03e
	TestAddr: 3a0200000
			STAGE: 0	Sweeping Read DQS, decrementing from 00 by 04, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1c 1c 1c 1c 1c 1c 1c 1c 1c
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1d 1d 1d 1d 1d 1d 1d 1d 1d
				Result       :  .  .  .  .  P  .  .  .  . 
				ResultFound  :              Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1e 1e 1e 1e 1d 1e 1e 1e 1e
				Result       :  .  P  P  P     P  .  .  . 
				ResultFound  :     Y  Y  Y  Y  Y          

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1e 1e 1e 1d 1e 1f 1f 1f
				Result       :  .                 .  P  . 
				ResultFound  :     Y  Y  Y  Y  Y     Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 1e 1e 1e 1d 1e 00 1f 00
				Result       :  P                 P     P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 2	Sweeping Read DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 13 13 13 13 13 13
				Result       :  P  P  P  .  P  .  .  P  . 
				ResultFound  :  Y  Y  Y     Y        Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 13 13 13 0f 13 0f 0f 13 0f
				Result       :           P     P  P     P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Read DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 10 14 10 10 14 10
				Result       :  .  .  .  P  .  P  P  P  P 
				ResultFound  :  Y  Y  Y     Y             

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 11 14 11 11 15 11
				Result       :           P     P  P  P  . 
				ResultFound  :  Y  Y  Y     Y           Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 12 14 12 12 16 11
				Result       :           P     P  .  .    
				ResultFound  :  Y  Y  Y     Y     Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 14 14 14 13 14 13 12 16 11
				Result       :           .     .          
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        00       10       10         08
		 1        1f       15       16         0a
		 2        00       11       11         09
		 3        1e       12       14         08
		 4        1d       13       16         08
		 5        1e       12       14         08
		 6        1e       13       15         09
		 7        1e       13       15         09
		 8        00       13       13         0a


End HW RxEn Seedless training


			Train WrDat:

			STAGE: 0	Sweeping Write DQS, incrementing from 00 by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 00 00 00 00 00 00 00 00
				Result       :  P  .  .  .  .  .  .  .  . 
				ResultFound  :  Y                         

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 00 04 04 04 04 04 04 04 04
				Result       :     P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 1	Sweeping Write DQS, decrementing from Current Delay by 01, until all bytelanes FAIL.

			STAGE: 2	Sweeping Write DQS, decrementing from 1f by 04, until all bytelanes PASS.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1f 1f 1f 1f 1f 1f 1f 1f 1f
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 1b 1b 1b 1b 1b 1b 1b 1b 1b
				Result       :  .  .  .  .  .  .  .  .  . 
				ResultFound  :                            

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 17 17 17 17 17 17 17 17 17
				Result       :  P  P  P  P  P  P  P  P  P 
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

			STAGE: 3	Sweeping Write DQS, incrementing from Current Delay by 01, until all bytelanes FAIL.

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 18 18 18 18 18 18 18 18
				Result       :  .  P  P  P  P  P  .  .  P 
				ResultFound  :  Y                 Y  Y    

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 19 19 19 19 19 18 18 19
				Result       :     .  .  .  P  .        . 
				ResultFound  :  Y  Y  Y  Y     Y  Y  Y  Y 

				Byte Lane    : 08 07 06 05 04 03 02 01 00
				DQS Delays   : 18 19 19 19 1a 19 18 18 19
				Result       :              .             
				ResultFound  :  Y  Y  Y  Y  Y  Y  Y  Y  Y 

		Data Eye Results:

		Byte     Left     Right
		Lane     Edge     Edge     Width     Center
		 0        03       18       15         0e
		 1        03       17       14         0d
		 2        03       17       14         0d
		 3        03       18       15         0e
		 4        03       19       16         0e
		 5        03       18       15         0e
		 6        03       18       15         0e
		 7        03       18       15         0e
		 8        00       17       17         0c
End Read/Write Data Eye Edge Detection

MemFInitTableDrive [E] Start
MemFInitTableDrive End
			Write to address: 3a0200000
			Dly  2e
			Dly  2f
			Dly  30
			Dly  31
			Dly  32
			Dly  33
			Dly  34
			Dly  35
			Dly  36
			Dly  37  P		Final MaxRdLat: 03d
End MaxRdLat training

MemFInitTableDrive [F] Start
MemFInitTableDrive End
	Release NB Pstate force

End DQS training

		LD: 2     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 09
		CDDTwrrd     : 00           Twrrd     : 02
		CDDTrwtTO    : 06           TrwtTO    : 08

		LD: 2     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 09
		CDDTwrrd     : 00           Twrrd     : 02
		CDDTrwtTO    : 06           TrwtTO    : 08

		LD: 1     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 07
		CDDTwrrd     : 00           Twrrd     : 03
		CDDTrwtTO    : 05           TrwtTO    : 06

		LD: 1     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 07
		CDDTwrrd     : 00           Twrrd     : 03
		CDDTrwtTO    : 04           TrwtTO    : 06

		LD: 2     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 09
		CDDTwrrd     : 00           Twrrd     : 02
		CDDTrwtTO    : 06           TrwtTO    : 08

		LD: 2     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 08
		CDDTwrrd     : 00           Twrrd     : 02
		CDDTrwtTO    : 05           TrwtTO    : 07

		LD: 2     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 09
		CDDTwrrd     : 00           Twrrd     : 02
		CDDTrwtTO    : 06           TrwtTO    : 08

		LD: 2     ROD: 0     WOD: 0     WrEarly: 0

		                            TrdrdSdSc : 01
		CDDTrdrdSdDc : 00           TrdrdSdDc : 03
		CDDTrdrdDd   : 00           TrdrdDd   : 04

		                            TwrwrSdSc  : 01
		CDDTwrwrSdDc : 00           TwrwrSdDc : 03
		CDDTwrwrDd   : 00           TwrwrDd   : 04

		                            TrwtWB    : 09
		CDDTwrrd     : 00           Twrrd     : 02
		CDDTrwtTO    : 06           TrwtTO    : 08


End Non-SPD Timings.
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [6] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
MemFInitTableDrive [11] Start
MemFInitTableDrive End
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
	Dct 0
		ODTSEn = 0
		ExtendTmp = 1
	Dct 1
		ODTSEn = 0
		ExtendTmp = 1
MemFInitTableDrive [13] Start
MemFInitTableDrive End
MemFInitTableDrive [13] Start
MemFInitTableDrive End
MemFInitTableDrive [13] Start
MemFInitTableDrive End
MemFInitTableDrive [13] Start
MemFInitTableDrive End
MemFInitTableDrive [13] Start
MemFInitTableDrive End
MemFInitTableDrive [13] Start
MemFInitTableDrive End
MemFInitTableDrive [13] Start
MemFInitTableDrive End
MemFInitTableDrive [13] Start
MemFInitTableDrive End

 * BOUNDS_CHK Event: 08040100 Data: 1240000, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: 1241000, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: 1242000, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: 1243000, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: 1244000, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: 1245000, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: 1246000, 0, 0, 0


 * BOUNDS_CHK Event: 08040100 Data: 1248000, 0, 0, 0

AmdMemAuto: End
AmdCpuPost: Start
  Dispatch CPU features after AP MTRR sync
    MT C1e is enabled
    Enabling L3 dependent features
    Boost is enabled
    Cache flush on hlt feature is enabled
  Perform feature leveling
  Create P-state info in the heap
  Dispatch CPU features before Relinquishing control of APs
    Low pwr P-state is enabled
    APM mode is enabled
  Relinquish control of APs


coreboot-unknown Wed Aug 22 17:12:18 MSK 2012 starting...
BSP Family_Model: 00600f12 
cpu_init_detectedx = 00000000 
agesawrapper_amdinitreset passed
cimx/rd890 early.c nb_Poweron_Init() Start
NbPowerOnResetInit entry
[NB]NbInitializer Enter
[NB]NbMiscInitializer Enter
[NB]NbMiscInitializer Exit
[NBHT]HtLibInitializer Enter
[NBHT]HtLibInitializer Exit
[NBPCIE]PcieLibInitializer Enter
[NBPCIE]PcieLibInitializer Exit
[NB]NbInitializer Exit
[NBPOR]NbPowerOnResetInit Enter
[NBPOR]NbPowerOnResetInit Exit
cimx/rd890 early.c nb_Poweron_Init() End. return status=0
cimx/sb700 early.c, sb_Poweron_Init() Start:
SB700 - Cfg.c - sb700_cimx_config - Start.
SB700 - Cfg.c - sb700_cimx_config - End.
CIMx - Entering sbPowerOnInit 
PFA=A000D2  AND=0, OR=1
PFA=A00040  AND=0, OR=44
PFA=A00041  AND=FF, OR=E9
PFA=A00064  AND=0, OR=BF
PFA=A00065  AND=0, OR=78
PFA=A00066  AND=BF, OR=9E
PFA=A00067  AND=F, OR=2
PFA=A00069  AND=0, OR=90
PFA=A0006C  AND=0, OR=20
PFA=A00078  AND=0, OR=FF
PFA=A00004  AND=0, OR=7
PFA=A00005  AND=0, OR=4
PFA=A000E1  AND=0, OR=99
PFA=A000AC  AND=EF, OR=2
PFA=A00062  AND=FC, OR=24
PFA=A30000  AND=A3, OR=0
PFA=A30040  AND=0, OR=4
PFA=A30048  AND=0, OR=7
PFA=A3004A  AND=0, OR=20
PFA=A30078  AND=FE, OR=0
PFA=A3007C  AND=0, OR=5
PFA=A300BB  AND=FE, OR=E9
PFA=A40000  AND=A4, OR=0
PFA=A40040  AND=0, OR=26
PFA=A4004B  AND=FF, OR=D0
PFA=A4001C  AND=0, OR=11
PFA=A4001D  AND=0, OR=11
PFA=A40004  AND=0, OR=21
PFA=A40050  AND=2, OR=1
PMIO Reg = 67   AndMask = FF  OrMask = 2
PMIO Reg = 37   AndMask = FF  OrMask = 4
PMIO Reg = 50   AndMask = 0  OrMask = E0
PMIO Reg = 60   AndMask = FF  OrMask = 20
PMIO Reg = 65   AndMask = 6F  OrMask = 0
PMIO Reg = 55   AndMask = BF  OrMask = 7
PMIO Reg = 66   AndMask = FF  OrMask = 20
PMIO Reg = B2   AndMask = FF  OrMask = 80
PMIO Reg = E   AndMask = FF  OrMask = 8
PMIO Reg = D7   AndMask = F6  OrMask = 80
PMIO Reg = 7C   AndMask = FF  OrMask = 10
PMIO Reg = 75   AndMask = C0  OrMask = 5
PMIO Reg = 52   AndMask = C0  OrMask = 8
PMIO Reg = 8B   AndMask = 0  OrMask = 10
PMIO Reg = 69   AndMask = F9  OrMask = 2
PFA=A00043  AND=F7, OR=0
PFA=A00038  AND=7F, OR=0
PFA=A000AD  AND=DF, OR=0
PFA=A00043  AND=FF, OR=8
PMIO Reg = D7   AndMask = FF  OrMask = 21
PMIO Reg = BB   AndMask = 7F  OrMask = 60
PFA=A3008E  AND=FD, OR=0
cimx/sb700 early.c, sb_Poweron_Init() End
AllocateExecutionCache: Start
AllocateExecutionCache: End

AmdInitEarly: Start 0 

AmdHtInitialize: Start
AMD Processor at Node 0 has raw CPUID=600f12.
ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c',  line 424
