ÿ coreboot-4.0-2743-gff07e39-dirty Tue Aug 28 17:06:50 CEST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: coreboot-4.0-2743-gff07e39-dirty Tue Aug 28 17:06:50 CEST 2012 starting... now booting... * AP 01started SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x0, freq=0x5, needs_reset=0x1 dev2 old_freq=0x0, freq=0x5, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 01K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 01No config data specified, using default MAC! ht reset - soft reset coreboot-4.0-2743-gff07e39-dirty Tue Aug 28 17:06:50 CEST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: coreboot-4.0-2743-gff07e39-dirty Tue Aug 28 17:06:50 CEST 2012 starting... now booting... * AP 01started SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change toggle LDTSTP# done Current fid_cur: 0x2, fid_max: 0xd Requested fid_new: 0xd FidVid table step fidvid: 0xc toggle LDTSTP# done 100MHZ step fidvid: 0xd toggle LDTSTP# done toggle LDTSTP# done Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000ceed0 Device error Device error Enabling dual channel memory Unbuffered 266MHz 266MHz Interleaving disabled RAM end at 0x00080000 kB Ram3 IN TEST WAKEUP 00Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=10 done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9a0 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce888 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce878 TrainDQSPos: MutualCSPassW[48] :000ce888 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=34 done DQS SAVE NVRAM: c2000 Writing 111222 of size 4 to nvram pos: 0 Writing 18181818 of size 4 to nvram pos: 4 Writing 17181819 of size 4 to nvram pos: 8 Writing 18 of size 1 to nvram pos: 12 Writing 2b2f00 of size 4 to nvram pos: 13 Writing 15151414 of size 4 to nvram pos: 17 Writing 14151414 of size 4 to nvram pos: 21 Writing 14 of size 1 to nvram pos: 25 Writing 34 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 Writing 111222 of size 4 to nvram pos: 30 Writing 18181818 of size 4 to nvram pos: 34 Writing 17181818 of size 4 to nvram pos: 38 Writing 18 of size 1 to nvram pos: 42 Writing 2b2f00 of size 4 to nvram pos: 43 Writing 15151516 of size 4 to nvram pos: 47 Writing 16161515 of size 4 to nvram pos: 51 Writing 15 of size 1 to nvram pos: 55 Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 Writing 34008099 of size 4 to nvram pos: 60 DQS Training:tsc[00]=00000000a54ed763 DQS Training:tsc[01]=00000000a736f534 DQS Training:tsc[02]=00000000a736f547 DQS Training:tsc[03]=000000014895fc2f DQS Training:tsc[04]=000000015960aea7 Ram4 v_esp=000cef18 testx = 5a5a5a5a IN TEST WAKEUP 00Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (557056 bytes), entry @ 0x100000 Jumping to image. coreboot-4.0-2743-gff07e39-dirty Tue Aug 28 17:06:50 CEST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.5: enabled 1 IOAPIC: 09: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 IOAPIC: 08: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.5: enabled 1 IOAPIC: 09: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 IOAPIC: 08: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled XXXdev path: PCI: 00:00.0 PCI: 00:00.0 [1106/0336] ops PCI: 00:00.0 [1106/0336] enabled Capability: type 0x02 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x08 @ 0x60 flags: 0x0060 PCI: 00:00.0 count: 0003 static_count: 0010 PCI: 00:00.0 [1106/0336] enabled next_unitid: 0010 PCI: 00:0f.0 PCI: 00:10.0 PCI: 00:10.1 PCI: 00:10.2 PCI: 00:10.3 PCI: 00:10.4 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:13.0 PCI: 00:13.1 HT: Leftover static devices. Check your devicetree.cb PCI: pci_scan_bus for bus 00 XXXdev path: PCI: 00:00.0 PCI: 00:00.0 [1106/0336] enabled PCI: 00:00.1 [1106/0000] ops K8x8xx: Enabling NB error reporting: Done VIA_X_1 device dump: 00: 06 11 36 13 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.1 [1106/1336] enabled PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops K8M890: UMA base is 1e000000 size is 32 (MB) VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff 30 00 20 19 00 20 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.3 [1106/3336] enabled PCI: 00:00.4 [1106/4336] enabled XXXdev path: PCI: 00:00.5 PCI: 00:00.5 [1106/5336] bus ops PCI: 00:00.5 [1106/5336] enabled PCI: 00:00.6 [1106/6290] enabled PCI: 00:00.7 [1106/0000] ops PCI: 00:00.7 [1106/7336] enabled XXXdev path: PCI: 00:01.0 PCI: 00:01.0 [1106/b188] bus ops B188 device dump 00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00 40: 91 40 08 44 31 3a 88 b1 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 0e 70 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 80 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00 c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.0 [1106/b188] enabled XXXdev path: PCI: 00:02.0 PCI: 00:02.0 [1106/a238] bus ops Configuring PCIe PEG 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c 12 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 07 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 PCIe link timeout 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 7c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c f0 40 81 00 00 03 00 01 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 0b 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 [1106/a238] enabled PCI: 00:03.0 [1106/c238] bus ops Configuring PCIe PEXs 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 10 01 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 PCIe link timeout 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 10 01 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 [1106/c238] enabled PCI: 00:0f.0 [1106/5372] ops PCI: 00:0f.0 [1106/5372] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: Left over static devices: PCI: 00:10.0 PCI: 00:10.1 PCI: 00:10.2 PCI: 00:10.3 PCI: 00:10.4 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:13.0 PCI: 00:13.1 PCI: Check your devicetree.cb. scan_static_bus for PCI: 00:00.5 XXXENABLE OF IOAPIC calledIOAPIC: 09 enabled scan_static_bus for PCI: 00:00.5 done do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 XXXdev path: PCI: 01:00.0 PCI: 01:00.0 [1106/3230] ops PCI: 01:00.0 [1106/3230] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 02 XXXdev path: PCI: 02:00.0 PCI: Static device PCI: 02:00.0 not found, disabling it. PCI: pci_scan_bus returning with max=002 Capability: type 0xff @ 0xfc do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus returning with max=003 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.5 read_resources bus 0 link: 0 PCI: 00:00.5 read_resources bus 0 link: 0 done PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:02.0 read_resources bus 2 link: 0 PCI: 00:02.0 read_resources bus 2 link: 0 done PCI: 00:02.0 read_resources bus 0 link: 1 PCI: 00:00.0 missing read_resources PCI: 00:02.0 read_resources bus 0 link: 1 done PCI: 00:03.0 read_resources bus 3 link: 0 PCI: 00:03.0 read_resources bus 3 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8 PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 child on link 0 IOAPIC: 09 PCI: 00:00.5 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 10000200 index 61 IOAPIC: 09 IOAPIC: 09 resource base fecc0000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 0 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 00:00.0 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:0f.0 24 * [0x0 - 0xff] io PCI: 00:0f.0 20 * [0x400 - 0x40f] io PCI: 00:0f.1 20 * [0x410 - 0x41f] io PCI: 00:0f.0 10 * [0x420 - 0x427] io PCI: 00:0f.0 18 * [0x428 - 0x42f] io PCI: 00:0f.0 14 * [0x430 - 0x433] io PCI: 00:0f.0 1c * [0x434 - 0x437] io PCI: 00:18.0 compute_resources_io: base: 438 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 00 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 24 * [0x10000000 - 0x1fffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 14 * [0x0 - 0xffffff] mem PCI: 01:00.0 30 * [0x1000000 - 0x100ffff] mem PCI: 00:01.0 compute_resources_mem: base: 1010000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.5 61 * [0x0 - 0xfffffff] mem PCI: 00:01.0 20 * [0x10000000 - 0x110fffff] mem PCI: 00:18.0 compute_resources_mem: base: 11100000 size: 11100000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 02 * [0x0 - 0x1fffffff] prefmem PCI: 00:18.0 01 * [0x20000000 - 0x310fffff] mem PCI: 00:18.3 94 * [0x34000000 - 0x37ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.5 constrain_resources: IOAPIC: 09 constrain_resources: PCI: 00:00.6 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:03.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 000c0000 lim->limit fecbffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:1000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 00 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1000 size: 1000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 00:0f.0 24 * [0x0 - 0xff] io Assigned: PCI: 00:0f.0 20 * [0x400 - 0x40f] io Assigned: PCI: 00:0f.1 20 * [0x410 - 0x41f] io Assigned: PCI: 00:0f.0 10 * [0x420 - 0x427] io Assigned: PCI: 00:0f.0 18 * [0x428 - 0x42f] io Assigned: PCI: 00:0f.0 14 * [0x430 - 0x433] io Assigned: PCI: 00:0f.0 1c * [0x434 - 0x437] io PCI: 00:18.0 allocate_resources_io: next_base: 438 size: 1000 align: 12 gran: 12 done PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:03.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:03.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000 align:28 gran:0 limit:fecbffff Assigned: PCI: 00:18.0 02 * [0xc0000000 - 0xdfffffff] prefmem Assigned: PCI: 00:18.0 01 * [0xe0000000 - 0xf10fffff] mem Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size: 38000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:28 gran:20 limit:fecbffff Assigned: PCI: 00:00.0 10 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 00:01.0 24 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_prefmem: base:d0000000 size:10000000 align:28 gran:20 limit:fecbffff Assigned: PCI: 01:00.0 10 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: e0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:02.0 allocate_resources_prefmem: base:fecbffff size:0 align:20 gran:20 limit:fecbffff PCI: 00:02.0 allocate_resources_prefmem: next_base: fecbffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_prefmem: base:fecbffff size:0 align:20 gran:20 limit:fecbffff PCI: 00:03.0 allocate_resources_prefmem: next_base: fecbffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:e0000000 size:11100000 align:28 gran:20 limit:fecbffff Assigned: PCI: 00:00.5 61 * [0xe0000000 - 0xefffffff] mem Assigned: PCI: 00:01.0 20 * [0xf0000000 - 0xf10fffff] mem PCI: 00:18.0 allocate_resources_mem: next_base: f1100000 size: 11100000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:f0000000 size:1100000 align:24 gran:20 limit:fecbffff Assigned: PCI: 01:00.0 14 * [0xf0000000 - 0xf0ffffff] mem Assigned: PCI: 01:00.0 30 * [0xf1000000 - 0xf100ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: f1010000 size: 1100000 align: 24 gran: 20 done PCI: 00:02.0 allocate_resources_mem: base:fecbffff size:0 align:20 gran:20 limit:fecbffff PCI: 00:02.0 allocate_resources_mem: next_base: fecbffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_mem: base:fecbffff size:0 align:20 gran:20 limit:fecbffff PCI: 00:03.0 allocate_resources_mem: next_base: fecbffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 setup_bsp_ramtop, TOP MEM: msr.lo = 0x20000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000 setup_uma_memory: uma size 0x04000000, memory start 0x1c000000 node 0 : uma_memory_base/1024=0x00070000, mmio_basek=0x00300000, basek=0x00000300, limitk=0x00080000 node 0: UMA memory starts below mmio_basek 0: mmio_basek=00300000, basek=00000300, limitk=00080000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 PCI: 00:18.0 1c0 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c io PCI: 00:18.0 1b8 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 prefmem PCI: 00:18.0 1b0 <- [0x00e0000000 - 0x00f10fffff] size 0x11100000 gran 0x14 mem PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:00.5 assign_resources, bus 0 link: 0 PCI: 00:00.5 assign_resources, bus 0 link: 0 PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem PCI: 01:00.0 14 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f100ffff] size 0x00010000 gran 0x10 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.0 24 <- [0x00fecbffff - 0x00fecbfffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.0 20 <- [0x00fecbffff - 0x00fecbfffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:02.0 assign_resources, bus 2 link: 0 PCI: 00:02.0 assign_resources, bus 2 link: 0 PCI: 00:02.0 assign_resources, bus 0 link: 1 PCI: 00:02.0 assign_resources, bus 0 link: 1 PCI: 00:03.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:03.0 24 <- [0x00fecbffff - 0x00fecbfffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:03.0 20 <- [0x00fecbffff - 0x00fecbfffe] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:0f.0 10 <- [0x0000000420 - 0x0000000427] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x0000000430 - 0x0000000433] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x0000000428 - 0x000000042f] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x0000000434 - 0x0000000437] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000000400 - 0x000000040f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000000000 - 0x00000000ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000000410 - 0x000000041f] size 0x00000010 gran 0x04 io PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 1000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0 limit fecbffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 1c000000 size 4000000 align 0 gran 0 limit 0 flags f0100200 index 7 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080100 index 1c0 PCI: 00:18.0 resource base c0000000 size 20000000 align 28 gran 20 limit fecbffff flags 60081200 index 1b8 PCI: 00:18.0 resource base e0000000 size 11100000 align 28 gran 20 limit fecbffff flags 60080200 index 1b0 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1a8 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit fecbffff flags 60001200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 child on link 0 IOAPIC: 09 PCI: 00:00.5 resource base e0000000 size 10000000 align 28 gran 28 limit fecbffff flags 70000200 index 61 IOAPIC: 09 IOAPIC: 09 resource base fecc0000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 0 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base d0000000 size 10000000 align 28 gran 20 limit fecbffff flags 60081202 index 24 PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit fecbffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base d0000000 size 10000000 align 28 gran 28 limit fecbffff flags 60001200 index 10 PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit fecbffff flags 60000200 index 14 PCI: 01:00.0 resource base f1000000 size 10000 align 16 gran 16 limit fecbffff flags 60002200 index 30 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 index 24 PCI: 00:02.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60080202 index 20 PCI: 02:00.0 PCI: 00:00.0 PCI: 00:03.0 PCI: 00:03.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 index 24 PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60080202 index 20 PCI: 00:0f.0 PCI: 00:0f.0 resource base 420 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 430 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 428 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 434 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 60000100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 410 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit fecbffff flags 60000200 index 94 Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/0000 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/0000 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/0000 PCI: 00:00.0 cmd <- 02 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 cmd <- 06 PCI: 00:00.3 cmd <- 06 PCI: 00:00.4 cmd <- 06 PCI: 00:00.5 cmd <- 06 PCI: 00:00.6 cmd <- 06 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 001f PCI: 00:01.0 cmd <- 07 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 00 PCI: 00:0f.0 subsystem <- 1043/0000 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 01 PCI: 01:00.0 cmd <- 03 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00001000, code_size=0x00000031 Initializing CPU #0 CPU: vendor AMD device 60fb1 CPU: family 0f, model 6b, stepping 01 Enabling cache CPU ID 0x80000001: 60fb1 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 448MB, range: 64MB, type UC Setting variable MTRR 1, base: 0MB, range: 512MB, type WB Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4000+ Setting up local apic... apic_id: 0x00 done. Scrubbing Disabled ECC Disabled CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device 60fb1 CPU: family 0f, model 6b, stepping 01 Enabling cache CPU ID 0x80000001: 60fb1 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 448MB, range: 64MB, type UC Setting variable MTRR 1, base: 0MB, range: 512MB, type WB Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4000+ Setting up local apic... apic_id: 0x01 done. CPU #1 initialized All AP CPUs stopped (7213 loops) PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:00.0 init PCI: 00:00.3 init K8M890: Using a 64MB framebuffer. PCI: 00:00.4 init PCI: 00:00.6 init PCI: 00:00.7 init K8x8xx: Initializing V-Link to VT8237R sb: VT8237R LPC not found ! PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0xb Enables in reg 0x42 read back as 0x9 IOAPIC: 09 init IOAPIC: Initializing IOAPIC at 0xfecc0000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 PCI: 01:00.0 init Chrome: Using 64MB Framebuffer at 0xD0000000. Chrome VGA Textmode initialized. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.5: enabled 1 IOAPIC: 09: enabled 1 PCI: 00:01.0: enabled 1 PCI: 01:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 02:00.0: enabled 0 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 IOAPIC: 08: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 APIC: 01: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.6: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:03.0: enabled 1 Re-Initializing CBMEM area to 0x1bee0000 Initializing CBMEM area to 0x1bee0000 (1179648 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1bee0200...ok High Tables Base is 1bee0000. Adding CBMEM entry as no. 2 ACPI: Writing ACPI tables at 1bee0400... ACPI: * FACS ACPI: * DSDT @ 1bee0540 Length 9bd ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * HPET ACPI: added table 2/32, length now 44 ACPI: * MADT ACPI: added table 3/32, length now 48 ACPI: * MCFG ACPI: added table 4/32, length now 52 ACPI: * SRAT SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=0007fd00 ACPI: added table 5/32, length now 56 ACPI: * SLIT ACPI: added table 6/32, length now 60 ACPI: * SSDT processor_brand=AMD Athlon(tm) 64 X2 Dual Core Processor 4000+ Pstates Algorithm ... Pstate_freq[0] = 2100MHz Pstate_vid[0] = 10 Pstate_volt[0] = 1300mv Pstate_power[0] = 65000mw Pstate_freq[1] = 2000MHz Pstate_vid[1] = 12 Pstate_volt[1] = 1250mv Pstate_power[1] = 57234mw Pstate_freq[2] = 1000MHz Pstate_vid[2] = 18 Pstate_volt[2] = 1100mv Pstate_power[2] = 22161mw PSS: 2100MHz power 65000 control 0xe8202a8d status 0x28d PSS: 2000MHz power 57234 control 0xe8202b0c status 0x30c PSS: 1000MHz power 22161 control 0xe8202c82 status 0x482 PSS: 2100MHz power 65000 control 0xe8202a8d status 0x28d PSS: 2000MHz power 57234 control 0xe8202b0c status 0x30c PSS: 1000MHz power 22161 control 0xe8202c82 status 0x482 ACPI: added table 7/32, length now 64 ACPI: done. ACPI tables: 4299 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 1beeb800 Root Device (ASUS M2V-MX SE Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) PCI_DOMAIN: 0000 (AMD K8 Root Complex) PCI: 00:18.0 (AMD K8 Northbridge) PCI: 00:00.0 (VIA k8x8xx Northbridge) PCI: 00:00.5 (VIA k8x8xx Northbridge) IOAPIC: 09 (IOAPIC) PCI: 00:01.0 (VIA k8x8xx Northbridge) PCI: 01:00.0 (VIA k8x8xx Northbridge) PCI: 00:02.0 (VIA k8x8xx Northbridge) PCI: 02:00.0 (VIA k8x8xx Northbridge) PCI: 00:00.0 (VIA k8x8xx Northbridge) PCI: 00:0f.1 (VIA VT8237R Southbridge) PCI: 00:0f.0 (VIA VT8237R Southbridge) PCI: 00:10.0 (VIA VT8237R Southbridge) PCI: 00:10.1 (VIA VT8237R Southbridge) PCI: 00:10.2 (VIA VT8237R Southbridge) PCI: 00:10.3 (VIA VT8237R Southbridge) PCI: 00:10.4 (VIA VT8237R Southbridge) PCI: 00:11.0 (VIA VT8237R Southbridge) IOAPIC: 08 (IOAPIC) I2C: 00:50 () I2C: 00:51 () I2C: 00:52 () I2C: 00:53 () PNP: 002e.0 (ITE IT8712F Super I/O) PNP: 002e.1 (ITE IT8712F Super I/O) PNP: 002e.2 (ITE IT8712F Super I/O) PNP: 002e.3 (ITE IT8712F Super I/O) PNP: 002e.4 (ITE IT8712F Super I/O) PNP: 002e.5 (ITE IT8712F Super I/O) PNP: 002e.6 (ITE IT8712F Super I/O) PNP: 002e.7 (ITE IT8712F Super I/O) PNP: 002e.8 (ITE IT8712F Super I/O) PNP: 002e.9 (ITE IT8712F Super I/O) PNP: 002e.a (ITE IT8712F Super I/O) PCI: 00:12.0 (VIA VT8237R Southbridge) PCI: 00:13.0 (VIA VT8237R Southbridge) PCI: 00:01.0 (VIA VT8237R Southbridge) PCI: 00:13.1 (VIA VT8237R Southbridge) PCI: 00:06.0 (VIA VT8237R Southbridge) PCI: 00:07.0 (VIA VT8237R Southbridge) PCI: 00:18.1 (AMD K8 Northbridge) PCI: 00:18.2 (AMD K8 Northbridge) PCI: 00:18.3 (AMD K8 Northbridge) APIC: 01 () PCI: 00:00.1 () PCI: 00:00.2 () PCI: 00:00.3 () PCI: 00:00.4 () PCI: 00:00.6 () PCI: 00:00.7 () PCI: 00:03.0 () SMBIOS tables: 307 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 23f0 New low_table_end: 0x00000528 Now going to write high coreboot table at 0x1beec000 rom_table_end = 0x1beec000 Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0x1beec000 to 0x1bef0000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001bedffff: RAM 3. 000000001bee0000-000000001bffffff: CONFIGURATION TABLES 4. 000000001c000000-000000001fffffff: RESERVED 5. 00000000e0000000-00000000efffffff: RESERVED Wrote coreboot table at: 1beec000, 0x200 bytes, checksum 6c94 coreboot table: 536 bytes. Adding CBMEM entry as no. 5 Multiboot Information structure has been written. 0. FREE SPACE 1bff4000 0000c000 1. GDT 1bee0200 00000200 2. ACPI 1bee0400 0000b400 3. SMBIOS 1beeb800 00000800 4. COREBOOT 1beec000 00008000 5. ACPI RESUME1bef4000 00100000 CBFS: Looking for 'fallback/payload' CBFS: found. Got a payload CPU0: stack from 00140000 to 00148000:Lowest stack address 00147980 Loading segment from rom address 0xfffaac38 code (compression=1) New segment dstaddr 0xe6650 memsize 0x199b0 srcaddr 0xfffaac70 filesize 0xcf1d (cleaned up) New segment addr 0xe6650 size 0x199b0 offset 0xfffaac70 filesize 0xcf1d Loading segment from rom address 0xfffaac54 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e6650 memsz: 0x00000000000199b0 filesz: 0x000000000000cf1d lb: [0x0000000000100000, 0x0000000000188000) Post relocation: addr: 0x00000000000e6650 memsz: 0x00000000000199b0 filesz: 0x000000000000cf1d using LZMA [ 0x000e6650, 00100000, 0x00100000) <- fffaac70 dest 000e6650, end 00100000, bouncebuffer 1bdd0000 Loaded segments Jumping to boot code at fc32c entry = 0x000fc32c lb_start = 0x00100000 lb_size = 0x00088000 adjust = 0x1bd58000 buffer = 0x1bdd0000 elf_boot_notes = 0x00124a70 adjusted_boot_notes = 0x1be7ca70 Start bios (version rel-1.7.0-91-g7a39e72-20120828_170752-ruik) Found mainboard ASUS M2V-MX SE Ram Size=0x1bee0000 (0x0000000000000000 high) Relocating low data from 0x000e6f20 to 0x000ef790 (size 2156) Relocating init from 0x000e778c to 0x1bec6710 (size 38852) Found CBFS header at 0xfffffc00