>From 2b2bb6f161a9a1706c7017041b173efcd99845c3 Mon Sep 17 00:00:00 2001
From: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date: Mon, 14 Jan 2013 00:28:07 +0100
Subject: [PATCH 1/2] Changes for nc6320

Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
---
 src/mainboard/roda/rk886ex/Kconfig       |  2 +-
 src/mainboard/roda/rk886ex/devicetree.cb |  2 +-
 src/mainboard/roda/rk886ex/romstage.c    | 92 +++++++-------------------------
 3 files changed, 20 insertions(+), 76 deletions(-)

diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 84a8543..0095f4d 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_TI_PCI7420
-	select SUPERIO_SMSC_LPC47N227
+	select SUPERIO_SMSC_LPC47N217
 	select SUPERIO_RENESAS_M3885X
 	select EC_ACPI
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index aadba9d..955561a 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -83,7 +83,7 @@ chip northbridge/intel/i945
 			#device pci 1e.2 off end # AC'97 Audio
 			#device pci 1e.3 off end # AC'97 Modem
                         device pci 1f.0 on # LPC bridge
-                                chip superio/smsc/lpc47n227
+                                chip superio/smsc/lpc47n217
 					device pnp 2e.1 on # Parallel port
 						 io 0x60 = 0x378
 						irq 0x70 = 5
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index d75d33f..dd7984a 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -35,6 +35,7 @@
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
+#include "superio/smsc/lpc47n217/early_serial.c"
 #include "option_table.h"
 
 void setup_ich7_gpios(void)
@@ -68,82 +69,35 @@ void setup_ich7_gpios(void)
 
 static void ich7_enable_lpc(void)
 {
-	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
-	       lpt_en = 1<<2; // enable LPT
-	}
 	// Enable Serial IRQ
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x8);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
-	// Enable 0x02e0
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2001); //CNF2_LPC_EN| lpt_en);
+	// Enable 0x04e0
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x34e1);
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
 	// COM3 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
+	//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
 	// COM4 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
-}
-
-/* This box has two superios, so enabling serial becomes slightly excessive.
- * We disable a lot of stuff to make sure that there are no conflicts between
- * the two. Also set up the GPIOs from the beginning. This is the "no schematic
- * but safe anyways" method.
- */
-static inline void pnp_enter_ext_func_mode(device_t dev)
-{
-	unsigned int port = dev >> 8;
-	outb(0x55, port);
+	//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
 }
 
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	unsigned int port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void pnp_write_register(device_t dev, int reg, int val)
-{
-	unsigned int port = dev >> 8;
-	outb(reg, port);
-	outb(val, port+1);
-}
 
 static void early_superio_config(void)
 {
-	device_t dev;
-
-	dev=PNP_DEV(0x2e, 0x00);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
-	pnp_write_register(dev, 0x02, 0x88); // UART power on
-	pnp_write_register(dev, 0x03, 0x72); // Floppy
-	pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
-	pnp_write_register(dev, 0x14, 0x03); // Floppy
-	pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
-	pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
-	pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
-	pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
-	pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
-	pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
-	pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
-	/* These are the SMI status registers in the SIO: */
-	pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
-
-	pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
-	pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
-	pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
-	pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
-	pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
-	pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
-	pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
-	pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
-	pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
-
-	pnp_exit_ext_func_mode(dev);
+	/* Found SMSC LPC47N217 (id=0x7a, rev=0x01) at 0x4e */
+	device_t dev = PNP_DEV(0x4e, LPC47N217_SP1);
+	lpc47n217_enable_serial(dev, CONFIG_TTYS0_BASE);
+	uart_init();
+#if 0
+	outb(0x24, 0xcd6);
+	outb(0x1, 0xcd7);
+	outb(0xea, 0xcd6);
+	outb(0x1, 0xcd7);
+	*(u8 *)0xfed80101 = 0x98;
+#endif
 }
 
 static void rcba_config(void)
@@ -243,13 +197,6 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-static void init_artec_dongle(void)
-{
-	// Enable 4MB decoding
-	outb(0xf1, 0x88);
-	outb(0xf4, 0x88);
-}
-
 #include <cbmem.h>
 
 void main(unsigned long bist)
@@ -285,9 +232,6 @@ void main(unsigned long bist)
 	 */
 	i945_early_initialization();
 
-	/* This has to happen after i945_early_initialization() */
-	init_artec_dongle();
-
 	/* Read PM1_CNT */
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
-- 
1.8.1

