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<p class=MsoNormal>How do you do.<o:p></o:p></p>
<p class=MsoNormal>Thank you for your effort for supporting coreboot.<o:p></o:p></p>
<p class=MsoNormal>I saw your patch to coreboot for LGA775 soket.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>I 'm porting Coreboot to Gigabyte GA-945GCM board(LGA775
socket, i945GC northbridge).<o:p></o:p></p>
<p class=MsoNormal>In my view, Coreboot does not support LGA775 perfectly.<o:p></o:p></p>
<p class=MsoNormal>Coreboot seems to have several problems with LGA775.<o:p></o:p></p>
<p class=MsoNormal>In my case, when it calls wbinvd on "smm_init"
function(southbridge/intel/i82801gx/smi.c: Line352),<o:p></o:p></p>
<p class=MsoNormal>, system goes away.<o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>Here is the log:<o:p></o:p></p>
<p class=MsoPlainText>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><o:p> </o:p></p>
<p class=MsoPlainText>...<o:p></o:p></p>
<p class=MsoPlainText>PCI: 00:1f.3 cmd <- 101<o:p></o:p></p>
<p class=MsoPlainText>PCI: 02:00.0 cmd <- 03<o:p></o:p></p>
<p class=MsoPlainText>done.<o:p></o:p></p>
<p class=MsoPlainText>Initializing devices...<o:p></o:p></p>
<p class=MsoPlainText>Root Device init<o:p></o:p></p>
<p class=MsoPlainText>CPU_CLUSTER: 0 init<o:p></o:p></p>
<p class=MsoPlainText>start_eip=0x00001000, code_size=0x00000031 <o:p></o:p></p>
<p class=MsoPlainText><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<o:p> </o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>When the code calls wbinvd(), it stops. So, I skipped the
calls of wbinvd() or calls of disable_cache().<o:p></o:p></p>
<p class=MsoPlainText>Then it go out more. But it also stops on [SMM-1].<o:p></o:p></p>
<p class=MsoPlainText>Here is the log:<o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><o:p> </o:p></p>
<p class=MsoPlainText>MTRR: Physical address space:<o:p></o:p></p>
<p class=MsoPlainText>0x0000000000000000 - 0x00000000000a0000 size 0x000a0000
type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007f800000 size 0x7f740000 type 6
0x000000007f800000 - 0x0000000100000000 size 0x80800000 type 0 call
enable_fixed_mtrr() CPU physical address size: 36 bits<o:p></o:p></p>
<p class=MsoPlainText>MTRR: default type WB/UC MTRR counts: 2/2.<o:p></o:p></p>
<p class=MsoPlainText>MTRR: UC selected as default type.<o:p></o:p></p>
<p class=MsoPlainText>MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000
type 6<o:p></o:p></p>
<p class=MsoPlainText>MTRR: 1 base 0x000000007f800000 mask 0x0000000fff800000
type 0<o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>MTRR check<o:p></o:p></p>
<p class=MsoPlainText>Fixed MTRRs : Enabled<o:p></o:p></p>
<p class=MsoPlainText>Variable MTRRs: Enabled<o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>Setting up local apic... apic_id: 0x00 done.<o:p></o:p></p>
<p class=MsoPlainText>CPU: 0 2 siblings<o:p></o:p></p>
<p class=MsoPlainText>memalign Enter, boundary 8, size 152, free_mem_ptr
0015ac70 memalign 0015ac70<o:p></o:p></p>
<p class=MsoPlainText>CPU: 0 has sibling 1<o:p></o:p></p>
<p class=MsoPlainText>CPU #0 initialized<o:p></o:p></p>
<p class=MsoPlainText>CPU1: stack_base 00158000, stack_end 00158ff8 Asserting
INIT.<o:p></o:p></p>
<p class=MsoPlainText>Waiting for send to finish...<o:p></o:p></p>
<p class=MsoPlainText>+Deasserting INIT.<o:p></o:p></p>
<p class=MsoPlainText>Waiting for send to finish...<o:p></o:p></p>
<p class=MsoPlainText>+#startup loops: 2.<o:p></o:p></p>
<p class=MsoPlainText>Sending STARTUP #1 to 1.<o:p></o:p></p>
<p class=MsoPlainText>After apic_write.<o:p></o:p></p>
<p class=MsoPlainText>[SMM-1]<o:p></o:p></p>
<p class=MsoPlainText><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<o:p> </o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Have you ever seen any board on which Coreboot works well?<o:p></o:p></p>
<p class=MsoNormal>If you have any idea, please contact me.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Thanks & regards.<o:p></o:p></p>
<p class=MsoNormal>Spcinc.<o:p></o:p></p>
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