<div dir="ltr"><div>> > If DDR3-667 works but AGESA fails at DDR3-1600, is it possible to go back<br>> > to DDR3-667 or try an intermediate speed, say DDR3-1333 ?<br>><br>> Maybe there is an option in AGESA where you can limit the maximum<br>
> frequency.<br>><br>> $ more src/mainboard/asus/f2a85-m/buildOpts.c<br>> […]<br>> #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY<br>> […]<br>> #define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY<br>
> […]<br><br></div><div>This is a great suggestion.<br><br>I have spent a few days studying the AGESA code to find out what frequencies it tries. I concluded that the built-in AGESA autodetection is very limited. It may be there is a bug in the AGESA autodetection because this is not the same code path generally used in vendor BIOSes. The error messages about missing tables are suspicious. I believe it means AMD has the motherboard OEM (i.e. Asus) provide parameter tables measured with a scope that help the timings match the production board.<br>
<br>Specifically I added IDS_HDT_CONSOLE (MEM_FLOW, "MemPPSCFlow enter " __FILE__ ":%d\n", __LINE__); and IDS_HDT_CONSOLE (MEM_FLOW, "MemPPSCFlow exit " __FILE__ ":%d\n", __LINE__); to the function MemPPSCFlow() in src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c<br>
</div><div><br><br></div><div><br></div><div>I attempted setting BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT and BLDCFG_MEMORY_CLOCK_SELECT:<br>diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c<br>
index 7f893f9..b9346b7 100644<br>--- a/src/mainboard/asus/f2a85-m/buildOpts.c<br>+++ b/src/mainboard/asus/f2a85-m/buildOpts.c<br>@@ -102,7 +102,7 @@<br> <br> #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE<br>
<br>-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY<br>+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY<br> #define BLDCFG_MEMORY_MODE_UNGANGED TRUE<br> #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE<br>
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED<br>@@ -116,8 +116,8 @@<br> #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT<br> #define BLDCFG_ONLINE_SPARE FALSE<br>
#define BLDCFG_BANK_SWIZZLE TRUE<br>-#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO<br>-#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY<br>+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_LIMITED<br>
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY<br> #define BLDCFG_DQS_TRAINING_CONTROL TRUE<br> #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE<br> #define BLDCFG_USE_BURST_MODE FALSE<br>
<br></div><div>I then ran make clean; make and tried booting coreboot, but hit the same error (ASSERTION FAILED mmExcludeDimm.c line 26). I'm going to keep trying lower speeds.<br></div><div><br></div><div>I also attemped configuring coreboot with 1.65V though my memory is only rated to 1.60V. I checked with the vendor BIOS that the memory is at least bootable at 1.65V. Then I tried booting coreboot at 1.65V (without the previous memory bus limit), but it stopped at the same assertion.<br>
</div><div><div><br><br>> Could you try to find out with `bios_extract` for example what AGESA<br>> version the vendor BIOS uses.<br><br></div><div>I have not had time to run bios_extract but I did identify that the BIOS file supplied on Asus' website for the F2A85-M/CSM is identical to the data on the chip after stripping the first 2048 bytes. For example:<br>
<br></div><div>dd if=f2a85-m-asus-5103-2012.09.10.v2.10.1208.cap of=f2a85-flashrom.bin bs=2048 skip=1<br></div><div><br><br>> PS: David, Google Mail changed the compose interface and they send HTML<br>> message in addition to text by default. Could you change that to just<br>
> plain text please [3][4]?<br><br></div>I think this is now plain-text only, please let me know if gmail sends it as HTML. Sorry!<br></div><br></div>