commit 1177b31252883f5b287617bb7ef5d892324cf8e1
Author: Böszörményi Zoltán <zb@cybertec.at>
Date:   Sun May 26 17:04:03 2013 +0200

    Add AMD SC3200 support to src/superio.

diff --git a/src/superio/Kconfig b/src/superio/Kconfig
index 32e60bb..630f083 100644
--- a/src/superio/Kconfig
+++ b/src/superio/Kconfig
@@ -20,6 +20,7 @@
 config SUPERIO_WANTS_14MHZ_CLOCK
 	bool
 
+source src/superio/amd/Kconfig
 source src/superio/fintek/Kconfig
 source src/superio/intel/Kconfig
 source src/superio/ite/Kconfig
diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc
index ff4d48f..26f93cf 100644
--- a/src/superio/Makefile.inc
+++ b/src/superio/Makefile.inc
@@ -17,6 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+subdirs-y += amd
 subdirs-y += fintek
 subdirs-y += intel
 subdirs-y += ite
diff --git a/src/superio/amd/Kconfig b/src/superio/amd/Kconfig
new file mode 100644
index 0000000..1ab22e7
--- /dev/null
+++ b/src/superio/amd/Kconfig
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Zoltán Böszörményi
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+
+config SUPERIO_AMD_SC3200
+	bool
diff --git a/src/superio/amd/Makefile.inc b/src/superio/amd/Makefile.inc
new file mode 100644
index 0000000..215b221
--- /dev/null
+++ b/src/superio/amd/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Zoltán Böszörményi
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-y += sc3200
diff --git a/src/superio/amd/sc3200/Makefile.inc b/src/superio/amd/sc3200/Makefile.inc
new file mode 100644
index 0000000..5ecf768
--- /dev/null
+++ b/src/superio/amd/sc3200/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Zoltán Böszörményi <zboszormenyi@sicom.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_AMD_SC3200) += superio.c
diff --git a/src/superio/amd/sc3200/early_init.c b/src/superio/amd/sc3200/early_init.c
new file mode 100644
index 0000000..6ea3db7
--- /dev/null
+++ b/src/superio/amd/sc3200/early_init.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Zoltán Böszörményi <zboszormenyi@sicom.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "sc3200.h"
+
+static void sc3200_disable_dev(device_t dev)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+}
+
+static void sc3200_enable_dev(device_t dev, u16 iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}
diff --git a/src/superio/amd/sc3200/early_serial.c b/src/superio/amd/sc3200/early_serial.c
new file mode 100644
index 0000000..f884cf9
--- /dev/null
+++ b/src/superio/amd/sc3200/early_serial.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Zoltán Böszörményi <zboszormenyi@sicom.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "sc3200.h"
+
+void sc3200_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}
+
+void sc3200_enable_dev(device_t dev)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 1);
+}
diff --git a/src/superio/amd/sc3200/sc3200.h b/src/superio/amd/sc3200/sc3200.h
new file mode 100644
index 0000000..a1838d0
--- /dev/null
+++ b/src/superio/amd/sc3200/sc3200.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Zoltán Böszörményi <zboszormenyi@sicom.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_AMD_SC3200_SC3200_H
+#define SUPERIO_AMD_SC3200_SC3200_H
+
+#define SC3200_RTC	0x00 /* RTC */
+#define SC3200_SWC	0x01 /* System Wake-Up Controller (SWC) */
+#define SC3200_SP3	0x02 /* Com3/IR */
+#define SC3200_SP1	0x03 /* Com1 */
+#define SC3200_ACB1	0x05 /* ACCESS.bus 1 */
+#define SC3200_ACB2	0x06 /* ACCESS.bus 2 */
+#define SC3200_PP	0x07 /* Parallel Port */
+#define SC3200_SP2	0x08 /* Com2 */
+
+#if defined(__PRE_RAM__)
+void sc3200_enable_serial(device_t dev, u16 iobase);
+void sc3200_enable_dev(device_t dev);
+#endif
+
+#endif
diff --git a/src/superio/amd/sc3200/superio.c b/src/superio/amd/sc3200/superio.c
new file mode 100644
index 0000000..70de2c2
--- /dev/null
+++ b/src/superio/amd/sc3200/superio.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Zoltán Böszörményi <zboszormenyi@sicom.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <uart8250.h>
+#include <stdlib.h>
+#include "sc3200.h"
+
+static void init(device_t dev)
+{
+	if (!dev->enabled)
+		return;
+
+	/* No KBC in this chip */
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, SC3200_RTC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0,  {0x07fe, 0}, {0x7fe, 0}, },
+	{ &ops, SC3200_SWC,  PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+	{ &ops, SC3200_SP3,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, SC3200_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, SC3200_ACB1, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
+	{ &ops, SC3200_ACB2, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
+	{ &ops, SC3200_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x03f8, 0}, },
+	{ &ops, SC3200_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_amd_sc3200_ops = {
+	CHIP_NAME("AMD SC3200 Super I/O")
+	.enable_dev = enable_dev,
+};
