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<TITLE>fwts log</TITLE>
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<TR><TD class=style_heading COLSPAN=2>Firmware Test Suite</TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Results generated by fwts: Version V0.26.03 (Thu Dec 20 16:46:56 CST 2012).</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Some of this work - Copyright (c) 1999 - 2010, Intel Corp. All rights reserved.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Some of this work - Copyright (c) 2010 - 2012, Canonical.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>This test run on 06/11/13 at 19:32:24 on host Linux ubuntu 3.5.0-22-generic #34-Ubuntu SMP Fri Jan 11 16:51:23 UTC 2013 i686.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Running tests: version bios_info oops mtrr acpiinfo klog csm microcode msr nx cpufreq maxfreq virt maxreadreq crs aspm hpet_check dmi_decode smbios pnp pciirq mpcheck os2gap hda_audio bios32 ebda pcc wmi osilinux apicedge method mcfg fan fadt dmar cstates checksum apicinstance acpitables syntaxcheck wakealarm.</TD>
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<TD COLSPAN=2 class=style_heading>Gather kernel system information.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 3: Gather kernel signature.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Signature: Ubuntu 3.5.0-22.34-generic 3.5.7.2</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 3: Gather kernel system information.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Kernel Version: Linux version 3.5.0-22-generic (buildd@gumiho) (gcc version 4.6.1 (Ubuntu/Linaro 4.6.1-9ubuntu3) ) #34-Ubuntu SMP Fri Jan 11 16:51:23 UTC 2013</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 3 of 3: Gather APCI driver version.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>ACPI Version: 20120320</TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 3 info only.</TD>
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<TD COLSPAN=2 class=style_heading>Gather BIOS DMI information.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Gather BIOS DMI information</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>BIOS Vendor : coreboot</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>BIOS Version : 4.0-4746-gd0299e4-dirty</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>BIOS Release Date : 11/04/2013</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Chassis Serial # : </PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Chassis Type : 3</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Chassis Vendor : Abit</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Chassis Version : </PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Chassic Asset Tag : </PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Product Name : BF6</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Product Serial # : 123456789</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Product Version : 1.0</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>System Vendor : Abit</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 1 info only.</TD>
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<TD COLSPAN=2 class=style_heading>Scan kernel log for Oopses.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Kernel log oops check.</TD>
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<TD class=style_passed>PASSED</TD><TD>Found no oopses in kernel log.</TD>
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<TD class=style_passed>PASSED</TD><TD>Found no WARN_ON warnings in kernel log.</TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>2 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
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<TD COLSPAN=2 class=style_heading>MTRR validation.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>MTRR overview</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>-------------</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Reg 0: 0x0000000000000000 - 0x0000000008000000 ( 128 MB) Write-Back</PRE></TD>
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<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>Reg 1: 0x0000000008000000 - 0x000000000a000000 ( 32 MB) Write-Back</PRE></TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 3: Validate the kernel MTRR IOMEM setup.</TD>
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<TD class=style_passed>PASSED</TD><TD>Memory ranges seem to have correct attributes.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 3: Validate the MTRR setup across all processors.</TD>
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<TD class=style_passed>PASSED</TD><TD>All processors have the a consistent MTRR setup.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 3 of 3: Check for AMD MtrrFixDramModEn being cleared by the BIOS.</TD>
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<TD class=style_skipped>Skipped</TD><TD>CPU is not an AMD, cannot test.</TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>2 passed, 0 failed, 0 warnings, 0 aborted, 1 skipped, 0 info only.</TD>
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<TD COLSPAN=2 class=style_heading>General ACPI information check.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 3: Determine Kernel ACPI version.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Kernel ACPICA driver version: 20120320, supports ACPI 5.0</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 3: Determine machines ACPI version.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 3 of 3: Determine AML compiler.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Determine the compiler used to generate the ACPI AML in the DSDT and SSDT.</TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 2 info only.</TD>
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<TD COLSPAN=2 class=style_heading>Scan kernel log for errors and warnings.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Kernel log error check.</TD>
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<TD class=style_high>FAILED [HIGH]</TD>
<TD>HIGH Kernel message: [ 0.202309] PnPBIOS: Disabled by ACPI PNP</TD>
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<TD class=style_advice>Advice</TD><TD COLSPAN=2 class=style_advice_info>The PnPBIOS driver has detected an issue that fwts does not know about.</TD>
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<TD class=style_high>FAILED [HIGH]</TD>
<TD>HIGH Kernel message: [ 0.253215] ACPI: PCI Interrupt Link [LNKB] disabled and referenced, BIOS bug</TD>
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<TD class=style_advice>Advice</TD><TD COLSPAN=2 class=style_advice_info>A PCI interrupt link could not be enabled when the associated ACPI _STA control was executed. It will be disabled. This is normally a bug in the _STA control for this link.</TD>
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<TD class=style_high>FAILED [HIGH]</TD>
<TD>HIGH Kernel message: [ 0.308430] ACPI: PCI Interrupt Link [LNKC] disabled and referenced, BIOS bug</TD>
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<TD class=style_advice>Advice</TD><TD COLSPAN=2 class=style_advice_info>A PCI interrupt link could not be enabled when the associated ACPI _STA control was executed. It will be disabled. This is normally a bug in the _STA control for this link.</TD>
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<TD class=style_high>FAILED [HIGH]</TD>
<TD>HIGH Kernel message: [ 0.364392] ACPI: PCI Interrupt Link [LNKD] disabled and referenced, BIOS bug</TD>
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<TD class=style_advice>Advice</TD><TD COLSPAN=2 class=style_advice_info>A PCI interrupt link could not be enabled when the associated ACPI _STA control was executed. It will be disabled. This is normally a bug in the _STA control for this link.</TD>
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<TD class=style_critical>FAILED [CRITICAL]</TD>
<TD>CRITICAL Kernel message: [ 13.857733] Disabling IRQ #11</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Message repeated 1 times.</TD>
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<TD class=style_advice>Advice</TD><TD COLSPAN=2 class=style_advice_info>The kernel detected an irq storm. This is most probably an IRQ routing bug.</TD>
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<TD class=style_critical>FAILED [CRITICAL]</TD>
<TD>CRITICAL Kernel message: [ 15.959385] Disabling IRQ #10</TD>
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<TD class=style_advice>Advice</TD><TD COLSPAN=2 class=style_advice_info>The kernel detected an irq storm. This is most probably an IRQ routing bug.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Found 6 unique errors in kernel log.</TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 6 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
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<TD COLSPAN=2 class=style_heading>Check for UEFI Compatibility Support Module.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check for UEFI Compatibility Support Module.</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Checking for UEFI Compatibility Support Module (CSM)</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>Int 10h jumps to 0xc41a9 in option ROM at: 0xc0000..0xca000</TD>
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<TD></TD><TD COLSPAN=2 class=style_infos>No CSM: Legacy BIOS firmware has video option ROM with Int 10h support.</TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 1 info only.</TD>
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<TD COLSPAN=2 class=style_heading>Check if system is using latest microcode.</TD>
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<TD class=style_error>Error</TD><TD COLSPAN=2>Cannot read microcode file /usr/share/misc/intel-microcode.dat.</TD>
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<TD class=style_error>Error</TD><TD COLSPAN=2>Aborted test, initialisation failed.</TD>
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<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 1 aborted, 0 skipped, 0 info only.</TD>
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<TD COLSPAN=2 class=style_heading>MSR register tests.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 5: Check CPU generic MSRs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR P5_MC_TYPE (0x1) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR PLATFORM_ID (0x17) (mask:1c000000000000) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR EBL_CR_POWERON (0x2a) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR APIC_BASE (0x1b) (mask:fffffffffffffeff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR BIOS_SIGN_ID (0x8b) (mask:ffffffff00000000) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRRCAP (0xfe) (mask:fff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR SYSENTER_CS (0x174) (mask:ffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR SYSENTER_ESP (0x175) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR SYSENTER_EIP (0x176) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MCG_CAP (0x179) (mask:1ff0fff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MCG_STATUS (0x17a) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE0 (0x200) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK0 (0x201) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE1 (0x202) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK1 (0x203) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE2 (0x204) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK2 (0x205) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE3 (0x206) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK3 (0x207) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE4 (0x208) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK4 (0x209) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE5 (0x20a) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK5 (0x20b) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE6 (0x20c) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK6 (0x20d) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSBASE7 (0x20e) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_PHYSMASK7 (0x20f) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX64K_000 (0x250) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX16K_800 (0x258) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX16K_a00 (0x259) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
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<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_C000 (0x268) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_C800 (0x269) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_D000 (0x26a) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_D800 (0x26b) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_E000 (0x26c) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_E800 (0x26d) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_F000 (0x26e) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_FIX4K_F800 (0x26f) (mask:ffffffffffffffff) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR PAT (0x277) (mask:707070707070703) was consistent across 1 CPUs.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>MSR MTRR_DEF_TYPE (0x2ff) (mask:c0f) was consistent across 1 CPUs.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 5: Check CPU specific model MSRs.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>No model specific tests for model 0x7.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 3 of 5: Check all P State Ratios.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 4 of 5: Check C1 and C3 autodemotion.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 5 of 5: Check SMRR MSR registers.</TD>
</TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>SMRR not supported by this CPU.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>40 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
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<TD COLSPAN=2 class=style_heading>Test if CPU NX is disabled by the BIOS.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
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<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 3: Check CPU NX capability.</TD>
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<TD class=style_passed>PASSED</TD><TD>The CPU is family 6, model 7 and does not have NX capabilities.</TD>
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<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 3: Check all CPUs have same BIOS set NX flag.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test verifies that all CPUs have the same NX flag setting. Although rare, BIOS may set the NX flag differently per CPU. </TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Only one CPU, no need to run test.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 3 of 3: Check all CPUs have same msr setting in MSR 0x1a0.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test verifies that all CPUs have the same NX flag setting by examining the per CPU MSR register 0x1a0.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Cannot read msr 0x1a0 on CPU0</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>CPU frequency scaling tests (takes ~1-2 mins).</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: CPU P-State Checks.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>For each processor in the system, this test steps through the various frequency states (P-states) that the BIOS advertises for the processor. For each processor/frequency combination, a quick performance value is measured. The test then validates that:</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> 1) Each processor has the same number of frequency states
2) Higher advertised frequencies have a higher performance
3) No duplicate frequency values are reported by the BIOS
4) Is BIOS wrongly doing Sw_All P-state coordination across cores
5) Is BIOS wrongly doing Sw_Any P-state coordination across cores
</PRE></TD>
</TR>
<TR>
<TD class=style_error>Warning</TD><TD COLSPAN=2 class=style_advice_info>Frequency scaling not supported.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check max CPU frequencies against max scaling frequency.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Maximum CPU frequency check.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test checks the maximum CPU frequency as detected by the kernel for each CPU against maxiumum frequency as specified by the BIOS frequency scaling settings.</TD>
</TR>
<TR>
<TD class=style_skipped>Skipped</TD><TD>Cannot read CPU frequencies from /proc/cpuinfo, this generally happens on AMD CPUs, skipping test.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 1 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Test CPU Virtualisation Configuration.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check CPU Virtualisation Configuration.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Check VT/VMX Virtualization extensions are set up correctly.</TD>
</TR>
<TR>
<TD class=style_skipped>Skipped</TD><TD>Processor does not support Virtualization extensions, won't test BIOS configuration, skipping test.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 1 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Checks firmware has set PCI Express MaxReadReq to a higher value on non-motherboard devices.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check firmware settings MaxReadReq for PCI Express devices.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>All devices have MaxReadReq set > 128.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check PCI host bridge configuration using _CRS.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check PCI host bridge configuration using _CRS.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>The kernel has detected a BIOS newer than the end of 2007 (11/4/2013) and has assumed that your BIOS can correctly specify the host bridge MMIO aperture using _CRS. If this does not work correctly you can override this by booting with "pci=nocrs".</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>PCIe ASPM check.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 2: PCIe ASPM ACPI test.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>No valid FACP information present: cannot test ASPM.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 2: PCIe ASPM registers test.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>PCIe ASPM setting matched was matched.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>HPET configuration test.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 3: Check HPET base in kernel log.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test checks the HPET PCI BAR for each timer block in the timer. The base address is passed by the firmware via an ACPI table. IRQ routing and initialization is also verified by the test.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>No base address found for HPET.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 3: Sanity check HPET configuration.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test skipped because previous test failed.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 3 of 3: Check HPET base in DSDT and/or SSDT. </TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Test DMI/SMBIOS tables for errors.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Test DMI/SMBIOS tables for errors.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Entry @ 0x09fec820 'BIOS Information (Type 0)'</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Entry @ 0x09fec865 'System Information (Type 1)'</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Entry @ 0x09fec898 'Chassis Information (Type 3)'</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Entry @ 0x09fec8b3 'Processor Information (Type 4)'</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Entry @ 0x09fec902 'System Boot Information (Type 32)'</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Entry @ 0x09fec90f 'End of Table (Type 127)'</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>6 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check SMBIOS.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Find and Check SMBIOS Table Entry Point.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test tries to find and sanity check the SMBIOS data structures.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Found SMBIOS Table Entry Point at 0xfdb00</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code>SMBIOS Entry Point Structure:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Anchor String : _SM_</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Checksum : 0x62</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Entry Point Length : 0x1f</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Major Version : 0x02</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Minor Version : 0x07</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Maximum Struct Size : 0x18</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Entry Point Revision : 0x00</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Formatted Area : 0x00 0x00 0x00 0x00 0x00</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Intermediate Anchor : _DMI_</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Intermediate Checksum : 0x7e</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Structure Table Length : 0x00f5</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Structure Table Address: 0x09fec820</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> # of SMBIOS Structures : 0x0006</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> SBMIOS BCD Revision : 00</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> BCD Revision 00 indicates compliance with specification stated in Major/Minor Version.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check BIOS Support Installation structure.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check PnP BIOS Support Installation structure.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test tries to find and sanity check the Plug and Play BIOS Support Installation Check structure. </TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Found PnP Installation Check structure at 0x000fd070</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Signature : $PnP</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Version : 0x10 (1.0)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Length : 0x0021 bytes</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Control Field : 0x0000 (Not supported)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Event Notification Flag Address : 0x00000000 (undefined)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Real Mode 16 bit Code Address : 0xf000:c6b4</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Real Mode 16 bit Data Address : 0xf000:0000</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> 16 bit Protected Mode Code Address : 0x000fc6b0</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> 16 bit Protected Mode Data Address : 0x000f0000</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> OEM Device Identifier : 0x00000000 (undefined)</PRE></TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Version 1.0 detected.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>PnP Installation Check structure is the correct length of 33 bytes.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>2 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check PCI IRQ Routing Table.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: PCI IRQ Routing Table.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test tries to find and sanity check the PCI IRQ Routing Table, as defined by http://www.microsoft.com/taiwan/whdc/archive/pciirq.mspx and described in pages 233-238 of PCI System Architecture, Fourth Edition, Mindshare, Inc. (1999). NOTE: The PCI IRQ Routing Table only really knows about ISA IRQs and is generally not used with APIC. </TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Found PCI IRQ Routing Table at 0x000fdb40</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Signature : $PIR</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Version : 0x0100 (1.0)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Table Size : 0x00b0 bytes (9 slot entries)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> PCI Router ID : 00:07.0</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> PCI Exclusive IRQs : 0x0e00 (9 10 11)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Compatible PCI Router : 8086:7000</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Miniport Data : 0x00000000 (none)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Reserved : 0x00,00,00,00,00,00,00,00,00,00,00</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Checksum : 0x7a</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 0:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:13, Slot Number : 0x01</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 1:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:11, Slot Number : 0x02</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 2:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:0f, Slot Number : 0x03</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 3:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:0d, Slot Number : 0x04</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 4:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:0b, Slot Number : 0x05</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 5:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:09, Slot Number : 0x06</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 6:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:08, Slot Number : 0x07</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 7:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:07, Slot Number : 0x00 (on-board)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Slot Entry 8:</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> ID: 00:01, Slot Number : 0x00 (on-board)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTA# Link Value : 0x60, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTB# Link Value : 0x61, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTC# Link Value : 0x62, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> INTD# Link Value : 0x63, IRQ Bitmap 0xdeb8 (3 4 5 7 9 10 11 12 14 15)</PRE></TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>The Compatible PCI Interrupt Router is defined.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Table size was correct for 9 slot entries.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Reserved region is set to zero.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>All 9 slots have sane looking link and IRQ bitmaps.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>4 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check MultiProcessor Tables.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Failed to get _MP_ data from firmware.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 9 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>OS/2 memory hole test.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check the OS/2 15Mb memory hole is absent.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>No OS/2 memory hole found.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check HDA Audio Pin Configs.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check HDA Audio Pin Configs.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check BIOS32 Service Directory.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check BIOS32 Service Directory.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test tries to find and sanity check the BIOS32 Service Directory as defined in the Standard BIOS 32-bit Service Directory Proposal, Revision 0.4 May 24, 1993, Phoenix Technologies Ltd and also the PCI BIOS specification.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Found BIOS32 Service Directory at 0x000fd040</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Signature : _32_</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Entry Point: 0x000fc789</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Revsion : 0x00</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Length : 0x01</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos><PRE class=style_code> Checksum : 0x7d</PRE></TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Service Directory Entry Point 0x000fc789 is not in high memory.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Service Directory Length is 1 (1 x 16 bytes) as expected.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Service Directory Revision is 0x00 and is supported by the kernel.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Service Directory checksum passed.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>4 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Validate EBDA region is mapped and reserved in memory map table.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check EBDA is reserved in E820 table.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>The Extended BIOS Data Area (EBDA) is normally located at the end of the low 640K region and is typically 2-4K in size. It should be reserved in the Int 15 AX=E820 BIOS memory map table.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>EBDA region mapped at 0x9fc00 and reserved as a 0K region in the Int 15 AX=E820 BIOS memory map table at 0x9fc00..0x9ffff.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Processor Clocking Control (PCC) Test.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Aborted test, initialisation failed.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 1 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Extract and analyse Windows Management Instrumentation (WMI).</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 2: Check Windows Management Instrumentation in DSDT</TD>
</TR>
<TR>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 2: Check Windows Management Instrumentation in SSDT</TD>
</TR>
<TR>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 2 aborted, 0 skipped, 2 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Disassemble DSDT to check for _OSI("Linux").</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Disassemble DSDT to check for _OSI("Linux").</TD>
</TR>
<TR>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 1 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>APIC Edge/Level Check.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Legacy and PCI Interrupt Edge/Level trigger checks.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 0 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 1 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 2 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 4 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 6 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 8 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 10 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 11 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 12 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD class=style_medium>FAILED [MEDIUM]</TD>
<TD>Non-Legacy interrupt 14 is incorrectly level triggered.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 10 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>ACPI DSDT Method Semantic Tests.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Cannot initialise ACPI.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Aborted test, initialisation failed.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 139 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>MCFG PCI Express* memory mapped config space.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Cannot load ACPI table</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Aborted test, initialisation failed.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 2 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Simple Fan Tests.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 2: Check fan status.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test how many fans there are in the system. Check for the current status of the fan(s).</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Fan cooling_device0 of type Processor has max cooling state 7 and current cooling state 0.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 2: Load system, check CPU fan status.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test how many fans there are in the system. Check for the current status of the fan(s).</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Loading CPUs for 20 seconds to try and get fan speeds to change.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Fan cooling_device0 current state did not change from value 0 while CPUs were busy.</TD>
</TR>
<TR>
<TD class=style_advice>Advice</TD><TD COLSPAN=2 class=style_advice_info>Did not detect any change in the CPU related thermal cooling device states. It could be that the devices are returning static information back to the driver and/or the fan speed is automatically being controlled by firmware using System Management Mode in which case the kernel interfaces being examined may not work anyway.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>FADT SCI_EN enabled check.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Cannot read ACPI table FACP.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Aborted test, initialisation failed.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 1 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check sane DMA Remapping (VT-d).</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check DMA Remapping.</TD>
</TR>
<TR>
<TD class=style_error>Error</TD><TD COLSPAN=2>Cannot load ACPI table.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check processor C state support.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check all CPUs C-states.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>This test checks if all processors have the same number of C-states, if the C-state counter works and if C-state transitions happen.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>Processor 0 has reached all C-states: </TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>1 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check ACPI table checksum.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check ACPI table checksums.</TD>
</TR>
<TR>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 1 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Check for single instance of APIC/MADT table.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check single instance of APIC/MADT table.</TD>
</TR>
<TR>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 1 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>ACPI table settings sanity checks.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 1: Check ACPI tables.</TD>
</TR>
<TR>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 1 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Re-assemble DSDT and find syntax errors and warnings.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 2: Disassemble and reassemble DSDT</TD>
</TR>
<TR>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 2: Disassemble and reassemble SSDT</TD>
</TR>
<TR>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>0 passed, 0 failed, 0 warnings, 2 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR>
<TD COLSPAN=2 class=style_heading>Test ACPI Wakealarm.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 1 of 4: Check existence of /sys/class/rtc/rtc0/wakealarm.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>/sys/class/rtc/rtc0/wakealarm found.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 2 of 4: Trigger wakealarm for 1 seconds in the future.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Trigger wakealarm for 1 seconds in the future.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>RTC wakealarm was triggered successfully.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 3 of 4: Check if wakealarm is fired.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>RTC wakealarm triggered and fired successfully.</TD>
</TR>
<TR><TD class=style_subtest COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Test 4 of 4: Multiple wakealarm firing tests.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Trigger wakealarm for 1 seconds in the future.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Trigger wakealarm for 2 seconds in the future.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Trigger wakealarm for 3 seconds in the future.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_infos>Trigger wakealarm for 4 seconds in the future.</TD>
</TR>
<TR>
<TD class=style_passed>PASSED</TD><TD>RTC wakealarm triggered and fired successfully.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>4 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.</TD>
</TR>
<TR><TD class=style_heading COLSPAN=2>Summary</TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>73 passed, 16 failed, 0 warnings, 152 aborted, 12 skipped, 9 info only.</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>Test Failure Summary</TD>
</TR>
<TR><TD class=style_heading COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>Critical failures: 2</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> klog: CRITICAL Kernel message: [ 13.857733] Disabling IRQ #11</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> klog: CRITICAL Kernel message: [ 15.959385] Disabling IRQ #10</PRE></TD>
</TR>
<TR><TD class=style_heading COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>High failures: 4</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> klog: HIGH Kernel message: [ 0.202309] PnPBIOS: Disabled by ACPI PNP</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> klog: HIGH Kernel message: [ 0.253215] ACPI: PCI Interrupt Link [LNKB] disabled and referenced, BIOS bug</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> klog: HIGH Kernel message: [ 0.308430] ACPI: PCI Interrupt Link [LNKC] disabled and referenced, BIOS bug</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> klog: HIGH Kernel message: [ 0.364392] ACPI: PCI Interrupt Link [LNKD] disabled and referenced, BIOS bug</PRE></TD>
</TR>
<TR><TD class=style_heading COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>Medium failures: 10</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 0 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 1 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 2 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 4 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 6 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 8 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 10 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 11 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 12 is incorrectly level triggered.</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code> apicedge: Non-Legacy interrupt 14 is incorrectly level triggered.</PRE></TD>
</TR>
<TR><TD class=style_heading COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>Low failures: NONE</TD>
</TR>
<TR><TD class=style_heading COLSPAN=2></TD></TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary>Other failures: NONE</TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>Test |Pass |Fail |Abort|Warn |Skip |Info |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>---------------+-----+-----+-----+-----+-----+-----+</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>acpiinfo | | | | | | 2|</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>acpitables | | | 1| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>apicedge | | 10| | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>apicinstance | | | 1| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>aspm | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>bios32 | 4| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>bios_info | | | | | | 1|</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>checksum | | | 1| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>cpufreq | | | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>crs | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>csm | | | | | | 1|</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>cstates | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>dmar | | | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>dmi_decode | 6| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>ebda | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>fadt | | | 1| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>fan | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>hda_audio | | | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>hpet_check | | | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>klog | | 6| | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>maxfreq | | | | | 1| |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>maxreadreq | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>mcfg | | | 2| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>method | | | 139| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>microcode | | | 1| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>mpcheck | | | | | 9| |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>msr | 40| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>mtrr | 2| | | | 1| |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>nx | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>oops | 2| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>os2gap | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>osilinux | | | 1| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>pcc | | | 1| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>pciirq | 4| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>pnp | 2| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>smbios | 1| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>syntaxcheck | | | 2| | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>version | | | | | | 3|</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>virt | | | | | 1| |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>wakealarm | 4| | | | | |</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>wmi | | | 2| | | 2|</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>---------------+-----+-----+-----+-----+-----+-----+</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>Total: | 73| 16| 152| 0| 12| 9|</PRE></TD>
</TR>
<TR>
<TD></TD><TD COLSPAN=2 class=style_summary><PRE class=style_code>---------------+-----+-----+-----+-----+-----+-----+</PRE></TD>
</TR>
</TABLE>
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