<div dir="ltr">Hi Zoran,<div><br></div><div style><br></div><div style><br></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Thu, Dec 5, 2013 at 7:44 AM, Stojsavljevic, Zoran <span dir="ltr"><<a href="mailto:zoran.stojsavljevic@intel.com" target="_blank">zoran.stojsavljevic@intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Hello,<br>
<br>
I just noticed new patches/drops into Coreboot (Cougar Canyon 2 board added). I did take git snapshot, and tried to see few things (what was added there). Talking about snapshot v4.0-4966 .<br>
<br>
It seems that Emerald Lake 2 (EL2) and Cougar Canyon 2 (CC2) support two slightly different concepts. I switched from EL2 to CC2 (since I have EL2 and CC2 here in lab, but only tried EL2 board with CC2 FSP context).<br>
</blockquote><div><br></div><div>Thanks for the report. Yes EL2 uses a mrc/systemagent binary contributed by Google. CC2 uses the FSP from Intel (and Sage). The FSP is new and we are still working on making the coreboot side of the interface better.</div>
<div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<br>
I needed to have 10+ adaptation building for CC2, and in this process I noticed the following:<br>
[1] CC2 has several parameters hard coded (in <chipset>);<br></blockquote><div style>Like? Send a patch.</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
[2] The new directory added: src/cpu/intel/fsp_model_206ax (there is already model_206ax);<br></blockquote><div> </div><div style> We would like to support both, but each binary has some different setup requirements and assumptions.</div>
<div style><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
[3] This directory is out of sync (does not compile), so I added IVB microcode patches files (microcode_m2xxx_000000yy.h) and modified microcode_blob.h file;<br></blockquote><div style>This should match the microcode the is available with the FSP. The date of current/best/working microcode is always an issue.</div>
<div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
[4] Added vbios (latest 2170.dat);<br>
[5] Did not noticed Management Engine (new concept for all other non-INTEL embedded folks, which suddenly popped up from nowhere) addendum (path) for CC2, which EL2 does have;<br></blockquote><div style><br></div><div style>
This is a chipset dependency. Even different versions of the chipset may require it or not.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
[6] Did not see/find descriptor.bin definition file and path definition (should be included somewhere);<br></blockquote><div style>Comes witht he FSP and/or you need to genterate it.</div><div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
[7] Used standard seabios from git as payload.<br>
<br>
And, yes, the whole Coreboot-v4.0-4966 does correctly compile with native gcc (NO cross-compiler) on my Fedora 18+ (Fedora 20) VM on my SNB DT:<br>
<br>
coreboot.rom: 8192 kB, bootblocksize 864, romsize 8388608, offset 0x400000<br>
alignment: 64 bytes<br>
<br>
Name Offset Type Size<br>
cmos_layout.bin 0x400000 cmos_layout 1164<br>
pci8086,0166.rom 0x4004c0 optionrom 65536<br>
cpu_microcode_blob.bin 0x410500 microcode 32832<br>
fallback/romstage 0x4185c0 stage 31082<br>
fallback/coreboot_ram 0x41ff80 stage 75924<br>
fallback/payload 0x432880 payload 55177<br>
config 0x440080 raw 4426<br>
pci8086,1502.rom 0x441200 raw 67584<br>
(empty) 0x451a40 null 3335512<br>
fsp.bin 0x77ffc0 (unknown) 393216<br>
(empty) 0x7e0000 null 130072<br>
<br>
Here is the question for thinking: both CC2 and EL2 choices should be unified, to reflect one steady procedure for INTEL FSP, right?<br></blockquote><div><br></div><div style>We are trying to figure that out, but there are currently different solutions for different needs.</div>
<div style> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
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I sent this email not in negative connotation, just trying to understand how better to approach Coreboot configuration procedure. Since there are more than few paths to be selected and IDF tool to be used to generate descriptor.bin .<br>
</blockquote><div><br></div><div style>We are working on some documentation, and some also comes with the FSP. </div><div style><br></div><div style><br></div><div style>Regards,</div><div style>Marc</div><div style><br>
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<div style> -- </div></div><a href="http://se-eng.com">http://se-eng.com</a>
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