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<div class="moz-cite-prefix">Hello Dave,<br>
<br>
From this link I found the set of PCI device IDs that AMD uses for
these chips<br>
on page 10:<br>
<br>
<a
href="http://support.amd.com/TechDocs/51810_16h_00h-0Fh_Rev_Guide.pdf">http://support.amd.com/TechDocs/51810_16h_00h-0Fh_Rev_Guide.pdf</a><br>
<br>
The choices are 0x9830 - 0x983A and 0x983D. Our IMB-A180 uses
9834.<br>
<br>
So I marched through the numbers and 0x9835 worked on the Display
Port<br>
that the new board supports.<br>
<br>
I should have tried your suggestion first. This is probably why
my wife<br>
tells me that I don't listen.<br>
;-)<br>
<br>
Anyway, thanks for your help! We now have debugging available on
the VGA.<br>
<br>
<font color="#ff0000">Now I have to find out why it does not
recognize boot media on the USB ports.<br>
It does see the keyboard though.</font><br>
<br>
<br>
Best regards,<br>
<br>
Mark Mason<br>
Engineering Design Team<br>
<br>
<br>
</div>
<blockquote
cite="mid:CAP5w7pn+nx1XkpfG46BCYSLtnvw7ejiCN3z8UYKDs0GA5keZ2w@mail.gmail.com"
type="cite">
<div dir="ltr">
<div>
<div>
<div>
<div>Mark,<br>
</div>
I captured a port 80 log from a design similar to the
IMB-a180 board and it looks identical.<br>
</div>
My guess (if what you are hoping to see is graphics output)
is that the graphics PCI ID doesn't<br>
</div>
match the vga bios ID. We normally let seabios load the video
bios. Maybe you could add some<br>
</div>
<div>code to dump out the graphics device ID for device 0:1.0.
On my system I get 1002:9835. The <br>
</div>
<div>
video bios rom image in CBFS would need that ID in it, or the
rom would need to be stored in<br>
CBFS in the generic "vgaroms/" folder (e.g.
vgaroms/my_vbios.rom).<br>
<br>
</div>
<div>Dave<br>
</div>
<div><br>
</div>
</div>
<div class="gmail_extra"><br>
<br>
<div class="gmail_quote">On Fri, May 30, 2014 at 1:50 PM, Kyösti
Mälkki <span dir="ltr"><<a moz-do-not-send="true"
href="mailto:kyosti.malkki@gmail.com" target="_blank">kyosti.malkki@gmail.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="">On 05/30/2014 09:19 PM, Mark C. Mason wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
We are bringing up a modified IMB-A180 design, and
coreboot appears<br>
to be running off the rails (resets to 0xfffffff0
consistently).<br>
<br>
There is only one dimm in the 0 socket, so
NUMBER_DIMMS_SUPPORTED<br>
is 1 in buildOpts.c, and devicetree.cb has only i2c
address 0xA0.<br>
This appears to work.<br>
<br>
There is no superIO, and hence no serial port (yet; I
will add a USB<br>
based debugger soon),<br>
and this has been removed from devicetree.cb.<br>
<br>
I'm in the process of finding and mapping all the post
codes, but<br>
any wisdom from the community would be appreciated at
this point.<br>
<br>
The post codes are below; it appears to be getting
pretty far along<br>
(though I am<br>
new to coreboot and this may be optimistic).<br>
<br>
The questions I have are:<br>
<br>
- what is going on at the end?<br>
- has dimm memory been successfully configured and
is in use?<br>
- should the vga console be functional at this
time? (no sign of<br>
life there)<br>
<br>
It always resets to 0xfffffff0 at the same point at the
end of the post<br>
codes.<br>
<br>
Thanks in advance,<br>
<br>
Mark Mason<br>
Engineering Design Team<br>
<br>
</blockquote>
<br>
</div>
<div class="">
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
0004600 55 64 e2 e3 65 ab e2 e3 e6 e7 cd ff e2 e3 ce e6<br>
0004620 e6 e6 e7 ec e2 e3 ed e6 e7 b8 cf e6 e7 e4 e4 e5<br>
0004640 e4 e5 9b 9c 9e 9d 7a 7b f8<br>
0004651<br>
<br>
</blockquote>
<br>
</div>
Decode the last three with this:<br>
src/include/console/post_codes.h<br>
<br>
Seems to be loading and jumping to payload. Note that some
payloads configurations will hit watchdog and reset in 60
seconds if they cannot find boot media.<br>
<br>
You can apply the attached patch as a quick hack I recently
made to send coreboot console text to IO port 0x3f8 without
any actual UART hardware.<br>
<br>
If necessary, you can also disable any POST displays in
menuconfig, and change this patch to use IO 0x80. But
listening on IO 0x3f8 may give you output from payload too.<br>
<br>
I'd recommend the USB debug method for any further serious
work.<span class="HOEnZb"><font color="#888888"><br>
<br>
Kyösti<br>
</font></span><br>
--<br>
coreboot mailing list: <a moz-do-not-send="true"
href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a moz-do-not-send="true"
href="http://www.coreboot.org/mailman/listinfo/coreboot"
target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br>
</blockquote>
</div>
<br>
</div>
</blockquote>
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