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<div class="moz-cite-prefix">That would be 543843.<br>
<br>
Cheers,<br>
Sean<br>
<br>
On 06/11/2014 08:09 PM, Mike Hibbett wrote:<br>
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<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi
Sean,<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Would
you have an IBL reference to that
</span>BYT-I_SEC_DUAL_BOOT_PV_GOLD file? I have a look and
couldn’t find it.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Mike.<span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<div style="border:none;border-top:solid #B5C4DF
1.0pt;padding:3.0pt 0cm 0cm 0cm">
<p class="MsoNormal"><b><span
style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:windowtext"
lang="EN-US">From:</span></b><span
style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:windowtext"
lang="EN-US"> coreboot
[<a class="moz-txt-link-freetext" href="mailto:coreboot-bounces@coreboot.org">mailto:coreboot-bounces@coreboot.org</a>]
<b>On Behalf Of </b>Sean McNeil<br>
<b>Sent:</b> 11 June 2014 11:12<br>
<b>To:</b> Gerald Otter<br>
<b>Cc:</b> <a class="moz-txt-link-abbreviated" href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] Intel FSP on Bayley Bay
CRB: No output<o:p></o:p></span></p>
</div>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">Hi Gerald,<br>
<br>
You should either erase the TXE area or replace it with the
correct one from BYT-I_SEC_DUAL_BOOT_PV_GOLD. The TXE within
BIOS will not play nice with anything except the BIOS.<br>
<br>
Cheers,<br>
Sean<br>
<br>
On 06/11/2014 03:16 PM, Gerald Otter wrote:<o:p></o:p></p>
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<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<p class="MsoNormal">Hi all, <o:p></o:p></p>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">indeed, I think I misinterpreted the
original issue, which is not solely due to the wrong/lack
of microcode being loaded.<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">I did not get any output on port 80 (
all zeros ). <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">I just found out this had to do with
the particular intel flash descriptor/txe I’ve been using,
which doesn’t seem to play nice with my coreboot build.<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">I’ve been in contact with someone
outside of the list who sent me a working image after my
initial e-mail. <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">I flashed the build with microcode over
the top 2MB of his image, after which my build worked
fine. <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">I assumed it was the microcode, when it
was actually (partly) due to the wrong txe/fd. <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">When the wrong microcode is loaded, the
4digit display alternates between 0x66 and 0x07, so you’re
right that there should be output in that case as well.<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">Right now I’m not really sure what the
differences are between the working fd/txe I have, and the
non-working fd/txe. <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">If there is any particular version of
the txe/fd that is working while others aren’t, then I’d
love to know. <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">Another option is to erase the fd and
txe and just start it in non-descriptor mode. There are
apparently some downsides to that, but I haven’t looked
into the details of that just yet.<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"> <o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">Gerald<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<div>
<div>
<p class="MsoNormal">On 11 Jun 2014, at 04:09, Sean
McNeil <<a moz-do-not-send="true"
href="mailto:seanmcneil3@gmail.com">seanmcneil3@gmail.com</a>>
wrote:<o:p></o:p></p>
</div>
<p class="MsoNormal"><br>
<br>
<o:p></o:p></p>
<div>
<p class="MsoNormal"><span style="font-size:9.0pt">Hi
Marc,<br>
<br>
There is indeed a port80 4 digit hex display on that
board, so Gerald should be getting something from
that.<br>
<br>
Hi Gerald,<br>
<br>
If you had serial output from the BIOS, then I think
you probably have the UART connected properly. I
always use the microUSB connector, though, with a
standard phone cable to get serial from those
boards. It has an on-board usb to serial adapter.
Coreboot usually sets baud rate to 115200, but it is
configurable. Check your .config:<br>
<br>
CONFIG_CONSOLE_SERIAL=y<br>
CONFIG_TTYS0_BASE=0x3f8<br>
CONFIG_CONSOLE_SERIAL_115200=y<br>
CONFIG_TTYS0_BAUD=115200<br>
CONFIG_TTYS0_LCS=3<br>
CONFIG_POST_IO=y<br>
CONFIG_POST_DEVICE=y<br>
CONFIG_POST_DEVICE_NONE=y<br>
CONFIG_POST_IO_PORT=0x80<br>
<br>
Regardless of these settings, FSP will send info to
the port80 so something should have shown.<br>
<br>
Other things you can check:<br>
<br>
1) Properly configured FSP for BayleyBay with the
bct program. BayleyBay is a non-ECC RAM board and
won't boot with ECC FSP.<br>
2) Have the appropriate microcode for your stepping
of CPU. B0 steppings are harder to get correct and
the microcode is not in git.<br>
<br>
Cheers,<br>
Sean<br>
<br>
On 06/11/2014 03:04 AM, Marc Jones wrote:<br>
<br>
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:9.0pt">Gerald,<br>
<br>
Does the crb have a port80? You should get early
postcodes from<br>
coreboot and the FSP. You are also correct that
there might be<br>
something different in the descriptor.bin that isn't
anticipated. You<br>
may want to use the coreboot util/ifdtool to get a
look at the entire<br>
image.<br>
<br>
Marc<br>
<br>
<br>
On Tue, Jun 3, 2014 at 6:03 AM, Gerald Otter <<a
moz-do-not-send="true"
href="mailto:gerald.otter@gmail.com">gerald.otter@gmail.com</a>>
wrote:<br>
<br>
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:9.0pt">Hi
all,<br>
<br>
I am trying to run coreboot + seabios payload on the
bayley bay crb with the recently committed FSP
integration, but have had no luck so far.<br>
This crb uses the bay trail I (now atom e3800) soc
from intel.<br>
<br>
Following the instructions from commit d75800c7f , I
have built a 2MB image and flashed it to the upper
2MB of the 8MB flash, leaving the TXE / flash
descriptor intact.<br>
I have added the config from the build. The FSP I
used is BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014,
together with the flash descriptor and TXE from the
80.21 bios provided by intel, and vga bios 36.2.2.<br>
Fwiw, I have tried both the 32bit and 64bit releases
of the bios, even though the flash descriptor and
TXE binary seem to be exactly the same.<br>
<br>
The issue I’m running into is that I have no idea if
anything is running at all.<br>
There is no output on the VGA/HDMI ports or uart.<br>
<br>
The legacy uart referred to in the source is working
correctly with the original intel bios, but does not
produce any output with the coreboot image.<br>
I have tried the most common baud rates (115200,
19200, 9600 ) and did some measurements with a scope
in case I got the baud rate wrong, but no cigar.<br>
The uart I’m using is the PCU uart, as opposed to
hsuart1/2 and the superIO uart. This matches with
the configuration in coreboot when compared to the
datasheet, so I’m assuming I got this set up
correctly.<br>
Unfortunately, this is about all the information I
have, so I hope I am missing something obvious when
building the image / flashing it, etc.<br>
<br>
I have also used intel’s flash image tool (fitc) to
build a complete image, thinking that maybe the
flash descriptor needed to contain some specific
information regarding the coreboot image
(size/checksums), but given the original
instructions I wasn’t surprised this didn’t work.<br>
<br>
Thanks in advance!<br>
<br>
<br>
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<br>
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